rggen-vhdl 0.1.0

data/lib/rggen/vhdl/bit_field/type/rof.erb

@@ -0,0 +1,24 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH   => <%= width %>,
+    STORAGE => false
+  )
+  port map (
+    i_clk             => '0',
+    i_rst_n           => '0',
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "0",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => <%= initial_value %>,
+    i_mask            => (others => '1'),
+    o_value           => open,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rof.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  vhdl do
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -0,0 +1,27 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => <%= read_action %>,
+    SW_WRITE_ACTION => <%= write_action %>,
+    HW_CLEAR_WIDTH  => <%= width %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => <%= write_enable %>,
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => <%= clear[loop_variables] %>,
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
+  vhdl do
+    build do
+      input :clear, {
+        name: "i_#{full_name}_clear", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        rs: 'RGGEN_READ_SET',
+        w0s: 'RGGEN_READ_DEFAULT',
+        w1s: 'RGGEN_READ_DEFAULT',
+        ws: 'RGGEN_READ_DEFAULT',
+        wos: 'RGGEN_READ_NONE'
+      }[bit_field.type]
+    end
+
+    def write_action
+      {
+        rs: 'RGGEN_WRITE_NONE',
+        w0s: 'RGGEN_WRITE_0_SET',
+        w1s: 'RGGEN_WRITE_1_SET',
+        ws: 'RGGEN_WRITE_SET',
+        wos: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+
+    def write_enable
+      bit_field.writable? && bin(1, 1) || bin(0, 1)
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.erb

@@ -0,0 +1,26 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => <%= read_action %>,
+    SW_WRITE_ONCE   => <%= write_once %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
+    end
+
+    def write_once
+      [:w1, :wo1].include?(bit_field.type)
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rwc.erb

@@ -0,0 +1,25 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    HW_CLEAR_WIDTH  => 1
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => <%= clear_signal %>,
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rwc.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb

@@ -0,0 +1,25 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH                     => <%= width %>,
+    INITIAL_VALUE             => <%= initial_value %>,
+    SW_WRITE_ENABLE_POLARITY  => <%= control_signal_polarity %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => <%= control_signal %>,
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,33 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}",
+          width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: 'enable', rwl: 'lock' }[bit_field.type]
+    end
+
+    def control_signal_polarity
+      { rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -0,0 +1,24 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH         => <%= width %>,
+    INITIAL_VALUE => <%= initial_value %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => <%= set_signal %>,
+    i_hw_write_data   => <%= value_in[loop_variables] %>,
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rws.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rws) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :set, {
+          name: "i_#{full_name}_set", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_signal
+      reference_bit_field || set[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -0,0 +1,26 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => <%= read_action %>,
+    SW_WRITE_ACTION => <%= write_action %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(
+  :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
+) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      read_set? && 'RGGEN_READ_SET' || 'RGGEN_READ_CLEAR'
+    end
+
+    def read_set?
+      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+    end
+
+    def write_action
+      {
+        w0crs: 'RGGEN_WRITE_0_CLEAR',
+        w0src: 'RGGEN_WRITE_0_SET',
+        w1crs: 'RGGEN_WRITE_1_CLEAR',
+        w1src: 'RGGEN_WRITE_1_SET',
+        wcrs: 'RGGEN_WRITE_CLEAR',
+        wsrc: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,25 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_WRITE_ACTION => <%= write_action %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,22 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def write_action
+      {
+        w0t: 'RGGEN_WRITE_0_TOGGLE',
+        w1t: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.type]
+    end
+  end
+end