rggen-vhdl 0.1.0

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data/CODE_OF_CONDUCT.md

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+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+We as members, contributors, and leaders pledge to make participation in our community a harassment-free experience for everyone, regardless of age, body size, visible or invisible disability, ethnicity, sex characteristics, gender identity and expression, level of experience, education, socio-economic status, nationality, personal appearance, race, religion, or sexual identity and orientation.
+
+We pledge to act and interact in ways that contribute to an open, welcoming, diverse, inclusive, and healthy community.
+
+## Our Standards
+
+Examples of behavior that contributes to a positive environment for our community include:
+
+* Demonstrating empathy and kindness toward other people
+* Being respectful of differing opinions, viewpoints, and experiences
+* Giving and gracefully accepting constructive feedback
+* Accepting responsibility and apologizing to those affected by our mistakes, and learning from the experience
+* Focusing on what is best not just for us as individuals, but for the overall community
+
+Examples of unacceptable behavior include:
+
+* The use of sexualized language or imagery, and sexual attention or
+  advances of any kind
+* Trolling, insulting or derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or email
+  address, without their explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Enforcement Responsibilities
+
+Community leaders are responsible for clarifying and enforcing our standards of acceptable behavior and will take appropriate and fair corrective action in response to any behavior that they deem inappropriate, threatening, offensive, or harmful.
+
+Community leaders have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, and will communicate reasons for moderation decisions when appropriate.
+
+## Scope
+
+This Code of Conduct applies within all community spaces, and also applies when an individual is officially representing the community in public spaces. Examples of representing our community include using an official e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be reported to the community leaders responsible for enforcement at taichi730@gmail.com. All complaints will be reviewed and investigated promptly and fairly.
+
+All community leaders are obligated to respect the privacy and security of the reporter of any incident.
+
+## Enforcement Guidelines
+
+Community leaders will follow these Community Impact Guidelines in determining the consequences for any action they deem in violation of this Code of Conduct:
+
+### 1. Correction
+
+**Community Impact**: Use of inappropriate language or other behavior deemed unprofessional or unwelcome in the community.
+
+**Consequence**: A private, written warning from community leaders, providing clarity around the nature of the violation and an explanation of why the behavior was inappropriate. A public apology may be requested.
+
+### 2. Warning
+
+**Community Impact**: A violation through a single incident or series of actions.
+
+**Consequence**: A warning with consequences for continued behavior. No interaction with the people involved, including unsolicited interaction with those enforcing the Code of Conduct, for a specified period of time. This includes avoiding interactions in community spaces as well as external channels like social media. Violating these terms may lead to a temporary or permanent ban.
+
+### 3. Temporary Ban
+
+**Community Impact**: A serious violation of community standards, including sustained inappropriate behavior.
+
+**Consequence**: A temporary ban from any sort of interaction or public communication with the community for a specified period of time. No public or private interaction with the people involved, including unsolicited interaction with those enforcing the Code of Conduct, is allowed during this period. Violating these terms may lead to a permanent ban.
+
+### 4. Permanent Ban
+
+**Community Impact**: Demonstrating a pattern of violation of community standards, including sustained inappropriate behavior,  harassment of an individual, or aggression toward or disparagement of classes of individuals.
+
+**Consequence**: A permanent ban from any sort of public interaction within the community.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 2.0,
+available at https://www.contributor-covenant.org/version/2/0/code_of_conduct.html.
+
+Community Impact Guidelines were inspired by [Mozilla's code of conduct enforcement ladder](https://github.com/mozilla/diversity).
+
+[homepage]: https://www.contributor-covenant.org
+
+For answers to common questions about this code of conduct, see the FAQ at
+https://www.contributor-covenant.org/faq. Translations are available at https://www.contributor-covenant.org/translations.

data/LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2021 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

data/README.md

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+[![Gem Version](https://badge.fury.io/rb/rggen-vhdl.svg)](https://badge.fury.io/rb/rggen-vhdl)
+[![CI](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml)
+[![Maintainability](https://api.codeclimate.com/v1/badges/d30b2c06ae3d7c0f254a/maintainability)](https://codeclimate.com/github/rggen/rggen-vhdl/maintainability)
+[![codecov](https://codecov.io/gh/rggen/rggen-vhdl/branch/master/graph/badge.svg?token=cyo9R4xCje)](https://codecov.io/gh/rggen/rggen-vhdl)
+[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+
+# RgGen::VHDL
+
+RgGen::VHDL is a RgGen plugin to generate RTL written in VHDL.
+
+## Installation
+
+To install RgGen::VHDL, use the following command:
+
+```
+$ gem install rggen-vhdl
+```
+
+## Usage
+
+You need to tell RgGen to load RgGen::VHDL plugin. There are two ways.
+
+### Using `--plugin` runtime option
+
+```
+$ rggen --plugin rggen-vhdl your_register_map.yml
+```
+
+### Using `RGGEN_PLUGINS` environment variable
+
+```
+$ export RGGEN_PLUGINS=${RGGEN_PLUGINS}:rggen-vhdl
+$ rggen your_register_map.yml
+```
+
+## Using Generated RTL
+
+Generated RTL modules are constructed by using common VHDL modules.
+You need to get them from the GitHub repository and set an envirnment variable to show their location.
+
+* GitHub repository
+    * https://github.com/rggen/rggen-vhdl-rtl.git
+* Environment variable
+    * RGGEN_VHDL_RTL_ROOT
+
+```
+$ git clone https://github.com/rggen/rggen-vhdl-rtl.git
+$ export RGGEN_VHDL_RTL_ROOT=`pwd`/rggen-vhdl-rtl
+```
+
+Then, you can use generated RTL modules with your design. This is an example command.
+
+```
+$ simulator \
+    -f ${RGGEN_VHDL_RTL_ROOT}/compile.f
+    your_csr_0.vhd your_csr_1.vhd your_design.vhd
+```
+
+## Contact
+
+Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
+
+* [GitHub Issue Tracker](https://github.com/rggen/rggen-vhdl/issues)
+* [Chat Room](https://gitter.im/rggen/rggen)
+* [Mailing List](https://groups.google.com/d/forum/rggen)
+* [Mail](mailto:rggen@googlegroups.com)
+
+## Copyright & License
+
+Copyright © 2021 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+
+## Code of Conduct
+
+Everyone interacting in the RgGen::VHDL project's codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen-vhdl/blob/master/CODE_OF_CONDUCT.md).

data/lib/rggen/vhdl.rb

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+# frozen_string_literal: true
+
+require 'rggen/systemverilog'
+require_relative 'vhdl/version'
+require_relative 'vhdl/utility/identifier'
+require_relative 'vhdl/utility/data_object'
+require_relative 'vhdl/utility/local_scope'
+require_relative 'vhdl/utility'
+require_relative 'vhdl/component'
+require_relative 'vhdl/feature'
+require_relative 'vhdl/factories'
+
+module RgGen
+  module VHDL
+    extend Core::Plugin
+
+    setup_plugin :'rggen-vhdl' do |plugin|
+      plugin.register_component :vhdl do
+        component Component, ComponentFactory
+        feature Feature, FeatureFactory
+      end
+
+      plugin.files [
+        'vhdl/bit_field/type',
+        'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
+        'vhdl/bit_field/type/ro',
+        'vhdl/bit_field/type/rof',
+        'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
+        'vhdl/bit_field/type/rw_w1_wo_wo1',
+        'vhdl/bit_field/type/rwc',
+        'vhdl/bit_field/type/rwe_rwl',
+        'vhdl/bit_field/type/rws',
+        'vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+        'vhdl/bit_field/type/w0t_w1t',
+        'vhdl/bit_field/type/w0trg_w1trg',
+        'vhdl/bit_field/type/wrc_wrs',
+        'vhdl/bit_field/vhdl_top',
+        'vhdl/register/type',
+        'vhdl/register/type/external',
+        'vhdl/register/type/indirect',
+        'vhdl/register/vhdl_top',
+        'vhdl/register_block/protocol',
+        'vhdl/register_block/protocol/apb',
+        'vhdl/register_block/protocol/axi4lite',
+        'vhdl/register_block/vhdl_top',
+        'vhdl/register_file/vhdl_top'
+      ]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_feature(:bit_field, :type) do
+  vhdl do
+    base_feature do
+      private
+
+      def full_name
+        bit_field.full_name('_')
+      end
+
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
+      def width
+        bit_field.width
+      end
+
+      def array_size
+        bit_field.array_size
+      end
+
+      def initial_value
+        index = bit_field.initial_value_array? && bit_field.local_index || 0
+        "slice(#{bit_field.initial_value}, #{width}, #{index})"
+      end
+
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
+      def bit_field_valid
+        register.bit_field_valid
+      end
+
+      def bit_field_read_mask
+        register.bit_field_read_mask[lsb, width]
+      end
+
+      def bit_field_write_mask
+        register.bit_field_write_mask[lsb, width]
+      end
+
+      def bit_field_write_data
+        register.bit_field_write_data[lsb, width]
+      end
+
+      def bit_field_read_data
+        register.bit_field_read_data[lsb, width]
+      end
+
+      def bit_field_value
+        register.bit_field_value[lsb, width]
+      end
+
+      def mask
+        reference_bit_field || "(others => '1')"
+      end
+
+      def reference_bit_field
+        bit_field.reference? &&
+          bit_field
+            .find_reference(register_block.bit_fields)
+            .value(bit_field.local_indices, bit_field.reference_width)
+      end
+
+      def loop_variables
+        bit_field.loop_variables
+      end
+    end
+
+    factory do
+      def target_feature_key(_configuration, bit_field)
+        type = bit_field.type
+        target_features.key?(type) && type ||
+          (error "code generator for #{type} bit field type is not implemented")
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

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+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => <%= read_action %>,
+    SW_WRITE_ACTION => <%= write_action %>,
+    HW_SET_WIDTH    => <%= width %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => <%= write_enable %>,
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => <%= set[loop_variables] %>,
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => <%= mask %>,
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => <%= value_out_unmasked %>
+  );

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
+  vhdl do
+    build do
+      input :set, {
+        name: "i_#{full_name}_set", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if bit_field.reference?
+        output :value_unmasked, {
+          name: "o_#{full_name}_unmasked", width: width, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        rc: 'RGGEN_READ_CLEAR',
+        w0c: 'RGGEN_READ_DEFAULT',
+        w1c: 'RGGEN_READ_DEFAULT',
+        wc: 'RGGEN_READ_DEFAULT',
+        woc: 'RGGEN_READ_NONE'
+      }[bit_field.type]
+    end
+
+    def write_action
+      {
+        rc: 'RGGEN_WRITE_NONE',
+        w0c: 'RGGEN_WRITE_0_CLEAR',
+        w1c: 'RGGEN_WRITE_1_CLEAR',
+        wc: 'RGGEN_WRITE_CLEAR',
+        woc: 'RGGEN_WRITE_CLEAR'
+      }[bit_field.type]
+    end
+
+    def write_enable
+      bit_field.writable? && bin(1, 1) || bin(0, 1)
+    end
+
+    def value_out_unmasked
+      bit_field.reference? && value_unmasked[loop_variables] || 'open'
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/ro.erb

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+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH   => <%= width %>,
+    STORAGE => false
+  )
+  port map (
+    i_clk             => '0',
+    i_rst_n           => '0',
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "0",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => <%= reference_or_value_in %>,
+    i_mask            => (others => '1'),
+    o_value           => open,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/ro.rb

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+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :ro) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def reference_or_value_in
+      bit_field.reference? && reference_bit_field || value_in[loop_variables]
+    end
+  end
+end