rggen-systemverilog 0.22.0 → 0.25.1
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +0 -24
- data/lib/rggen/systemverilog/common/factories.rb +1 -1
- data/lib/rggen/systemverilog/common/feature.rb +3 -3
- data/lib/rggen/systemverilog/common/utility.rb +5 -1
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +1 -2
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +16 -4
- data/lib/rggen/systemverilog/common/utility/identifier.rb +32 -23
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +9 -7
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +4 -4
- data/lib/rggen/systemverilog/ral.rb +20 -28
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +37 -44
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +11 -47
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +54 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +44 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb +34 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +16 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +6 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → wrc_wrs.rb} +7 -5
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +52 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +8 -6
- data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -6
- data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +8 -20
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +52 -50
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +3 -7
- data/lib/rggen/systemverilog/rtl/register_index.rb +17 -15
- data/lib/rggen/systemverilog/rtl/register_type.rb +69 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +19 -48
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +0 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +0 -43
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +0 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +0 -32
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +0 -21
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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5
5
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export :total_registers
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6
6
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7
7
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build do
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8
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-
input :clock, {
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9
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-
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10
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-
}
|
11
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-
input :reset, {
|
12
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-
name: 'i_rst_n', data_type: :logic, width: 1
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13
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-
}
|
8
|
+
input :clock, { name: 'i_clk', width: 1 }
|
9
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+
input :reset, { name: 'i_rst_n', width: 1 }
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14
10
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interface :register_if, {
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15
11
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name: 'register_if', interface_type: 'rggen_register_if',
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16
12
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parameter_values: [address_width, bus_width, value_width],
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@@ -23,7 +19,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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23
19
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end
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24
20
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|
25
21
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def total_registers
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26
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-
register_block.files_and_registers.
|
22
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+
register_block.files_and_registers.sum(&:count)
|
27
23
|
end
|
28
24
|
|
29
25
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private
|
@@ -9,7 +9,7 @@ module RgGen
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9
9
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EXPORTED_METHODS = [
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10
10
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:loop_variables, :local_loop_variables,
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11
11
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:local_index, :local_indices,
|
12
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-
:index, :
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12
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+
:index, :inside_loop?
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13
13
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].freeze
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14
14
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15
15
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def self.included(feature)
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@@ -23,7 +23,7 @@ module RgGen
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|
23
23
|
end
|
24
24
|
|
25
25
|
def loop_variables
|
26
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-
(
|
26
|
+
(inside_loop? || nil) &&
|
27
27
|
[*upper_register_file&.loop_variables, *local_loop_variables]
|
28
28
|
end
|
29
29
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|
@@ -50,17 +50,14 @@ module RgGen
|
|
50
50
|
end
|
51
51
|
|
52
52
|
def index(offset_or_offsets = nil)
|
53
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-
|
54
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-
|
55
|
-
|
56
|
-
|
57
|
-
else
|
58
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-
partial_indices.join('+')
|
59
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-
end
|
53
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+
offset_or_offsets
|
54
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+
.yield_self(&method(:index_operands))
|
55
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+
.yield_self(&method(:partial_sums))
|
56
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+
.yield_self(&method(:reduce_indices))
|
60
57
|
end
|
61
58
|
|
62
|
-
def
|
63
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-
component.array? || upper_register_file&.
|
59
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+
def inside_loop?
|
60
|
+
component.array? || upper_register_file&.inside_loop? || false
|
64
61
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end
|
65
62
|
|
66
63
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private
|
@@ -87,12 +84,17 @@ module RgGen
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87
84
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]
|
88
85
|
end
|
89
86
|
|
87
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+
def reduce_indices(indices)
|
88
|
+
if indices.empty? || indices.all?(&method(:integer?))
|
89
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+
indices.sum
|
90
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+
else
|
91
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+
indices.join('+')
|
92
|
+
end
|
93
|
+
end
|
94
|
+
|
90
95
|
def local_register_index(offset)
|
91
96
|
(component.array? || nil) &&
|
92
|
-
|
93
|
-
operands = [component.count(false), offset || local_index]
|
94
|
-
product(operands, true)
|
95
|
-
end
|
97
|
+
product([component.count(false), offset || local_index], true)
|
96
98
|
end
|
97
99
|
|
98
100
|
def product(operands, need_bracket)
|
@@ -0,0 +1,69 @@
|
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1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module RTL
|
6
|
+
module RegisterType
|
7
|
+
include PartialSum
|
8
|
+
|
9
|
+
private
|
10
|
+
|
11
|
+
def readable
|
12
|
+
register.readable? && 1 || 0
|
13
|
+
end
|
14
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+
|
15
|
+
def writable
|
16
|
+
register.writable? && 1 || 0
|
17
|
+
end
|
18
|
+
|
19
|
+
def bus_width
|
20
|
+
configuration.bus_width
|
21
|
+
end
|
22
|
+
|
23
|
+
def address_width
|
24
|
+
register_block.local_address_width
|
25
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+
end
|
26
|
+
|
27
|
+
def offset_address
|
28
|
+
[*register_files, register]
|
29
|
+
.flat_map(&method(:collect_offsets))
|
30
|
+
.yield_self(&method(:partial_sums))
|
31
|
+
.yield_self(&method(:format_offsets))
|
32
|
+
end
|
33
|
+
|
34
|
+
def collect_offsets(component)
|
35
|
+
if component.register_file? && component.array?
|
36
|
+
[component.offset_address, byte_offset(component)]
|
37
|
+
else
|
38
|
+
component.offset_address
|
39
|
+
end
|
40
|
+
end
|
41
|
+
|
42
|
+
def byte_offset(component)
|
43
|
+
"#{component.byte_size(false)}*(#{component.local_index})"
|
44
|
+
end
|
45
|
+
|
46
|
+
def format_offsets(offsets)
|
47
|
+
offsets.map(&method(:format_offset)).join('+')
|
48
|
+
end
|
49
|
+
|
50
|
+
def format_offset(offset)
|
51
|
+
offset.is_a?(Integer) ? hex(offset, address_width) : offset
|
52
|
+
end
|
53
|
+
|
54
|
+
def width
|
55
|
+
register.width
|
56
|
+
end
|
57
|
+
|
58
|
+
def valid_bits
|
59
|
+
bits = register.bit_fields.map(&:bit_map).inject(:|)
|
60
|
+
hex(bits, register.width)
|
61
|
+
end
|
62
|
+
|
63
|
+
def register_index
|
64
|
+
register.local_index || 0
|
65
|
+
end
|
66
|
+
end
|
67
|
+
end
|
68
|
+
end
|
69
|
+
end
|
metadata
CHANGED
@@ -1,43 +1,15 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.25.1
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2021-05-16 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
|
-
- !ruby/object:Gem::Dependency
|
14
|
-
name: docile
|
15
|
-
requirement: !ruby/object:Gem::Requirement
|
16
|
-
requirements:
|
17
|
-
- - ">="
|
18
|
-
- !ruby/object:Gem::Version
|
19
|
-
version: 1.1.5
|
20
|
-
type: :runtime
|
21
|
-
prerelease: false
|
22
|
-
version_requirements: !ruby/object:Gem::Requirement
|
23
|
-
requirements:
|
24
|
-
- - ">="
|
25
|
-
- !ruby/object:Gem::Version
|
26
|
-
version: 1.1.5
|
27
|
-
- !ruby/object:Gem::Dependency
|
28
|
-
name: facets
|
29
|
-
requirement: !ruby/object:Gem::Requirement
|
30
|
-
requirements:
|
31
|
-
- - ">="
|
32
|
-
- !ruby/object:Gem::Version
|
33
|
-
version: '3.0'
|
34
|
-
type: :runtime
|
35
|
-
prerelease: false
|
36
|
-
version_requirements: !ruby/object:Gem::Requirement
|
37
|
-
requirements:
|
38
|
-
- - ">="
|
39
|
-
- !ruby/object:Gem::Version
|
40
|
-
version: '3.0'
|
41
13
|
- !ruby/object:Gem::Dependency
|
42
14
|
name: bundler
|
43
15
|
requirement: !ruby/object:Gem::Requirement
|
@@ -83,7 +55,7 @@ files:
|
|
83
55
|
- lib/rggen/systemverilog/common/utility/structure_definition.rb
|
84
56
|
- lib/rggen/systemverilog/ral.rb
|
85
57
|
- lib/rggen/systemverilog/ral/bit_field/type.rb
|
86
|
-
- lib/rggen/systemverilog/ral/bit_field/type/
|
58
|
+
- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
|
87
59
|
- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
|
88
60
|
- lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
|
89
61
|
- lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
|
@@ -103,37 +75,35 @@ files:
|
|
103
75
|
- lib/rggen/systemverilog/rtl.rb
|
104
76
|
- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
|
105
77
|
- lib/rggen/systemverilog/rtl/bit_field/type.rb
|
106
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
107
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
108
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
|
109
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
|
78
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
|
79
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
|
110
80
|
- lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
|
111
81
|
- lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
|
112
82
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
|
113
83
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
114
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
115
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
84
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
|
85
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
|
116
86
|
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
|
117
87
|
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
|
118
88
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
|
119
89
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
|
120
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
121
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
122
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb
|
123
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
|
90
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
|
91
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
|
124
92
|
- lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
|
125
93
|
- lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
|
126
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
127
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
128
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
|
129
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
|
94
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
|
95
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
|
130
96
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
|
131
97
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
|
132
98
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
|
133
99
|
- lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
|
100
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
|
101
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
|
102
|
+
- lib/rggen/systemverilog/rtl/bit_field_index.rb
|
134
103
|
- lib/rggen/systemverilog/rtl/feature.rb
|
135
104
|
- lib/rggen/systemverilog/rtl/global/array_port_format.rb
|
136
105
|
- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
|
106
|
+
- lib/rggen/systemverilog/rtl/indirect_index.rb
|
137
107
|
- lib/rggen/systemverilog/rtl/partial_sum.rb
|
138
108
|
- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
|
139
109
|
- lib/rggen/systemverilog/rtl/register/type.rb
|
@@ -151,6 +121,7 @@ files:
|
|
151
121
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
|
152
122
|
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
153
123
|
- lib/rggen/systemverilog/rtl/register_index.rb
|
124
|
+
- lib/rggen/systemverilog/rtl/register_type.rb
|
154
125
|
- lib/rggen/systemverilog/rtl/setup.rb
|
155
126
|
- lib/rggen/systemverilog/version.rb
|
156
127
|
homepage: https://github.com/rggen/rggen-systemverilog
|
@@ -169,15 +140,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
169
140
|
requirements:
|
170
141
|
- - ">="
|
171
142
|
- !ruby/object:Gem::Version
|
172
|
-
version: '2.
|
143
|
+
version: '2.5'
|
173
144
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
174
145
|
requirements:
|
175
146
|
- - ">="
|
176
147
|
- !ruby/object:Gem::Version
|
177
148
|
version: '0'
|
178
149
|
requirements: []
|
179
|
-
rubygems_version: 3.
|
150
|
+
rubygems_version: 3.2.3
|
180
151
|
signing_key:
|
181
152
|
specification_version: 4
|
182
|
-
summary: rggen-systemverilog-0.
|
153
|
+
summary: rggen-systemverilog-0.25.1
|
183
154
|
test_files: []
|
@@ -1,15 +0,0 @@
|
|
1
|
-
<%= module_name %> #(
|
2
|
-
<% if [:w0c, :w1c].include?(bit_field.type) %>
|
3
|
-
.CLEAR_VALUE (<%= clear_value %>),
|
4
|
-
<% end %>
|
5
|
-
.WIDTH (<%= width %>),
|
6
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
7
|
-
) u_bit_field (
|
8
|
-
.i_clk (<%= clock %>),
|
9
|
-
.i_rst_n (<%= reset%>),
|
10
|
-
.bit_field_if (<%= bit_field_if %>),
|
11
|
-
.i_set (<%= set[loop_variables] %>),
|
12
|
-
.i_mask (<%= mask %>),
|
13
|
-
.o_value (<%= value_out[loop_variables] %>),
|
14
|
-
.o_value_unmasked (<%= value_out_unmasked %>)
|
15
|
-
);
|
@@ -1,43 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
input :set, {
|
7
|
-
name: "i_#{full_name}_set", data_type: :logic, width: width,
|
8
|
-
array_size: array_size, array_format: array_port_format
|
9
|
-
}
|
10
|
-
output :value_out, {
|
11
|
-
name: "o_#{full_name}", data_type: :logic, width: width,
|
12
|
-
array_size: array_size, array_format: array_port_format
|
13
|
-
}
|
14
|
-
if bit_field.reference?
|
15
|
-
output :value_unmasked, {
|
16
|
-
name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
|
17
|
-
array_size: array_size, array_format: array_port_format
|
18
|
-
}
|
19
|
-
end
|
20
|
-
end
|
21
|
-
|
22
|
-
main_code :bit_field, from_template: true
|
23
|
-
|
24
|
-
private
|
25
|
-
|
26
|
-
def module_name
|
27
|
-
if bit_field.type == :rc
|
28
|
-
'rggen_bit_field_rc'
|
29
|
-
else
|
30
|
-
'rggen_bit_field_w01c'
|
31
|
-
end
|
32
|
-
end
|
33
|
-
|
34
|
-
def clear_value
|
35
|
-
bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
|
36
|
-
end
|
37
|
-
|
38
|
-
def value_out_unmasked
|
39
|
-
(bit_field.reference? || nil) &&
|
40
|
-
value_unmasked[loop_variables]
|
41
|
-
end
|
42
|
-
end
|
43
|
-
end
|
@@ -1,13 +0,0 @@
|
|
1
|
-
<%= module_name %> #(
|
2
|
-
<% if [:w0s, :w1s].include?(bit_field.type) %>
|
3
|
-
.SET_VALUE (<%= set_value %>),
|
4
|
-
<% end %>
|
5
|
-
.WIDTH (<%= width %>),
|
6
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
7
|
-
) u_bit_field (
|
8
|
-
.i_clk (<%= clock %>),
|
9
|
-
.i_rst_n (<%= reset %>),
|
10
|
-
.bit_field_if (<%= bit_field_if %>),
|
11
|
-
.i_clear (<%= clear[loop_variables] %>),
|
12
|
-
.o_value (<%= value_out[loop_variables] %>)
|
13
|
-
);
|
@@ -1,32 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
input :clear, {
|
7
|
-
name: "i_#{full_name}_clear", data_type: :logic, width: width,
|
8
|
-
array_size: array_size, array_format: array_port_format
|
9
|
-
}
|
10
|
-
output :value_out, {
|
11
|
-
name: "o_#{full_name}", data_type: :logic, width: width,
|
12
|
-
array_size: array_size, array_format: array_port_format
|
13
|
-
}
|
14
|
-
end
|
15
|
-
|
16
|
-
main_code :bit_field, from_template: true
|
17
|
-
|
18
|
-
private
|
19
|
-
|
20
|
-
def module_name
|
21
|
-
if bit_field.type == :rs
|
22
|
-
'rggen_bit_field_rs'
|
23
|
-
else
|
24
|
-
'rggen_bit_field_w01s'
|
25
|
-
end
|
26
|
-
end
|
27
|
-
|
28
|
-
def set_value
|
29
|
-
bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
|
30
|
-
end
|
31
|
-
end
|
32
|
-
end
|
@@ -1,10 +0,0 @@
|
|
1
|
-
rggen_bit_field_rwe #(
|
2
|
-
.WIDTH (<%= width %>),
|
3
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
4
|
-
) u_bit_field (
|
5
|
-
.i_clk (<%= clock %>),
|
6
|
-
.i_rst_n (<%= reset %>),
|
7
|
-
.bit_field_if (<%= bit_field_if %>),
|
8
|
-
.i_enable (<%= enable_signal %>),
|
9
|
-
.o_value (<%= value_out[loop_variables] %>)
|
10
|
-
);
|