rggen-systemverilog 0.22.0 → 0.25.1
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +0 -24
- data/lib/rggen/systemverilog/common/factories.rb +1 -1
- data/lib/rggen/systemverilog/common/feature.rb +3 -3
- data/lib/rggen/systemverilog/common/utility.rb +5 -1
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +1 -2
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +16 -4
- data/lib/rggen/systemverilog/common/utility/identifier.rb +32 -23
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +9 -7
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +4 -4
- data/lib/rggen/systemverilog/ral.rb +20 -28
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +37 -44
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +11 -47
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +54 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +44 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb +34 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +16 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +6 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → wrc_wrs.rb} +7 -5
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +52 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +8 -6
- data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -6
- data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +8 -20
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +52 -50
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +3 -7
- data/lib/rggen/systemverilog/rtl/register_index.rb +17 -15
- data/lib/rggen/systemverilog/rtl/register_type.rb +69 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +19 -48
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +0 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +0 -43
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +0 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +0 -32
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +0 -21
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
@@ -1,11 +1,19 @@
|
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1
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-
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1
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+
rggen_bit_field #(
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2
2
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.WIDTH (<%= width %>),
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3
3
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.INITIAL_VALUE (<%= initial_value %>),
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4
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-
.
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5
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-
.
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4
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+
.SW_READ_ACTION (<%= read_action %>),
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5
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+
.SW_WRITE_ONCE (<%= write_once %>)
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6
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) u_bit_field (
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7
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-
.i_clk
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8
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-
.i_rst_n
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9
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-
.bit_field_if
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10
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-
.
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7
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+
.i_clk (<%= clock %>),
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8
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+
.i_rst_n (<%= reset %>),
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9
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+
.bit_field_if (<%= bit_field_if %>),
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10
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+
.i_sw_write_enable ('1),
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11
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+
.i_hw_write_enable ('0),
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12
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+
.i_hw_write_data ('0),
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13
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+
.i_hw_set ('0),
|
14
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+
.i_hw_clear ('0),
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15
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+
.i_value ('0),
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16
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+
.i_mask ('1),
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17
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+
.o_value (<%= value_out[loop_variables] %>),
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+
.o_value_unmasked ()
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11
19
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);
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@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
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4
4
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sv_rtl do
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5
5
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build do
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6
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output :value_out, {
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7
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-
name: "o_#{full_name}",
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7
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+
name: "o_#{full_name}", width: width,
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8
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array_size: array_size, array_format: array_port_format
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9
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}
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10
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end
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@@ -13,8 +13,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
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13
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private
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-
def
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-
bit_field.
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+
def read_action
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+
bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
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18
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end
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19
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20
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def write_once
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@@ -1,10 +1,18 @@
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1
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-
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1
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+
rggen_bit_field #(
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2
2
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.WIDTH (<%= width %>),
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3
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-
.INITIAL_VALUE (<%= initial_value %>)
|
3
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+
.INITIAL_VALUE (<%= initial_value %>),
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4
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+
.HW_CLEAR_WIDTH (1)
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4
5
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) u_bit_field (
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5
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-
.i_clk
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6
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-
.i_rst_n
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7
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-
.bit_field_if
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8
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-
.
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9
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-
.
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6
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+
.i_clk (<%= clock %>),
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7
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+
.i_rst_n (<%= reset %>),
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8
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+
.bit_field_if (<%= bit_field_if %>),
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9
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+
.i_sw_write_enable ('1),
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10
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+
.i_hw_write_enable ('0),
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11
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+
.i_hw_write_data ('0),
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12
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+
.i_hw_set ('0),
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13
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+
.i_hw_clear (<%= clear_signal %>),
|
14
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+
.i_value ('0),
|
15
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+
.i_mask ('1),
|
16
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+
.o_value (<%= value_out[loop_variables] %>),
|
17
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+
.o_value_unmasked ()
|
10
18
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);
|
@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
|
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5
5
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build do
|
6
6
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unless bit_field.reference?
|
7
7
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input :clear, {
|
8
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-
name: "i_#{full_name}_clear",
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8
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+
name: "i_#{full_name}_clear", width: 1,
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9
9
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array_size: array_size, array_format: array_port_format
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10
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}
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11
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end
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output :value_out, {
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-
name: "o_#{full_name}",
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+
name: "o_#{full_name}", width: width,
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14
14
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array_size: array_size, array_format: array_port_format
|
15
15
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}
|
16
16
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end
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@@ -0,0 +1,18 @@
|
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1
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+
rggen_bit_field #(
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2
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+
.WIDTH (<%= width %>),
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3
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+
.INITIAL_VALUE (<%= initial_value %>),
|
4
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+
.SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
|
5
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+
) u_bit_field (
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6
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+
.i_clk (<%= clock %>),
|
7
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+
.i_rst_n (<%= reset %>),
|
8
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+
.bit_field_if (<%= bit_field_if %>),
|
9
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+
.i_sw_write_enable (<%= control_signal %>),
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10
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+
.i_hw_write_enable ('0),
|
11
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+
.i_hw_write_data ('0),
|
12
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+
.i_hw_set ('0),
|
13
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+
.i_hw_clear ('0),
|
14
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+
.i_value ('0),
|
15
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+
.i_mask ('1),
|
16
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+
.o_value (<%= value_out[loop_variables] %>),
|
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+
.o_value_unmasked ()
|
18
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+
);
|
@@ -0,0 +1,34 @@
|
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1
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+
# frozen_string_literal: true
|
2
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+
|
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+
RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
|
4
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+
sv_rtl do
|
5
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+
build do
|
6
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+
unless bit_field.reference?
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+
input :control, {
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8
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+
name: "i_#{full_name}_#{enable_or_lock}", width: 1,
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9
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+
array_size: array_size, array_format: array_port_format
|
10
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+
}
|
11
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+
end
|
12
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+
output :value_out, {
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13
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+
name: "o_#{full_name}", width: width,
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14
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+
array_size: array_size, array_format: array_port_format
|
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+
}
|
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+
end
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+
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main_code :bit_field, from_template: true
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+
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+
private
|
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+
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+
def enable_or_lock
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{ rwe: :enable, rwl: :lock }[bit_field.type]
|
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+
end
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25
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+
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+
def control_signal
|
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+
reference_bit_field || control[loop_variables]
|
28
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+
end
|
29
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+
|
30
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+
def polarity
|
31
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+
{ rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type]
|
32
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+
end
|
33
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+
end
|
34
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+
end
|
@@ -1,11 +1,17 @@
|
|
1
|
-
|
1
|
+
rggen_bit_field #(
|
2
2
|
.WIDTH (<%= width %>),
|
3
3
|
.INITIAL_VALUE (<%= initial_value %>)
|
4
4
|
) u_bit_field (
|
5
|
-
.i_clk
|
6
|
-
.i_rst_n
|
7
|
-
.bit_field_if
|
8
|
-
.
|
9
|
-
.
|
10
|
-
.
|
5
|
+
.i_clk (<%= clock %>),
|
6
|
+
.i_rst_n (<%= reset %>),
|
7
|
+
.bit_field_if (<%= bit_field_if %>),
|
8
|
+
.i_sw_write_enable ('1),
|
9
|
+
.i_hw_write_enable (<%= set_signal %>),
|
10
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+
.i_hw_write_data (<%= value_in[loop_variables] %>),
|
11
|
+
.i_hw_set ('0),
|
12
|
+
.i_hw_clear ('0),
|
13
|
+
.i_value ('0),
|
14
|
+
.i_mask ('1),
|
15
|
+
.o_value (<%= value_out[loop_variables] %>),
|
16
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+
.o_value_unmasked ()
|
11
17
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);
|
@@ -5,16 +5,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
|
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5
5
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build do
|
6
6
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unless bit_field.reference?
|
7
7
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input :set, {
|
8
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-
name: "i_#{full_name}_set",
|
8
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+
name: "i_#{full_name}_set", width: 1,
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9
9
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array_size: array_size, array_format: array_port_format
|
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10
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}
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11
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end
|
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12
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input :value_in, {
|
13
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-
name: "i_#{full_name}",
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13
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+
name: "i_#{full_name}", width: width,
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14
14
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array_size: array_size, array_format: array_port_format
|
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15
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}
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16
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output :value_out, {
|
17
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-
name: "o_#{full_name}",
|
17
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+
name: "o_#{full_name}", width: width,
|
18
18
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array_size: array_size, array_format: array_port_format
|
19
19
|
}
|
20
20
|
end
|
@@ -0,0 +1,19 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.SW_READ_ACTION (<%= read_action %>),
|
5
|
+
.SW_WRITE_ACTION (<%= write_action %>)
|
6
|
+
) u_bit_field (
|
7
|
+
.i_clk (<%= clock %>),
|
8
|
+
.i_rst_n (<%= reset %>),
|
9
|
+
.bit_field_if (<%= bit_field_if %>),
|
10
|
+
.i_sw_write_enable ('1),
|
11
|
+
.i_hw_write_enable ('0),
|
12
|
+
.i_hw_write_data ('0),
|
13
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+
.i_hw_set ('0),
|
14
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+
.i_hw_clear ('0),
|
15
|
+
.i_value ('0),
|
16
|
+
.i_mask ('1),
|
17
|
+
.o_value (<%= value_out[loop_variables] %>),
|
18
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+
.o_value_unmasked ()
|
19
|
+
);
|
@@ -0,0 +1,37 @@
|
|
1
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+
# frozen_string_literal: true
|
2
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+
|
3
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+
RgGen.define_list_item_feature(
|
4
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+
:bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
|
5
|
+
) do
|
6
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+
sv_rtl do
|
7
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+
build do
|
8
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+
output :value_out, {
|
9
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+
name: "o_#{full_name}", width: width,
|
10
|
+
array_size: array_size, array_format: array_port_format
|
11
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+
}
|
12
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+
end
|
13
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+
|
14
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+
main_code :bit_field, from_template: true
|
15
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+
|
16
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+
private
|
17
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+
|
18
|
+
def read_action
|
19
|
+
read_set? && 'RGGEN_READ_SET' || 'RGGEN_READ_CLEAR'
|
20
|
+
end
|
21
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+
|
22
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+
def read_set?
|
23
|
+
[:w0crs, :w1crs, :wcrs].include?(bit_field.type)
|
24
|
+
end
|
25
|
+
|
26
|
+
def write_action
|
27
|
+
{
|
28
|
+
w0crs: 'RGGEN_WRITE_0_CLEAR',
|
29
|
+
w0src: 'RGGEN_WRITE_0_SET',
|
30
|
+
w1crs: 'RGGEN_WRITE_1_CLEAR',
|
31
|
+
w1src: 'RGGEN_WRITE_1_SET',
|
32
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+
wcrs: 'RGGEN_WRITE_CLEAR',
|
33
|
+
wsrc: 'RGGEN_WRITE_SET'
|
34
|
+
}[bit_field.type]
|
35
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+
end
|
36
|
+
end
|
37
|
+
end
|
@@ -1,10 +1,18 @@
|
|
1
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-
|
2
|
-
.
|
3
|
-
.
|
4
|
-
.
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.SW_WRITE_ACTION (<%= write_action %>)
|
5
5
|
) u_bit_field (
|
6
|
-
.i_clk
|
7
|
-
.i_rst_n
|
8
|
-
.bit_field_if
|
9
|
-
.
|
6
|
+
.i_clk (<%= clock %>),
|
7
|
+
.i_rst_n (<%= reset %>),
|
8
|
+
.bit_field_if (<%= bit_field_if %>),
|
9
|
+
.i_sw_write_enable ('1),
|
10
|
+
.i_hw_write_enable ('0),
|
11
|
+
.i_hw_write_data ('0),
|
12
|
+
.i_hw_set ('0),
|
13
|
+
.i_hw_clear ('0),
|
14
|
+
.i_value ('0),
|
15
|
+
.i_mask ('1),
|
16
|
+
.o_value (<%= value_out[loop_variables] %>),
|
17
|
+
.o_value_unmasked ()
|
10
18
|
);
|
@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
output :value_out, {
|
7
|
-
name: "o_#{full_name}",
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
8
|
array_size: array_size, array_format: array_port_format
|
9
9
|
}
|
10
10
|
end
|
@@ -13,8 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
|
|
13
13
|
|
14
14
|
private
|
15
15
|
|
16
|
-
def
|
17
|
-
|
16
|
+
def write_action
|
17
|
+
{
|
18
|
+
w0t: 'RGGEN_WRITE_0_TOGGLE',
|
19
|
+
w1t: 'RGGEN_WRITE_1_TOGGLE'
|
20
|
+
}[bit_field.type]
|
18
21
|
end
|
19
22
|
end
|
20
23
|
end
|
@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
|
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
output :trigger, {
|
7
|
-
name: "o_#{full_name}_trigger",
|
7
|
+
name: "o_#{full_name}_trigger", width: width,
|
8
8
|
array_size: array_size, array_format: array_port_format
|
9
9
|
}
|
10
10
|
end
|
@@ -0,0 +1,18 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.SW_READ_ACTION (<%= read_action %>)
|
5
|
+
) u_bit_field (
|
6
|
+
.i_clk (<%= clock %>),
|
7
|
+
.i_rst_n (<%= reset %>),
|
8
|
+
.bit_field_if (<%= bit_field_if %>),
|
9
|
+
.i_sw_write_enable ('1),
|
10
|
+
.i_hw_write_enable ('0),
|
11
|
+
.i_hw_write_data ('0),
|
12
|
+
.i_hw_set ('0),
|
13
|
+
.i_hw_clear ('0),
|
14
|
+
.i_value ('0),
|
15
|
+
.i_mask ('1),
|
16
|
+
.o_value (<%= value_out[loop_variables] %>),
|
17
|
+
.o_value_unmasked ()
|
18
|
+
);
|
@@ -1,10 +1,10 @@
|
|
1
1
|
# frozen_string_literal: true
|
2
2
|
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
|
4
4
|
sv_rtl do
|
5
5
|
build do
|
6
6
|
output :value_out, {
|
7
|
-
name: "o_#{full_name}",
|
7
|
+
name: "o_#{full_name}", width: width,
|
8
8
|
array_size: array_size, array_format: array_port_format
|
9
9
|
}
|
10
10
|
end
|
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
|
|
13
13
|
|
14
14
|
private
|
15
15
|
|
16
|
-
def
|
17
|
-
|
18
|
-
|
16
|
+
def read_action
|
17
|
+
{
|
18
|
+
wrc: 'RGGEN_READ_CLEAR',
|
19
|
+
wrs: 'RGGEN_READ_SET'
|
20
|
+
}[bit_field.type]
|
19
21
|
end
|
20
22
|
end
|
21
23
|
end
|
@@ -0,0 +1,52 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
module RgGen
|
4
|
+
module SystemVerilog
|
5
|
+
module RTL
|
6
|
+
module BitFieldIndex
|
7
|
+
EXPORTED_METHODS = [
|
8
|
+
:local_index, :local_indices, :loop_variables, :array_size
|
9
|
+
].freeze
|
10
|
+
|
11
|
+
def self.included(feature)
|
12
|
+
feature.module_eval do
|
13
|
+
EXPORTED_METHODS.each { |m| export m }
|
14
|
+
end
|
15
|
+
end
|
16
|
+
|
17
|
+
def local_index
|
18
|
+
create_identifier(local_index_name)
|
19
|
+
end
|
20
|
+
|
21
|
+
def local_indices
|
22
|
+
[*register.local_indices, local_index_name]
|
23
|
+
end
|
24
|
+
|
25
|
+
def loop_variables
|
26
|
+
(inside_loop? || nil) &&
|
27
|
+
[*register.loop_variables, local_index].compact
|
28
|
+
end
|
29
|
+
|
30
|
+
def array_size
|
31
|
+
(inside_loop? || nil) &&
|
32
|
+
[
|
33
|
+
*register_files.flat_map(&:array_size),
|
34
|
+
*register.array_size,
|
35
|
+
*bit_field.sequence_size
|
36
|
+
].compact
|
37
|
+
end
|
38
|
+
|
39
|
+
private
|
40
|
+
|
41
|
+
def local_index_name
|
42
|
+
(bit_field.sequential? || nil) &&
|
43
|
+
loop_index((register.loop_variables&.size || 0) + 1)
|
44
|
+
end
|
45
|
+
|
46
|
+
def inside_loop?
|
47
|
+
register.inside_loop? || bit_field.sequential?
|
48
|
+
end
|
49
|
+
end
|
50
|
+
end
|
51
|
+
end
|
52
|
+
end
|
@@ -16,10 +16,12 @@ module RgGen
|
|
16
16
|
InterfaceInstance.new(attributes, &block)
|
17
17
|
end
|
18
18
|
|
19
|
-
def
|
20
|
-
|
21
|
-
|
22
|
-
|
19
|
+
def create_port(direction, attributes, &block)
|
20
|
+
attributes =
|
21
|
+
{ data_type: 'logic' }
|
22
|
+
.merge(attributes)
|
23
|
+
.merge(direction: direction)
|
24
|
+
DataObject.new(:argument, attributes, &block)
|
23
25
|
end
|
24
26
|
|
25
27
|
def create_if_port(_, attributes, &block)
|
@@ -34,8 +36,8 @@ module RgGen
|
|
34
36
|
|
35
37
|
define_entity :logic, :create_variable, :variable, -> { component }
|
36
38
|
define_entity :interface, :create_if_instance, :variable, -> { component }
|
37
|
-
define_entity :input, :
|
38
|
-
define_entity :output, :
|
39
|
+
define_entity :input, :create_port, :port, -> { register_block }
|
40
|
+
define_entity :output, :create_port, :port, -> { register_block }
|
39
41
|
define_entity :interface_port, :create_if_port, :port, -> { register_block }
|
40
42
|
define_entity :parameter, :create_parameter, :parameter, -> { register_block }
|
41
43
|
define_entity :localparam, :create_parameter, :parameter, -> { component }
|