rggen-systemverilog 0.22.0 → 0.25.1
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +0 -24
- data/lib/rggen/systemverilog/common/factories.rb +1 -1
- data/lib/rggen/systemverilog/common/feature.rb +3 -3
- data/lib/rggen/systemverilog/common/utility.rb +5 -1
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +1 -2
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +16 -4
- data/lib/rggen/systemverilog/common/utility/identifier.rb +32 -23
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +9 -7
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +4 -4
- data/lib/rggen/systemverilog/ral.rb +20 -28
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +37 -44
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +11 -47
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +54 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +44 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb +34 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +16 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb +6 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → wrc_wrs.rb} +7 -5
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +52 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +8 -6
- data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -6
- data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +8 -20
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +52 -50
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +3 -7
- data/lib/rggen/systemverilog/rtl/register_index.rb +17 -15
- data/lib/rggen/systemverilog/rtl/register_type.rb +69 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +19 -48
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +0 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +0 -43
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +0 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +0 -32
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +0 -21
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 4618b040c5d3d57ec1277788e3cfa5cc4363df8c2ddaa2d3d18bec10ed4a203d
|
4
|
+
data.tar.gz: b8af85fb8a83278de85ab9b6bdbe927f5c2e6d62143f7ef7b31088e03d52dccf
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: '092893bb2e1429821c3455575f4eadcbc3ddb2e956e77f1e7bee3ad97b4e97738141d350aa8976b9c0dad1d276af1ddcd51a8c9539d562de8b59bded9be8f934'
|
7
|
+
data.tar.gz: a4b4824e9056ab2acf190869e90dcbe426ef367f267b95259a588e7d66a6c9237b1737caca8c84fd2f9b8afa97a2ba007203823223e8d685e9595d5908153f05
|
data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
|
|
1
1
|
The MIT License (MIT)
|
2
2
|
|
3
|
-
Copyright (c) 2019-
|
3
|
+
Copyright (c) 2019-2021 Taichi Ishitani
|
4
4
|
|
5
5
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
6
6
|
of this software and associated documentation files (the "Software"), to deal
|
data/README.md
CHANGED
@@ -7,7 +7,7 @@
|
|
7
7
|
|
8
8
|
# RgGen::SystemVerilog
|
9
9
|
|
10
|
-
RgGen::SystemVerilog
|
10
|
+
RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
|
11
11
|
|
12
12
|
## Installation
|
13
13
|
|
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
|
|
34
34
|
|
35
35
|
## Copyright & License
|
36
36
|
|
37
|
-
Copyright © 2019-
|
37
|
+
Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
|
38
38
|
|
39
39
|
## Code of Conduct
|
40
40
|
|
@@ -1,8 +1,5 @@
|
|
1
1
|
# frozen_string_literal: true
|
2
2
|
|
3
|
-
require 'docile'
|
4
|
-
require 'facets/kernel/attr_singleton'
|
5
|
-
|
6
3
|
require_relative 'version'
|
7
4
|
|
8
5
|
require_relative 'common/utility/identifier'
|
@@ -21,24 +18,3 @@ require_relative 'common/utility'
|
|
21
18
|
require_relative 'common/component'
|
22
19
|
require_relative 'common/feature'
|
23
20
|
require_relative 'common/factories'
|
24
|
-
|
25
|
-
module RgGen
|
26
|
-
module SystemVerilog
|
27
|
-
module Common
|
28
|
-
def self.register_component(builder, name, feature_class)
|
29
|
-
builder.output_component_registry(name) do
|
30
|
-
register_component [
|
31
|
-
:root, :register_block, :register_file, :register, :bit_field
|
32
|
-
] do |category|
|
33
|
-
component Component, ComponentFactory
|
34
|
-
feature feature_class, FeatureFactory if category != :root
|
35
|
-
end
|
36
|
-
end
|
37
|
-
end
|
38
|
-
|
39
|
-
def self.load_features(features, root)
|
40
|
-
features.each { |feature| require File.join(root, feature) }
|
41
|
-
end
|
42
|
-
end
|
43
|
-
end
|
44
|
-
end
|
@@ -8,7 +8,7 @@ module RgGen
|
|
8
8
|
template_engine Core::OutputBase::ERBEngine
|
9
9
|
|
10
10
|
EntityContext =
|
11
|
-
Struct.new(:entity_type, :
|
11
|
+
Struct.new(:entity_type, :method_name, :declaration_type, :default_layer)
|
12
12
|
|
13
13
|
class << self
|
14
14
|
private
|
@@ -58,7 +58,7 @@ module RgGen
|
|
58
58
|
|
59
59
|
def create_entity(context, name, attributes, &block)
|
60
60
|
merged_attributes = { name: name }.merge(Hash(attributes))
|
61
|
-
__send__(context.
|
61
|
+
__send__(context.method_name, context.entity_type, merged_attributes, &block)
|
62
62
|
end
|
63
63
|
|
64
64
|
def add_entity(context, entity, name, layer)
|
@@ -73,7 +73,7 @@ module RgGen
|
|
73
73
|
|
74
74
|
def add_identifier(entity, name)
|
75
75
|
instance_variable_set("@#{name}", entity.identifier)
|
76
|
-
|
76
|
+
singleton_exec { attr_reader name }
|
77
77
|
export(name)
|
78
78
|
end
|
79
79
|
|
@@ -13,7 +13,7 @@ module RgGen
|
|
13
13
|
private
|
14
14
|
|
15
15
|
def create_identifier(name)
|
16
|
-
Identifier.new(name)
|
16
|
+
name && Identifier.new(name)
|
17
17
|
end
|
18
18
|
|
19
19
|
def assign(lhs, rhs)
|
@@ -45,6 +45,10 @@ module RgGen
|
|
45
45
|
end
|
46
46
|
end
|
47
47
|
|
48
|
+
def all_bits_1
|
49
|
+
"'1"
|
50
|
+
end
|
51
|
+
|
48
52
|
def all_bits_0
|
49
53
|
"'0"
|
50
54
|
end
|
@@ -13,10 +13,14 @@ module RgGen
|
|
13
13
|
private
|
14
14
|
|
15
15
|
def header_code(code)
|
16
|
-
code
|
16
|
+
class_header_begin(code)
|
17
17
|
parameter_declarations(code)
|
18
18
|
class_inheritance(code)
|
19
|
-
code
|
19
|
+
class_header_end(code)
|
20
|
+
end
|
21
|
+
|
22
|
+
def class_header_begin(code)
|
23
|
+
code << ['class', space, name]
|
20
24
|
end
|
21
25
|
|
22
26
|
def parameter_declarations(code)
|
@@ -28,7 +32,11 @@ module RgGen
|
|
28
32
|
|
29
33
|
def class_inheritance(code)
|
30
34
|
return unless base
|
31
|
-
code << [space,
|
35
|
+
code << [space, 'extends', space, base]
|
36
|
+
end
|
37
|
+
|
38
|
+
def class_header_end(code)
|
39
|
+
code << semicolon
|
32
40
|
end
|
33
41
|
|
34
42
|
def pre_body_code(code)
|
@@ -36,7 +44,7 @@ module RgGen
|
|
36
44
|
end
|
37
45
|
|
38
46
|
def footer_code
|
39
|
-
|
47
|
+
'endclass'
|
40
48
|
end
|
41
49
|
end
|
42
50
|
end
|
@@ -19,11 +19,15 @@ module RgGen
|
|
19
19
|
private
|
20
20
|
|
21
21
|
def header_code(code)
|
22
|
-
code
|
22
|
+
function_header_begin(code)
|
23
23
|
return_type_declaration(code)
|
24
|
-
code
|
24
|
+
function_name(code)
|
25
25
|
argument_declarations(code)
|
26
|
-
code
|
26
|
+
function_header_end(code)
|
27
|
+
end
|
28
|
+
|
29
|
+
def function_header_begin(code)
|
30
|
+
code << 'function'
|
27
31
|
end
|
28
32
|
|
29
33
|
def return_type_declaration(code)
|
@@ -31,14 +35,22 @@ module RgGen
|
|
31
35
|
code << [space, return_type.declaration]
|
32
36
|
end
|
33
37
|
|
38
|
+
def function_name(code)
|
39
|
+
code << space << name
|
40
|
+
end
|
41
|
+
|
34
42
|
def argument_declarations(code)
|
35
43
|
wrap(code, '(', ')') do
|
36
44
|
add_declarations_to_header(code, Array(arguments))
|
37
45
|
end
|
38
46
|
end
|
39
47
|
|
48
|
+
def function_header_end(code)
|
49
|
+
code << semicolon
|
50
|
+
end
|
51
|
+
|
40
52
|
def footer_code
|
41
|
-
|
53
|
+
'endfunction'
|
42
54
|
end
|
43
55
|
end
|
44
56
|
end
|
@@ -35,9 +35,9 @@ module RgGen
|
|
35
35
|
@name.to_s
|
36
36
|
end
|
37
37
|
|
38
|
-
def [](array_index_or_lsb, width = nil)
|
38
|
+
def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
|
39
39
|
if array_index_or_lsb
|
40
|
-
__create_new_identifier__(array_index_or_lsb, width)
|
40
|
+
__create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
|
41
41
|
else
|
42
42
|
self
|
43
43
|
end
|
@@ -45,45 +45,53 @@ module RgGen
|
|
45
45
|
|
46
46
|
private
|
47
47
|
|
48
|
-
def __create_new_identifier__(array_index_or_lsb, width)
|
49
|
-
select = __create_select__(array_index_or_lsb, width)
|
50
|
-
|
48
|
+
def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
|
49
|
+
select = __create_select__(array_index_or_lsb, lsb_or_width, width)
|
50
|
+
self.class.new("#{@name}#{select}") do |identifier|
|
51
51
|
identifier.__sub_identifiers__(@sub_identifiers)
|
52
52
|
end
|
53
53
|
end
|
54
54
|
|
55
|
-
def __create_select__(array_index_or_lsb, width)
|
55
|
+
def __create_select__(array_index_or_lsb, lsb_or_width, width)
|
56
56
|
if array_index_or_lsb.is_a?(::Array)
|
57
|
-
__array_select__(array_index_or_lsb)
|
58
|
-
elsif
|
59
|
-
"[#{array_index_or_lsb}+:#{
|
57
|
+
__array_select__(array_index_or_lsb, lsb_or_width, width)
|
58
|
+
elsif lsb_or_width
|
59
|
+
"[#{array_index_or_lsb}+:#{lsb_or_width}]"
|
60
60
|
else
|
61
61
|
"[#{array_index_or_lsb}]"
|
62
62
|
end
|
63
63
|
end
|
64
64
|
|
65
|
-
def __array_select__(array_index)
|
65
|
+
def __array_select__(array_index, lsb, width)
|
66
66
|
if @array_format == :serialized
|
67
|
-
"[#{__serialized_lsb__(array_index)}+:#{@width}]"
|
67
|
+
"[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
|
68
68
|
else
|
69
|
-
|
70
|
-
.map { |index| "[#{index}]" }
|
71
|
-
|
69
|
+
[
|
70
|
+
*array_index.map { |index| "[#{index}]" },
|
71
|
+
lsb && __create_select__(lsb, width, nil)
|
72
|
+
].compact.join
|
72
73
|
end
|
73
74
|
end
|
74
75
|
|
75
|
-
def __serialized_lsb__(array_index)
|
76
|
-
|
76
|
+
def __serialized_lsb__(array_index, lsb)
|
77
|
+
index =
|
78
|
+
array_index
|
79
|
+
.yield_self(&method(:__serialized_index__))
|
80
|
+
.yield_self(&method(:__enclose_index_in_parenthesis))
|
81
|
+
array_lsb = __reduce_array__([@width, index], :*, 1)
|
82
|
+
__reduce_array__([array_lsb, lsb], :+, 0)
|
77
83
|
end
|
78
84
|
|
79
85
|
def __serialized_index__(array_index)
|
80
|
-
|
81
|
-
|
82
|
-
|
83
|
-
|
84
|
-
|
85
|
-
|
86
|
-
|
86
|
+
array_index
|
87
|
+
.reverse
|
88
|
+
.zip(__index_factors__)
|
89
|
+
.map { |i, f| __calc_index_value__(i, f) }
|
90
|
+
.yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
|
91
|
+
end
|
92
|
+
|
93
|
+
def __enclose_index_in_parenthesis(index)
|
94
|
+
integer?(index) && index || "(#{index})"
|
87
95
|
end
|
88
96
|
|
89
97
|
def __index_factors__
|
@@ -97,6 +105,7 @@ module RgGen
|
|
97
105
|
end
|
98
106
|
|
99
107
|
def __reduce_array__(array, operator, initial_value)
|
108
|
+
array = array.compact
|
100
109
|
if array.all?(&method(:integer?))
|
101
110
|
array.reduce(initial_value, &operator)
|
102
111
|
else
|
@@ -17,13 +17,13 @@ module RgGen
|
|
17
17
|
private
|
18
18
|
|
19
19
|
def header_code(code)
|
20
|
-
code << [
|
20
|
+
code << ['generate', space] if @top_scope
|
21
21
|
code << "if (1) begin : #{name}" << nl
|
22
22
|
end
|
23
23
|
|
24
24
|
def footer_code(code)
|
25
|
-
code <<
|
26
|
-
code << [space,
|
25
|
+
code << 'end'
|
26
|
+
code << [space, 'endgenerate'] if @top_scope
|
27
27
|
end
|
28
28
|
|
29
29
|
def pre_body_code(code)
|
@@ -58,10 +58,12 @@ module RgGen
|
|
58
58
|
end
|
59
59
|
|
60
60
|
def post_body_code(code)
|
61
|
-
|
62
|
-
|
63
|
-
|
64
|
-
|
61
|
+
loop_size&.size&.times { generate_for_end(code) }
|
62
|
+
end
|
63
|
+
|
64
|
+
def generate_for_end(code)
|
65
|
+
code.indent -= 2
|
66
|
+
code << 'end' << nl
|
65
67
|
end
|
66
68
|
end
|
67
69
|
end
|
@@ -23,11 +23,15 @@ module RgGen
|
|
23
23
|
private
|
24
24
|
|
25
25
|
def header_code(code)
|
26
|
-
code
|
26
|
+
module_header_begin(code)
|
27
27
|
package_import_declaration(code)
|
28
28
|
parameter_declarations(code)
|
29
29
|
port_declarations(code)
|
30
|
-
code
|
30
|
+
module_header_end(code)
|
31
|
+
end
|
32
|
+
|
33
|
+
def module_header_begin(code)
|
34
|
+
code << 'module' << space << name
|
31
35
|
end
|
32
36
|
|
33
37
|
def package_import_declaration(code)
|
@@ -41,7 +45,7 @@ module RgGen
|
|
41
45
|
def pacakge_import_items
|
42
46
|
Array(@package_imports).map.with_index do |package, i|
|
43
47
|
if i.zero?
|
44
|
-
[
|
48
|
+
['import', "#{package}::*"].join(space)
|
45
49
|
else
|
46
50
|
[space(6), "#{package}::*"].join(space)
|
47
51
|
end
|
@@ -62,12 +66,16 @@ module RgGen
|
|
62
66
|
end
|
63
67
|
end
|
64
68
|
|
69
|
+
def module_header_end(code)
|
70
|
+
code << semicolon
|
71
|
+
end
|
72
|
+
|
65
73
|
def pre_body_code(code)
|
66
74
|
add_declarations_to_body(code, Array(variables))
|
67
75
|
end
|
68
76
|
|
69
77
|
def footer_code
|
70
|
-
|
78
|
+
'endmodule'
|
71
79
|
end
|
72
80
|
end
|
73
81
|
end
|
@@ -30,7 +30,7 @@ module RgGen
|
|
30
30
|
private
|
31
31
|
|
32
32
|
def header_code(code)
|
33
|
-
code << [
|
33
|
+
code << ['package', space, name, semicolon]
|
34
34
|
end
|
35
35
|
|
36
36
|
def pre_body_code(code)
|
@@ -41,18 +41,18 @@ module RgGen
|
|
41
41
|
def package_import_declaration(code)
|
42
42
|
declarations =
|
43
43
|
Array(@package_imports)
|
44
|
-
.map { |package| [
|
44
|
+
.map { |package| ['import', space, package, '::*'] }
|
45
45
|
add_declarations_to_body(code, declarations)
|
46
46
|
end
|
47
47
|
|
48
48
|
def file_include_directives(code)
|
49
49
|
Array(@include_files).each do |file|
|
50
|
-
code << [
|
50
|
+
code << ['`include', space, string(file), nl]
|
51
51
|
end
|
52
52
|
end
|
53
53
|
|
54
54
|
def footer_code
|
55
|
-
|
55
|
+
'endpackage'
|
56
56
|
end
|
57
57
|
end
|
58
58
|
end
|
@@ -7,37 +7,29 @@ require_relative 'ral/register_common'
|
|
7
7
|
module RgGen
|
8
8
|
module SystemVerilog
|
9
9
|
module RAL
|
10
|
-
|
10
|
+
extend Core::Plugin
|
11
11
|
|
12
|
-
|
13
|
-
|
14
|
-
'ral/bit_field/type/reserved_rof',
|
15
|
-
'ral/bit_field/type/rwc_rws',
|
16
|
-
'ral/bit_field/type/rwe_rwl',
|
17
|
-
'ral/bit_field/type/w0trg_w1trg',
|
18
|
-
'ral/register/type',
|
19
|
-
'ral/register/type/external',
|
20
|
-
'ral/register/type/indirect',
|
21
|
-
'ral/register_block/sv_ral_model',
|
22
|
-
'ral/register_block/sv_ral_package',
|
23
|
-
'ral/register_file/sv_ral_model'
|
24
|
-
].freeze
|
12
|
+
setup_plugin :'rggen-sv-ral' do |plugin|
|
13
|
+
plugin.version SystemVerilog::VERSION
|
25
14
|
|
26
|
-
|
27
|
-
|
28
|
-
|
29
|
-
|
30
|
-
def self.register_component(builder)
|
31
|
-
Common.register_component(builder, :sv_ral, Feature)
|
32
|
-
end
|
33
|
-
|
34
|
-
def self.load_features
|
35
|
-
Common.load_features(FEATURES, __dir__)
|
36
|
-
end
|
15
|
+
plugin.register_component :sv_ral do
|
16
|
+
component Common::Component, Common::ComponentFactory
|
17
|
+
feature Feature, Common::FeatureFactory
|
18
|
+
end
|
37
19
|
|
38
|
-
|
39
|
-
|
40
|
-
|
20
|
+
plugin.files [
|
21
|
+
'ral/bit_field/type',
|
22
|
+
'ral/bit_field/type/rof',
|
23
|
+
'ral/bit_field/type/rwc_rws',
|
24
|
+
'ral/bit_field/type/rwe_rwl',
|
25
|
+
'ral/bit_field/type/w0trg_w1trg',
|
26
|
+
'ral/register/type',
|
27
|
+
'ral/register/type/external',
|
28
|
+
'ral/register/type/indirect',
|
29
|
+
'ral/register_block/sv_ral_model',
|
30
|
+
'ral/register_block/sv_ral_package',
|
31
|
+
'ral/register_file/sv_ral_model'
|
32
|
+
]
|
41
33
|
end
|
42
34
|
end
|
43
35
|
end
|