rggen-systemverilog 0.22.0 → 0.25.1

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module IndirectIndex
+        private
+
+        def index_fields
+          @index_fields ||=
+            register.collect_index_fields(register_block.bit_fields)
+        end
+
+        def index_width
+          @index_width ||= index_fields.sum(&:width)
+        end
+
+        def index_values
+          loop_variables = register.local_loop_variables
+          register.index_entries.zip(index_fields).map do |entry, field|
+            if entry.array_index?
+              loop_variables.shift[0, field.width]
+            else
+              hex(entry.value, field.width)
+            end
+          end
+        end
+
+        def indirect_index_assignment
+          assign(indirect_index, concat(index_fields.map(&:value)))
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -7,12 +7,11 @@ module RgGen
         private
 
         def partial_sums(operands)
-          sums =
-            operands
-              .chunk(&method(:integer?))
-              .flat_map(&method(:calc_partial_sum))
-              .reject { |value| integer?(value) && value.zero? }
-          sums.empty? && [0] || sums
+          operands
+            .chunk(&method(:integer?))
+            .flat_map(&method(:calc_partial_sum))
+            .reject { |value| integer?(value) && value.zero? }
+            .tap { |sums| sums.empty? && (sums << 0) }
         end
 
         def calc_partial_sum(kind_ans_values)

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,65 +3,10 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
-      include RgGen::SystemVerilog::RTL::PartialSum
+      include RgGen::SystemVerilog::RTL::RegisterType
 
       private
 
-      def readable
-        register.readable? && 1 || 0
-      end
-
-      def writable
-        register.writable? && 1 || 0
-      end
-
-      def bus_width
-        configuration.bus_width
-      end
-
-      def address_width
-        register_block.local_address_width
-      end
-
-      def offset_address
-        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
-        offsets = partial_sums(offsets)
-        format_offsets(offsets)
-      end
-
-      def collect_offsets(component)
-        if component.register_file? && component.array?
-          [component.offset_address, byte_offset(component)]
-        else
-          component.offset_address
-        end
-      end
-
-      def byte_offset(component)
-        "#{component.byte_size(false)}*(#{component.local_index})"
-      end
-
-      def format_offsets(offsets)
-        offsets.map(&method(:format_offset)).join('+')
-      end
-
-      def format_offset(offset)
-        offset.is_a?(Integer) ? hex(offset, address_width) : offset
-      end
-
-      def width
-        register.width
-      end
-
-      def valid_bits
-        bits = register.bit_fields.map(&:bit_map).inject(:|)
-        hex(bits, register.width)
-      end
-
-      def register_index
-        register.local_index || 0
-      end
-
       def register_if
         register_block.register_if[register.index]
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -11,36 +11,28 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         }
       else
         output :valid, {
-          name: "o_#{register.name}_valid",
-          data_type: :logic, width: 1
+          name: "o_#{register.name}_valid", width: 1
         }
         output :access, {
-          name: "o_#{register.name}_access",
-          data_type: :logic, width: '$bits(rggen_access)'
+          name: "o_#{register.name}_access", width: '$bits(rggen_access)'
         }
         output :address, {
-          name: "o_#{register.name}_address",
-          data_type: :logic, width: address_width
+          name: "o_#{register.name}_address", width: address_width
         }
         output :write_data, {
-          name: "o_#{register.name}_data",
-          data_type: :logic, width: bus_width
+          name: "o_#{register.name}_data", width: bus_width
         }
         output :strobe, {
-          name: "o_#{register.name}_strobe",
-          data_type: :logic, width: byte_width
+          name: "o_#{register.name}_strobe", width: byte_width
         }
         input :ready, {
-          name: "i_#{register.name}_ready",
-          data_type: :logic, width: 1
+          name: "i_#{register.name}_ready", width: 1
         }
         input :status, {
-          name: "i_#{register.name}_status",
-          data_type: :logic, width: 2
+          name: "i_#{register.name}_status", width: 2
         }
         input :read_data, {
-          name: "i_#{register.name}_data",
-          data_type: :logic, width: bus_width
+          name: "i_#{register.name}_data", width: bus_width
         }
         interface :bus_if, {
           name: 'bus_if', interface_type: 'rggen_bus_if',
@@ -71,10 +63,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     private
 
-    def address_width
-      register_block.local_address_width
-    end
-
     def byte_width
       configuration.byte_width
     end

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -2,6 +2,8 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
     build do
       logic :indirect_index, { width: index_width }
     end
@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
       code << indirect_index_assignment << nl
       code << process_template
     end
-
-    private
-
-    def index_fields
-      @index_fields ||=
-        register.collect_index_fields(register_block.bit_fields)
-    end
-
-    def index_width
-      @index_width ||= index_fields.map(&:width).sum
-    end
-
-    def index_values
-      loop_variables = register.local_loop_variables
-      register.index_entries.zip(index_fields).map do |entry, field|
-        if entry.array_index?
-          loop_variables.shift[0, field.width]
-        else
-          hex(entry.value, field.width)
-        end
-      end
-    end
-
-    def indirect_index_assignment
-      assign(indirect_index, concat(index_fields.map(&:value)))
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -2,19 +2,25 @@
 
 RgGen.define_list_feature(:register_block, :protocol) do
   shared_context do
-    def feature_registry(registry = nil)
-      @registry = registry if registry
-      @registry
+    def feature_registry(registry)
+      feature_registries << registry
     end
 
     def available_protocols
-      feature_registry
-        .enabled_features(:protocol)
-        .select(&method(:valid_protocol?))
+      feature_registries
+        .map(&method(:collect_available_protocols)).inject(:&)
     end
 
-    def valid_protocol?(protocol)
-      feature_registry.feature?(:protocol, protocol)
+    private
+
+    def feature_registries
+      @feature_registries ||= []
+    end
+
+    def collect_available_protocols(registry)
+      registry
+        .enabled_features(:protocol)
+        .select { |protocol| registry.feature?(:protocol, protocol) }
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -27,34 +27,34 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
         }
       else
         input :psel, {
-          name: 'i_psel', data_type: :logic, width: 1
+          name: 'i_psel', width: 1
         }
         input :penable, {
-          name: 'i_penable', data_type: :logic, width: 1
+          name: 'i_penable', width: 1
         }
         input :paddr, {
-          name: 'i_paddr', data_type: :logic, width: address_width
+          name: 'i_paddr', width: address_width
         }
         input :pprot, {
-          name: 'i_pprot', data_type: :logic, width: 3
+          name: 'i_pprot', width: 3
         }
         input :pwrite, {
-          name: 'i_pwrite', data_type: :logic, width: 1
+          name: 'i_pwrite', width: 1
         }
         input :pstrb, {
-          name: 'i_pstrb', data_type: :logic, width: byte_width
+          name: 'i_pstrb', width: byte_width
         }
         input :pwdata, {
-          name: 'i_pwdata', data_type: :logic, width: bus_width
+          name: 'i_pwdata', width: bus_width
         }
         output :pready, {
-          name: 'o_pready', data_type: :logic, width: 1
+          name: 'o_pready', width: 1
         }
         output :prdata, {
-          name: 'o_prdata', data_type: :logic, width: bus_width
+          name: 'o_prdata', width: bus_width
         }
         output :pslverr, {
-          name: 'o_pslverr', data_type: :logic, width: 1
+          name: 'o_pslverr', width: 1
         }
         interface :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if',

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -26,73 +26,73 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         }
       else
         input :awvalid, {
-          name: 'i_awvalid', data_type: :logic, width: 1
+          name: 'i_awvalid', width: 1
         }
         output :awready, {
-          name: 'o_awready', data_type: :logic, width: 1
+          name: 'o_awready', width: 1
         }
         input :awid, {
-          name: 'i_awid', data_type: :logic, width: id_port_width
+          name: 'i_awid', width: id_port_width
         }
         input :awaddr, {
-          name: 'i_awaddr', data_type: :logic, width: address_width
+          name: 'i_awaddr', width: address_width
         }
         input :awprot, {
-          name: 'i_awprot', data_type: :logic, width: 3
+          name: 'i_awprot', width: 3
         }
         input :wvalid, {
-          name: 'i_wvalid', data_type: :logic, width: 1
+          name: 'i_wvalid', width: 1
         }
         output :wready, {
-          name: 'o_wready', data_type: :logic, width: 1
+          name: 'o_wready', width: 1
         }
         input :wdata, {
-          name: 'i_wdata', data_type: :logic, width: bus_width
+          name: 'i_wdata', width: bus_width
         }
         input :wstrb, {
-          name: 'i_wstrb', data_type: :logic, width: byte_width
+          name: 'i_wstrb', width: byte_width
         }
         output :bvalid, {
-          name: 'o_bvalid', data_type: :logic, width: 1
+          name: 'o_bvalid', width: 1
         }
         output :bid, {
-          name: 'o_bid', data_type: :logic, width: id_port_width
+          name: 'o_bid', width: id_port_width
         }
         input :bready, {
-          name: 'i_bready', data_type: :logic, width: 1
+          name: 'i_bready', width: 1
         }
         output :bresp, {
-          name: 'o_bresp', data_type: :logic, width: 2
+          name: 'o_bresp', width: 2
         }
         input :arvalid, {
-          name: 'i_arvalid', data_type: :logic, width: 1
+          name: 'i_arvalid', width: 1
         }
         output :arready, {
-          name: 'o_arready', data_type: :logic, width: 1
+          name: 'o_arready', width: 1
         }
         input :arid, {
-          name: 'i_arid', data_type: :logic, width: id_port_width
+          name: 'i_arid', width: id_port_width
         }
         input :araddr, {
-          name: 'i_araddr', data_type: :logic, width: address_width
+          name: 'i_araddr', width: address_width
         }
         input :arprot, {
-          name: 'i_arprot', data_type: :logic, width: 3
+          name: 'i_arprot', width: 3
         }
         output :rvalid, {
-          name: 'o_rvalid', data_type: :logic, width: 1
+          name: 'o_rvalid', width: 1
         }
         input :rready, {
-          name: 'i_rready', data_type: :logic, width: 1
+          name: 'i_rready', width: 1
         }
         output :rid, {
-          name: 'o_rid', data_type: :logic, width: id_port_width
+          name: 'o_rid', width: id_port_width
         }
         output :rdata, {
-          name: 'o_rdata', data_type: :logic, width: bus_width
+          name: 'o_rdata', width: bus_width
         }
         output :rresp, {
-          name: 'o_rresp', data_type: :logic, width: 2
+          name: 'o_rresp', width: 2
         }
         interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
@@ -110,33 +110,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
     main_code :register_block, from_template: true
     main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [axi4lite_if.awvalid, awvalid],
-          [awready, axi4lite_if.awready],
-          [axi4lite_if.awid, awid],
-          [axi4lite_if.awaddr, awaddr],
-          [axi4lite_if.awprot, awprot],
-          [axi4lite_if.wvalid, wvalid],
-          [wready, axi4lite_if.wready],
-          [axi4lite_if.wdata, wdata],
-          [axi4lite_if.wstrb, wstrb],
-          [bvalid, axi4lite_if.bvalid],
-          [axi4lite_if.bready, bready],
-          [bid, axi4lite_if.bid],
-          [bresp, axi4lite_if.bresp],
-          [axi4lite_if.arvalid, arvalid],
-          [arready, axi4lite_if.arready],
-          [axi4lite_if.arid, arid],
-          [axi4lite_if.araddr, araddr],
-          [axi4lite_if.arprot, arprot],
-          [rvalid, axi4lite_if.rvalid],
-          [axi4lite_if.rready, rready],
-          [rid, axi4lite_if.rid],
-          [rdata, axi4lite_if.rdata],
-          [rresp, axi4lite_if.rresp]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
+      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
     end
 
     private
@@ -144,5 +118,33 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     def id_port_width
       "((#{id_width}>0)?#{id_width}:1)"
     end
+
+    def assign_axi4lite_signals(code)
+      [
+        [axi4lite_if.awvalid, awvalid],
+        [awready, axi4lite_if.awready],
+        [axi4lite_if.awid, awid],
+        [axi4lite_if.awaddr, awaddr],
+        [axi4lite_if.awprot, awprot],
+        [axi4lite_if.wvalid, wvalid],
+        [wready, axi4lite_if.wready],
+        [axi4lite_if.wdata, wdata],
+        [axi4lite_if.wstrb, wstrb],
+        [bvalid, axi4lite_if.bvalid],
+        [axi4lite_if.bready, bready],
+        [bid, axi4lite_if.bid],
+        [bresp, axi4lite_if.bresp],
+        [axi4lite_if.arvalid, arvalid],
+        [arready, axi4lite_if.arready],
+        [axi4lite_if.arid, arid],
+        [axi4lite_if.araddr, araddr],
+        [axi4lite_if.arprot, arprot],
+        [rvalid, axi4lite_if.rvalid],
+        [axi4lite_if.rready, rready],
+        [rid, axi4lite_if.rid],
+        [rdata, axi4lite_if.rdata],
+        [rresp, axi4lite_if.rresp]
+      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
+    end
   end
 end