rggen-systemverilog 0.22.0 → 0.25.1

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -29,12 +29,12 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def model_name
         name = helper.model_name
-        name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
+        name.is_a?(Proc) && instance_eval(&name) || name || 'rggen_ral_field'
       end
 
       def constructors
         (bit_field.sequence_size&.times || [nil]).map do |index|
-          macro_call(:rggen_ral_create_field, arguments(index))
+          macro_call('rggen_ral_create_field', arguments(index))
         end
       end
 

data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup RgGen::SystemVerilog::RAL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
   builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -4,57 +4,50 @@ require_relative 'common'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
+require_relative 'rtl/register_type'
+require_relative 'rtl/indirect_index'
+require_relative 'rtl/bit_field_index'
 
 module RgGen
   module SystemVerilog
     module RTL
-      PLUGIN_NAME = :'rggen-sv-rtl'
+      extend Core::Plugin
 
-      FEATURES = [
-        'rtl/bit_field/sv_rtl_top',
-        'rtl/bit_field/type',
-        'rtl/bit_field/type/rc_w0c_w1c',
-        'rtl/bit_field/type/reserved',
-        'rtl/bit_field/type/ro',
-        'rtl/bit_field/type/rof',
-        'rtl/bit_field/type/rs_w0s_w1s',
-        'rtl/bit_field/type/rw_w1_wo_wo1',
-        'rtl/bit_field/type/rwc',
-        'rtl/bit_field/type/rwe',
-        'rtl/bit_field/type/rwl',
-        'rtl/bit_field/type/rws',
-        'rtl/bit_field/type/w0crs_w1crs',
-        'rtl/bit_field/type/w0src_w1src',
-        'rtl/bit_field/type/w0t_w1t',
-        'rtl/bit_field/type/w0trg_w1trg',
-        'rtl/global/array_port_format',
-        'rtl/global/fold_sv_interface_port',
-        'rtl/register/sv_rtl_top',
-        'rtl/register/type',
-        'rtl/register/type/external',
-        'rtl/register/type/indirect',
-        'rtl/register_block/protocol',
-        'rtl/register_block/protocol/apb',
-        'rtl/register_block/protocol/axi4lite',
-        'rtl/register_block/sv_rtl_top',
-        'rtl/register_file/sv_rtl_top'
-      ].freeze
+      setup_plugin :'rggen-sv-rtl' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_rtl, Feature)
-      end
-
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_rtl do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'rtl/bit_field/sv_rtl_top',
+          'rtl/bit_field/type',
+          'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+          'rtl/bit_field/type/ro',
+          'rtl/bit_field/type/rof',
+          'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+          'rtl/bit_field/type/rw_w1_wo_wo1',
+          'rtl/bit_field/type/rwc',
+          'rtl/bit_field/type/rwe_rwl',
+          'rtl/bit_field/type/rws',
+          'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+          'rtl/bit_field/type/w0t_w1t',
+          'rtl/bit_field/type/w0trg_w1trg',
+          'rtl/bit_field/type/wrc_wrs',
+          'rtl/global/array_port_format',
+          'rtl/global/fold_sv_interface_port',
+          'rtl/register/sv_rtl_top',
+          'rtl/register/type',
+          'rtl/register/type/external',
+          'rtl/register/type/indirect',
+          'rtl/register_block/protocol',
+          'rtl/register_block/protocol/apb',
+          'rtl/register_block/protocol/axi4lite',
+          'rtl/register_block/sv_rtl_top',
+          'rtl/register_file/sv_rtl_top'
+        ]
       end
     end
   end

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -2,10 +2,8 @@
 
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
-    export :local_index
-    export :local_indices
-    export :loop_variables
-    export :array_size
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
     export :value
 
     build do
@@ -13,13 +11,13 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       elsif initial_value?
         parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
           array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_lhs
+          default: initial_value_rhs
         }
       end
       interface :bit_field_sub_if, {
@@ -42,31 +40,8 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       code << bit_field_if_connection << nl
     end
 
-    def local_index
-      (index_name = local_index_name) &&
-        create_identifier(index_name)
-    end
-
-    def local_indices
-      [*register.local_indices, local_index_name]
-    end
-
-    def loop_variables
-      (inside_loop? || nil) &&
-        [*register.loop_variables, local_index].compact
-    end
-
-    def array_size
-      (inside_loop? || nil) &&
-        [
-          *register_files.flat_map(&:array_size),
-          *register.array_size,
-          *bit_field.sequence_size
-        ].compact
-    end
-
     def value(offsets = nil, width = nil)
-      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
       register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
@@ -77,14 +52,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       define_method(m) { bit_field.__send__(__method__) }
     end
 
-    def local_index_name
-      (bit_field.sequential? || nil) &&
-        begin
-          depth = (register.loop_variables&.size || 0) + 1
-          loop_index(depth)
-        end
-    end
-
     def register_if(offsets)
       index = register.index(offsets || register.local_indices)
       register_block.register_if[index]
@@ -106,11 +73,11 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         configuration.array_port_format
     end
 
-    def initial_value_lhs
-      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    def initial_value_rhs
+      initial_value_array? && initial_value_array_rhs || sized_initial_value
     end
 
-    def initial_value_array_lhs
+    def initial_value_array_rhs
       if fixed_initial_value?
         array(sized_initial_values)
       elsif initial_value_format == :unpacked
@@ -129,12 +96,9 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
     end
 
-    def inside_loop?
-      register.array? || bit_field.sequential?
-    end
-
     def loop_size
-      (loop_variable = local_index_name) &&
+      loop_variable = local_index
+      loop_variable &&
         { loop_variable => bit_field.sequence_size }
     end
 
@@ -152,7 +116,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     def bit_field_if_connection
       macro_call(
-        :rggen_connect_bit_field_if,
+        'rggen_connect_bit_field_if',
         [
           register.bit_field_if,
           bit_field.bit_field_sub_if,

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -35,8 +35,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def mask
-        reference_bit_field ||
-          hex(2**bit_field.width - 1, bit_field.width)
+        reference_bit_field || all_bits_1
       end
 
       def reference_bit_field

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set[loop_variables] %>),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             (<%= mask %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   (<%= value_out_unmasked %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
+  sv_rtl do
+    build do
+      input :set, {
+        name: "i_#{full_name}_set", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      if bit_field.reference?
+        output :value_unmasked, {
+          name: "o_#{full_name}_unmasked", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        rc: 'RGGEN_READ_CLEAR',
+        w0c: 'RGGEN_READ_DEFAULT',
+        w1c: 'RGGEN_READ_DEFAULT',
+        wc: 'RGGEN_READ_DEFAULT',
+        woc: 'RGGEN_READ_NONE'
+      }[bit_field.type]
+    end
+
+    def write_action
+      {
+        rc: 'RGGEN_WRITE_NONE',
+        w0c: 'RGGEN_WRITE_0_CLEAR',
+        w1c: 'RGGEN_WRITE_1_CLEAR',
+        wc: 'RGGEN_WRITE_CLEAR',
+        woc: 'RGGEN_WRITE_CLEAR'
+      }[bit_field.type]
+    end
+
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
+    end
+
+    def value_out_unmasked
+      (bit_field.reference? || nil) && value_unmasked[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= reference_or_value_in %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", data_type: :logic, width: width,
+          name: "i_#{full_name}", width: width,
           array_size: array_size, array_format: array_port_format
         }
       end

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= initial_value %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= initial_value %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear[loop_variables] %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
+  sv_rtl do
+    build do
+      input :clear, {
+        name: "i_#{full_name}_clear", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        rs: 'RGGEN_READ_SET',
+        w0s: 'RGGEN_READ_DEFAULT',
+        w1s: 'RGGEN_READ_DEFAULT',
+        ws: 'RGGEN_READ_DEFAULT',
+        wos: 'RGGEN_READ_NONE'
+      }[bit_field.type]
+    end
+
+    def write_action
+      {
+        rs: 'RGGEN_WRITE_NONE',
+        w0s: 'RGGEN_WRITE_0_SET',
+        w1s: 'RGGEN_WRITE_1_SET',
+        ws: 'RGGEN_WRITE_SET',
+        wos: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
+    end
+  end
+end