rggen-systemverilog 0.21.1 → 0.25.0

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_rwl #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_lock       (<%= lock_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :lock, {
-          name: "i_#{full_name}_lock", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def lock_signal
-      reference_bit_field || lock[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01crs #(
-  .CLEAR_VALUE    (<%= clear_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01src #(
-  .SET_VALUE      (<%= set_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);