rggen-systemverilog 0.21.1 → 0.25.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +0 -24
- data/lib/rggen/systemverilog/common/factories.rb +1 -1
- data/lib/rggen/systemverilog/common/feature.rb +3 -3
- data/lib/rggen/systemverilog/common/utility.rb +5 -1
- data/lib/rggen/systemverilog/common/utility/class_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +1 -2
- data/lib/rggen/systemverilog/common/utility/function_definition.rb +16 -4
- data/lib/rggen/systemverilog/common/utility/identifier.rb +25 -22
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +9 -7
- data/lib/rggen/systemverilog/common/utility/module_definition.rb +12 -4
- data/lib/rggen/systemverilog/common/utility/package_definition.rb +4 -4
- data/lib/rggen/systemverilog/ral.rb +20 -26
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb +5 -0
- data/lib/rggen/systemverilog/ral/setup.rb +1 -1
- data/lib/rggen/systemverilog/rtl.rb +37 -41
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +11 -47
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +1 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +54 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb +15 -4
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +44 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb +15 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb +34 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb +13 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +19 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +37 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0t_w1t.rb} +7 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb +18 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → wrc_wrs.rb} +7 -5
- data/lib/rggen/systemverilog/rtl/bit_field_index.rb +52 -0
- data/lib/rggen/systemverilog/rtl/feature.rb +8 -6
- data/lib/rggen/systemverilog/rtl/indirect_index.rb +35 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +5 -6
- data/lib/rggen/systemverilog/rtl/register/type.rb +1 -56
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +8 -20
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +2 -26
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -8
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +10 -10
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +52 -50
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +3 -7
- data/lib/rggen/systemverilog/rtl/register_index.rb +17 -15
- data/lib/rggen/systemverilog/rtl/register_type.rb +69 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -1
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +21 -48
- data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb +0 -5
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb +0 -15
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +0 -43
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb +0 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb +0 -7
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb +0 -13
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +0 -32
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +0 -26
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb +0 -10
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb +0 -10
@@ -7,12 +7,11 @@ module RgGen
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private
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def partial_sums(operands)
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-
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sums.empty? && [0] || sums
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operands
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.chunk(&method(:integer?))
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.flat_map(&method(:calc_partial_sum))
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.reject { |value| integer?(value) && value.zero? }
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.tap { |sums| sums.empty? && (sums << 0) }
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end
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def calc_partial_sum(kind_ans_values)
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RgGen.define_list_feature(:register, :type) do
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sv_rtl do
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base_feature do
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include RgGen::SystemVerilog::RTL::
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include RgGen::SystemVerilog::RTL::RegisterType
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private
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def readable
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register.readable? && 1 || 0
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end
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def writable
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register.writable? && 1 || 0
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end
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def bus_width
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configuration.bus_width
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end
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def address_width
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register_block.local_address_width
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end
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def offset_address
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offsets = [*register_files, register].flat_map(&method(:collect_offsets))
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offsets = partial_sums(offsets)
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format_offsets(offsets)
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end
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def collect_offsets(component)
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if component.register_file? && component.array?
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[component.offset_address, byte_offset(component)]
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else
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component.offset_address
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end
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end
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def byte_offset(component)
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"#{component.byte_size(false)}*(#{component.local_index})"
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end
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def format_offsets(offsets)
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offsets.map(&method(:format_offset)).join('+')
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end
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def format_offset(offset)
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offset.is_a?(Integer) ? hex(offset, address_width) : offset
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end
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def width
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register.width
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end
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def valid_bits
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bits = register.bit_fields.map(&:bit_map).inject(:|)
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hex(bits, register.width)
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end
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def register_index
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register.local_index || 0
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end
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def register_if
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register_block.register_if[register.index]
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end
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@@ -11,36 +11,28 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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}
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else
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output :valid, {
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name: "o_#{register.name}_valid",
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data_type: :logic, width: 1
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name: "o_#{register.name}_valid", width: 1
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}
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output :access, {
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name: "o_#{register.name}_access",
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data_type: :logic, width: '$bits(rggen_access)'
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name: "o_#{register.name}_access", width: '$bits(rggen_access)'
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}
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output :address, {
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name: "o_#{register.name}_address",
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data_type: :logic, width: address_width
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name: "o_#{register.name}_address", width: address_width
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}
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output :write_data, {
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name: "o_#{register.name}_data",
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data_type: :logic, width: bus_width
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name: "o_#{register.name}_data", width: bus_width
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}
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output :strobe, {
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name: "o_#{register.name}_strobe",
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data_type: :logic, width: byte_width
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name: "o_#{register.name}_strobe", width: byte_width
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}
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input :ready, {
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name: "i_#{register.name}_ready",
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data_type: :logic, width: 1
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name: "i_#{register.name}_ready", width: 1
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}
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input :status, {
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name: "i_#{register.name}_status",
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data_type: :logic, width: 2
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name: "i_#{register.name}_status", width: 2
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}
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input :read_data, {
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name: "i_#{register.name}_data",
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data_type: :logic, width: bus_width
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name: "i_#{register.name}_data", width: bus_width
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}
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interface :bus_if, {
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name: 'bus_if', interface_type: 'rggen_bus_if',
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@@ -71,10 +63,6 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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private
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def address_width
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register_block.local_address_width
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end
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def byte_width
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configuration.byte_width
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end
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@@ -2,6 +2,8 @@
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RgGen.define_list_item_feature(:register, :type, :indirect) do
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sv_rtl do
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include RgGen::SystemVerilog::RTL::IndirectIndex
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build do
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logic :indirect_index, { width: index_width }
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end
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@@ -10,31 +12,5 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
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code << indirect_index_assignment << nl
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code << process_template
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end
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private
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def index_fields
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@index_fields ||=
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register.collect_index_fields(register_block.bit_fields)
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end
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def index_width
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@index_width ||= index_fields.map(&:width).sum
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end
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def index_values
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loop_variables = register.local_loop_variables
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register.index_entries.zip(index_fields).map do |entry, field|
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if entry.array_index?
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loop_variables.shift[0, field.width]
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else
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hex(entry.value, field.width)
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end
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end
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end
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def indirect_index_assignment
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assign(indirect_index, concat(index_fields.map(&:value)))
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end
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end
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end
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@@ -2,19 +2,25 @@
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RgGen.define_list_feature(:register_block, :protocol) do
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shared_context do
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def feature_registry(registry
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@registry
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def feature_registry(registry)
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feature_registries << registry
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end
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def available_protocols
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.
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.select(&method(:valid_protocol?))
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feature_registries
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.map(&method(:collect_available_protocols)).inject(:&)
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end
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private
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def feature_registries
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@feature_registries ||= []
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end
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def collect_available_protocols(registry)
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registry
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.enabled_features(:protocol)
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.select { |protocol| registry.feature?(:protocol, protocol) }
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end
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end
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@@ -27,34 +27,34 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
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}
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else
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input :psel, {
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name: 'i_psel',
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name: 'i_psel', width: 1
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}
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input :penable, {
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name: 'i_penable',
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name: 'i_penable', width: 1
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}
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input :paddr, {
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name: 'i_paddr',
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name: 'i_paddr', width: address_width
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}
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input :pprot, {
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name: 'i_pprot',
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name: 'i_pprot', width: 3
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}
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input :pwrite, {
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name: 'i_pwrite',
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name: 'i_pwrite', width: 1
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}
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input :pstrb, {
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name: 'i_pstrb',
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name: 'i_pstrb', width: byte_width
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}
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input :pwdata, {
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name: 'i_pwdata',
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name: 'i_pwdata', width: bus_width
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}
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output :pready, {
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name: 'o_pready',
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name: 'o_pready', width: 1
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}
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output :prdata, {
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name: 'o_prdata',
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name: 'o_prdata', width: bus_width
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}
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output :pslverr, {
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name: 'o_pslverr',
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name: 'o_pslverr', width: 1
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}
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interface :apb_if, {
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name: 'apb_if', interface_type: 'rggen_apb_if',
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@@ -26,73 +26,73 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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}
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else
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input :awvalid, {
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name: 'i_awvalid',
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name: 'i_awvalid', width: 1
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}
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output :awready, {
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name: 'o_awready',
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name: 'o_awready', width: 1
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}
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input :awid, {
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name: 'i_awid',
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name: 'i_awid', width: id_port_width
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}
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input :awaddr, {
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name: 'i_awaddr',
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name: 'i_awaddr', width: address_width
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}
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input :awprot, {
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name: 'i_awprot',
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name: 'i_awprot', width: 3
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}
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input :wvalid, {
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name: 'i_wvalid',
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name: 'i_wvalid', width: 1
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}
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output :wready, {
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-
name: 'o_wready',
|
47
|
+
name: 'o_wready', width: 1
|
48
48
|
}
|
49
49
|
input :wdata, {
|
50
|
-
name: 'i_wdata',
|
50
|
+
name: 'i_wdata', width: bus_width
|
51
51
|
}
|
52
52
|
input :wstrb, {
|
53
|
-
name: 'i_wstrb',
|
53
|
+
name: 'i_wstrb', width: byte_width
|
54
54
|
}
|
55
55
|
output :bvalid, {
|
56
|
-
name: 'o_bvalid',
|
56
|
+
name: 'o_bvalid', width: 1
|
57
57
|
}
|
58
58
|
output :bid, {
|
59
|
-
name: 'o_bid',
|
59
|
+
name: 'o_bid', width: id_port_width
|
60
60
|
}
|
61
61
|
input :bready, {
|
62
|
-
name: 'i_bready',
|
62
|
+
name: 'i_bready', width: 1
|
63
63
|
}
|
64
64
|
output :bresp, {
|
65
|
-
name: 'o_bresp',
|
65
|
+
name: 'o_bresp', width: 2
|
66
66
|
}
|
67
67
|
input :arvalid, {
|
68
|
-
name: 'i_arvalid',
|
68
|
+
name: 'i_arvalid', width: 1
|
69
69
|
}
|
70
70
|
output :arready, {
|
71
|
-
name: 'o_arready',
|
71
|
+
name: 'o_arready', width: 1
|
72
72
|
}
|
73
73
|
input :arid, {
|
74
|
-
name: 'i_arid',
|
74
|
+
name: 'i_arid', width: id_port_width
|
75
75
|
}
|
76
76
|
input :araddr, {
|
77
|
-
name: 'i_araddr',
|
77
|
+
name: 'i_araddr', width: address_width
|
78
78
|
}
|
79
79
|
input :arprot, {
|
80
|
-
name: 'i_arprot',
|
80
|
+
name: 'i_arprot', width: 3
|
81
81
|
}
|
82
82
|
output :rvalid, {
|
83
|
-
name: 'o_rvalid',
|
83
|
+
name: 'o_rvalid', width: 1
|
84
84
|
}
|
85
85
|
input :rready, {
|
86
|
-
name: 'i_rready',
|
86
|
+
name: 'i_rready', width: 1
|
87
87
|
}
|
88
88
|
output :rid, {
|
89
|
-
name: 'o_rid',
|
89
|
+
name: 'o_rid', width: id_port_width
|
90
90
|
}
|
91
91
|
output :rdata, {
|
92
|
-
name: 'o_rdata',
|
92
|
+
name: 'o_rdata', width: bus_width
|
93
93
|
}
|
94
94
|
output :rresp, {
|
95
|
-
name: 'o_rresp',
|
95
|
+
name: 'o_rresp', width: 2
|
96
96
|
}
|
97
97
|
interface :axi4lite_if, {
|
98
98
|
name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
|
@@ -110,33 +110,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
|
|
110
110
|
|
111
111
|
main_code :register_block, from_template: true
|
112
112
|
main_code :register_block do |code|
|
113
|
-
|
114
|
-
[
|
115
|
-
[axi4lite_if.awvalid, awvalid],
|
116
|
-
[awready, axi4lite_if.awready],
|
117
|
-
[axi4lite_if.awid, awid],
|
118
|
-
[axi4lite_if.awaddr, awaddr],
|
119
|
-
[axi4lite_if.awprot, awprot],
|
120
|
-
[axi4lite_if.wvalid, wvalid],
|
121
|
-
[wready, axi4lite_if.wready],
|
122
|
-
[axi4lite_if.wdata, wdata],
|
123
|
-
[axi4lite_if.wstrb, wstrb],
|
124
|
-
[bvalid, axi4lite_if.bvalid],
|
125
|
-
[axi4lite_if.bready, bready],
|
126
|
-
[bid, axi4lite_if.bid],
|
127
|
-
[bresp, axi4lite_if.bresp],
|
128
|
-
[axi4lite_if.arvalid, arvalid],
|
129
|
-
[arready, axi4lite_if.arready],
|
130
|
-
[axi4lite_if.arid, arid],
|
131
|
-
[axi4lite_if.araddr, araddr],
|
132
|
-
[axi4lite_if.arprot, arprot],
|
133
|
-
[rvalid, axi4lite_if.rvalid],
|
134
|
-
[axi4lite_if.rready, rready],
|
135
|
-
[rid, axi4lite_if.rid],
|
136
|
-
[rdata, axi4lite_if.rdata],
|
137
|
-
[rresp, axi4lite_if.rresp]
|
138
|
-
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
139
|
-
end
|
113
|
+
configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
|
140
114
|
end
|
141
115
|
|
142
116
|
private
|
@@ -144,5 +118,33 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
|
|
144
118
|
def id_port_width
|
145
119
|
"((#{id_width}>0)?#{id_width}:1)"
|
146
120
|
end
|
121
|
+
|
122
|
+
def assign_axi4lite_signals(code)
|
123
|
+
[
|
124
|
+
[axi4lite_if.awvalid, awvalid],
|
125
|
+
[awready, axi4lite_if.awready],
|
126
|
+
[axi4lite_if.awid, awid],
|
127
|
+
[axi4lite_if.awaddr, awaddr],
|
128
|
+
[axi4lite_if.awprot, awprot],
|
129
|
+
[axi4lite_if.wvalid, wvalid],
|
130
|
+
[wready, axi4lite_if.wready],
|
131
|
+
[axi4lite_if.wdata, wdata],
|
132
|
+
[axi4lite_if.wstrb, wstrb],
|
133
|
+
[bvalid, axi4lite_if.bvalid],
|
134
|
+
[axi4lite_if.bready, bready],
|
135
|
+
[bid, axi4lite_if.bid],
|
136
|
+
[bresp, axi4lite_if.bresp],
|
137
|
+
[axi4lite_if.arvalid, arvalid],
|
138
|
+
[arready, axi4lite_if.arready],
|
139
|
+
[axi4lite_if.arid, arid],
|
140
|
+
[axi4lite_if.araddr, araddr],
|
141
|
+
[axi4lite_if.arprot, arprot],
|
142
|
+
[rvalid, axi4lite_if.rvalid],
|
143
|
+
[axi4lite_if.rready, rready],
|
144
|
+
[rid, axi4lite_if.rid],
|
145
|
+
[rdata, axi4lite_if.rdata],
|
146
|
+
[rresp, axi4lite_if.rresp]
|
147
|
+
].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
|
148
|
+
end
|
147
149
|
end
|
148
150
|
end
|
@@ -5,12 +5,8 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
|
|
5
5
|
export :total_registers
|
6
6
|
|
7
7
|
build do
|
8
|
-
input :clock, {
|
9
|
-
|
10
|
-
}
|
11
|
-
input :reset, {
|
12
|
-
name: 'i_rst_n', data_type: :logic, width: 1
|
13
|
-
}
|
8
|
+
input :clock, { name: 'i_clk', width: 1 }
|
9
|
+
input :reset, { name: 'i_rst_n', width: 1 }
|
14
10
|
interface :register_if, {
|
15
11
|
name: 'register_if', interface_type: 'rggen_register_if',
|
16
12
|
parameter_values: [address_width, bus_width, value_width],
|
@@ -23,7 +19,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
|
|
23
19
|
end
|
24
20
|
|
25
21
|
def total_registers
|
26
|
-
register_block.files_and_registers.
|
22
|
+
register_block.files_and_registers.sum(&:count)
|
27
23
|
end
|
28
24
|
|
29
25
|
private
|