rggen-systemverilog 0.21.1 → 0.25.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2020 Taichi Ishitani
+Copyright (c) 2019-2021 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -7,7 +7,7 @@
 
 # RgGen::SystemVerilog
 
-RgGen::SystemVerilog privides SystemVerilog RTL generator and UVM RAL model generator for RgGen.
+RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.
 
 ## Installation
 
@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common.rb

@@ -1,8 +1,5 @@
 # frozen_string_literal: true
 
-require 'docile'
-require 'facets/kernel/attr_singleton'
-
 require_relative 'version'
 
 require_relative 'common/utility/identifier'
@@ -21,24 +18,3 @@ require_relative 'common/utility'
 require_relative 'common/component'
 require_relative 'common/feature'
 require_relative 'common/factories'
-
-module RgGen
-  module SystemVerilog
-    module Common
-      def self.register_component(builder, name, feature_class)
-        builder.output_component_registry(name) do
-          register_component [
-            :root, :register_block, :register_file, :register, :bit_field
-          ] do |category|
-            component Component, ComponentFactory
-            feature feature_class, FeatureFactory if category != :root
-          end
-        end
-      end
-
-      def self.load_features(features, root)
-        features.each { |feature| require File.join(root, feature) }
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/common/factories.rb

@@ -3,7 +3,7 @@
 module RgGen
   module SystemVerilog
     module Common
-      class ComponentFactory < Core::OutputBase::ComponentFactory
+      class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
       end
 
       class FeatureFactory < Core::OutputBase::FeatureFactory

data/lib/rggen/systemverilog/common/feature.rb

@@ -8,7 +8,7 @@ module RgGen
         template_engine Core::OutputBase::ERBEngine
 
         EntityContext =
-          Struct.new(:entity_type, :method, :declaration_type, :default_layer)
+          Struct.new(:entity_type, :method_name, :declaration_type, :default_layer)
 
         class << self
           private
@@ -58,7 +58,7 @@ module RgGen
 
         def create_entity(context, name, attributes, &block)
           merged_attributes = { name: name }.merge(Hash(attributes))
-          __send__(context.method, context.entity_type, merged_attributes, &block)
+          __send__(context.method_name, context.entity_type, merged_attributes, &block)
         end
 
         def add_entity(context, entity, name, layer)
@@ -73,7 +73,7 @@ module RgGen
 
         def add_identifier(entity, name)
           instance_variable_set("@#{name}", entity.identifier)
-          attr_singleton_reader(name)
+          singleton_exec { attr_reader name }
           export(name)
         end
 

data/lib/rggen/systemverilog/common/utility.rb

@@ -13,7 +13,7 @@ module RgGen
         private
 
         def create_identifier(name)
-          Identifier.new(name)
+          name && Identifier.new(name)
         end
 
         def assign(lhs, rhs)
@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_1
+          "'1"
+        end
+
         def all_bits_0
           "'0"
         end

data/lib/rggen/systemverilog/common/utility/class_definition.rb

@@ -13,10 +13,14 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:class, space, name]
+            class_header_begin(code)
             parameter_declarations(code)
             class_inheritance(code)
-            code << semicolon
+            class_header_end(code)
+          end
+
+          def class_header_begin(code)
+            code << ['class', space, name]
           end
 
           def parameter_declarations(code)
@@ -28,7 +32,11 @@ module RgGen
 
           def class_inheritance(code)
             return unless base
-            code << [space, :extends, space, base]
+            code << [space, 'extends', space, base]
+          end
+
+          def class_header_end(code)
+            code << semicolon
           end
 
           def pre_body_code(code)
@@ -36,7 +44,7 @@ module RgGen
           end
 
           def footer_code
-            :endclass
+            'endclass'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -25,8 +25,7 @@ module RgGen
 
           def declaration
             declaration_snippets
-              .select(&:itself)
-              .reject(&:empty?)
+              .select { |snippet| snippet && !snippet.empty? }
               .join(' ')
           end
 

data/lib/rggen/systemverilog/common/utility/function_definition.rb

@@ -19,11 +19,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << :function
+            function_header_begin(code)
             return_type_declaration(code)
-            code << [space, name]
+            function_name(code)
             argument_declarations(code)
-            code << semicolon
+            function_header_end(code)
+          end
+
+          def function_header_begin(code)
+            code << 'function'
           end
 
           def return_type_declaration(code)
@@ -31,14 +35,22 @@ module RgGen
             code << [space, return_type.declaration]
           end
 
+          def function_name(code)
+            code << space << name
+          end
+
           def argument_declarations(code)
             wrap(code, '(', ')') do
               add_declarations_to_header(code, Array(arguments))
             end
           end
 
+          def function_header_end(code)
+            code << semicolon
+          end
+
           def footer_code
-            :endfunction
+            'endfunction'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -35,9 +35,9 @@ module RgGen
             @name.to_s
           end
 
-          def [](array_index_or_lsb, width = nil)
+          def [](array_index_or_lsb, lsb_or_width = nil, width = nil)
             if array_index_or_lsb
-              __create_new_identifier__(array_index_or_lsb, width)
+              __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
             else
               self
             end
@@ -45,45 +45,47 @@ module RgGen
 
           private
 
-          def __create_new_identifier__(array_index_or_lsb, width)
-            select = __create_select__(array_index_or_lsb, width)
+          def __create_new_identifier__(array_index_or_lsb, lsb_or_width, width)
+            select = __create_select__(array_index_or_lsb, lsb_or_width, width)
             Identifier.new("#{@name}#{select}") do |identifier|
               identifier.__sub_identifiers__(@sub_identifiers)
             end
           end
 
-          def __create_select__(array_index_or_lsb, width)
+          def __create_select__(array_index_or_lsb, lsb_or_width, width)
             if array_index_or_lsb.is_a?(::Array)
-              __array_select__(array_index_or_lsb)
-            elsif width
-              "[#{array_index_or_lsb}+:#{width}]"
+              __array_select__(array_index_or_lsb, lsb_or_width, width)
+            elsif lsb_or_width
+              "[#{array_index_or_lsb}+:#{lsb_or_width}]"
             else
               "[#{array_index_or_lsb}]"
             end
           end
 
-          def __array_select__(array_index)
+          def __array_select__(array_index, lsb, width)
             if @array_format == :serialized
-              "[#{__serialized_lsb__(array_index)}+:#{@width}]"
+              "[#{__serialized_lsb__(array_index, lsb)}+:#{width || @width}]"
             else
-              array_index
-                .map { |index| "[#{index}]" }
-                .join
+              [
+                *array_index.map { |index| "[#{index}]" },
+                lsb && __create_select__(lsb, width, nil)
+              ].compact.join
             end
           end
 
-          def __serialized_lsb__(array_index)
-            __reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
+          def __serialized_lsb__(array_index, lsb)
+            serialized_index = __serialized_index__(array_index)
+            array_lsb = __reduce_array__([@width, serialized_index], :*, 1)
+            __reduce_array__([array_lsb, lsb], :+, 0)
           end
 
           def __serialized_index__(array_index)
-            index_values =
-              array_index
-                .reverse
-                .zip(__index_factors__)
-                .map { |i, f| __calc_index_value__(i, f) }
-            index = __reduce_array__(index_values.reverse, :+, 0)
-            integer?(index) ? index : "(#{index})"
+            array_index
+              .reverse
+              .zip(__index_factors__)
+              .map { |i, f| __calc_index_value__(i, f) }
+              .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
+              .yield_self { |index| integer?(index) && index || "(#{index})" }
           end
 
           def __index_factors__
@@ -97,6 +99,7 @@ module RgGen
           end
 
           def __reduce_array__(array, operator, initial_value)
+            array = array.compact
             if array.all?(&method(:integer?))
               array.reduce(initial_value, &operator)
             else

data/lib/rggen/systemverilog/common/utility/local_scope.rb

@@ -17,13 +17,13 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:generate, space] if @top_scope
+            code << ['generate', space] if @top_scope
             code << "if (1) begin : #{name}" << nl
           end
 
           def footer_code(code)
-            code << :end
-            code << [space, :endgenerate] if @top_scope
+            code << 'end'
+            code << [space, 'endgenerate'] if @top_scope
           end
 
           def pre_body_code(code)
@@ -58,10 +58,12 @@ module RgGen
           end
 
           def post_body_code(code)
-            (loop_size&.size || 0).times do
-              code.indent -= 2
-              code << :end << nl
-            end
+            loop_size&.size&.times { generate_for_end(code) }
+          end
+
+          def generate_for_end(code)
+            code.indent -= 2
+            code << 'end' << nl
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/module_definition.rb

@@ -23,11 +23,15 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:module, space, name]
+            module_header_begin(code)
             package_import_declaration(code)
             parameter_declarations(code)
             port_declarations(code)
-            code << semicolon
+            module_header_end(code)
+          end
+
+          def module_header_begin(code)
+            code << 'module' << space << name
           end
 
           def package_import_declaration(code)
@@ -41,7 +45,7 @@ module RgGen
           def pacakge_import_items
             Array(@package_imports).map.with_index do |package, i|
               if i.zero?
-                [:import, "#{package}::*"].join(space)
+                ['import', "#{package}::*"].join(space)
               else
                 [space(6), "#{package}::*"].join(space)
               end
@@ -62,12 +66,16 @@ module RgGen
             end
           end
 
+          def module_header_end(code)
+            code << semicolon
+          end
+
           def pre_body_code(code)
             add_declarations_to_body(code, Array(variables))
           end
 
           def footer_code
-            :endmodule
+            'endmodule'
           end
         end
       end

data/lib/rggen/systemverilog/common/utility/package_definition.rb

@@ -30,7 +30,7 @@ module RgGen
           private
 
           def header_code(code)
-            code << [:package, space, name, semicolon]
+            code << ['package', space, name, semicolon]
           end
 
           def pre_body_code(code)
@@ -41,18 +41,18 @@ module RgGen
           def package_import_declaration(code)
             declarations =
               Array(@package_imports)
-                .map { |package| [:import, space, package, '::*'] }
+                .map { |package| ['import', space, package, '::*'] }
             add_declarations_to_body(code, declarations)
           end
 
           def file_include_directives(code)
             Array(@include_files).each do |file|
-              code << [:'`include', space, string(file), nl]
+              code << ['`include', space, string(file), nl]
             end
           end
 
           def footer_code
-            :endpackage
+            'endpackage'
           end
         end
       end

data/lib/rggen/systemverilog/ral.rb

@@ -7,35 +7,29 @@ require_relative 'ral/register_common'
 module RgGen
   module SystemVerilog
     module RAL
-      FEATURES = [
-        'ral/bit_field/type',
-        'ral/bit_field/type/reserved_rof',
-        'ral/bit_field/type/rwc_rws',
-        'ral/bit_field/type/rwe_rwl',
-        'ral/bit_field/type/w0trg_w1trg',
-        'ral/register/type',
-        'ral/register/type/external',
-        'ral/register/type/indirect',
-        'ral/register_block/sv_ral_model',
-        'ral/register_block/sv_ral_package',
-        'ral/register_file/sv_ral_model'
-      ].freeze
+      extend Core::Plugin
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_ral, Feature)
-      end
+      setup_plugin :'rggen-sv-ral' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_ral do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'ral/bit_field/type',
+          'ral/bit_field/type/rof',
+          'ral/bit_field/type/rwc_rws',
+          'ral/bit_field/type/rwe_rwl',
+          'ral/bit_field/type/w0trg_w1trg',
+          'ral/register/type',
+          'ral/register/type/external',
+          'ral/register/type/indirect',
+          'ral/register_block/sv_ral_model',
+          'ral/register_block/sv_ral_package',
+          'ral/register_file/sv_ral_model'
+        ]
       end
     end
   end