rggen-systemverilog 0.21.1 → 0.25.0

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -9,7 +9,7 @@ module RgGen
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
           :local_index, :local_indices,
-          :index, :inside_roop?
+          :index, :inside_loop?
         ].freeze
 
         def self.included(feature)
@@ -23,7 +23,7 @@ module RgGen
         end
 
         def loop_variables
-          (inside_roop? || nil) &&
+          (inside_loop? || nil) &&
             [*upper_register_file&.loop_variables, *local_loop_variables]
         end
 
@@ -50,17 +50,14 @@ module RgGen
         end
 
         def index(offset_or_offsets = nil)
-          operands = index_operands(offset_or_offsets)
-          partial_indices = partial_sums(operands)
-          if partial_indices.empty? || partial_indices.all?(&method(:integer?))
-            partial_indices.sum
-          else
-            partial_indices.join('+')
-          end
+          offset_or_offsets
+            .yield_self(&method(:index_operands))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:reduce_indices))
         end
 
-        def inside_roop?
-          component.array? || upper_register_file&.inside_roop? || false
+        def inside_loop?
+          component.array? || upper_register_file&.inside_loop? || false
         end
 
         private
@@ -87,12 +84,17 @@ module RgGen
           ]
         end
 
+        def reduce_indices(indices)
+          if indices.empty? || indices.all?(&method(:integer?))
+            indices.sum
+          else
+            indices.join('+')
+          end
+        end
+
         def local_register_index(offset)
           (component.array? || nil) &&
-            begin
-              operands = [component.count(false), offset || local_index]
-              product(operands, true)
-            end
+            product([component.count(false), offset || local_index], true)
         end
 
         def product(operands, need_bracket)

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -0,0 +1,69 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module RegisterType
+        include PartialSum
+
+        private
+
+        def readable
+          register.readable? && 1 || 0
+        end
+
+        def writable
+          register.writable? && 1 || 0
+        end
+
+        def bus_width
+          configuration.bus_width
+        end
+
+        def address_width
+          register_block.local_address_width
+        end
+
+        def offset_address
+          [*register_files, register]
+            .flat_map(&method(:collect_offsets))
+            .yield_self(&method(:partial_sums))
+            .yield_self(&method(:format_offsets))
+        end
+
+        def collect_offsets(component)
+          if component.register_file? && component.array?
+            [component.offset_address, byte_offset(component)]
+          else
+            component.offset_address
+          end
+        end
+
+        def byte_offset(component)
+          "#{component.byte_size(false)}*(#{component.local_index})"
+        end
+
+        def format_offsets(offsets)
+          offsets.map(&method(:format_offset)).join('+')
+        end
+
+        def format_offset(offset)
+          offset.is_a?(Integer) ? hex(offset, address_width) : offset
+        end
+
+        def width
+          register.width
+        end
+
+        def valid_bits
+          bits = register.bit_fields.map(&:bit_map).inject(:|)
+          hex(bits, register.width)
+        end
+
+        def register_index
+          register.local_index || 0
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.21.1'
+    VERSION = '0.25.0'
   end
 end

metadata

@@ -1,43 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.21.1
+  version: 0.25.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-24 00:00:00.000000000 Z
+date: 2021-02-28 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: docile
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
-- !ruby/object:Gem::Dependency
-  name: facets
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.0'
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -83,7 +55,7 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
-- lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/ral/bit_field/type/w0trg_w1trg.rb
@@ -103,35 +75,35 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
+- lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
+- lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register/type.rb
@@ -149,6 +121,7 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/register_index.rb
+- lib/rggen/systemverilog/rtl/register_type.rb
 - lib/rggen/systemverilog/rtl/setup.rb
 - lib/rggen/systemverilog/version.rb
 homepage: https://github.com/rggen/rggen-systemverilog
@@ -167,15 +140,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.4'
+      version: '2.5'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.1.2
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.21.1
+summary: rggen-systemverilog-0.25.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/reserved_rof.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:reserved, :rof]) do
-  sv_ral { access 'RO' }
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb

@@ -1,15 +0,0 @@
-<%= module_name %> #(
-<% if [:w0c, :w1c].include?(bit_field.type) %>
-  .CLEAR_VALUE    (<%= clear_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk            (<%= clock %>),
-  .i_rst_n          (<%= reset%>),
-  .bit_field_if     (<%= bit_field_if %>),
-  .i_set            (<%= set[loop_variables] %>),
-  .i_mask           (<%= mask %>),
-  .o_value          (<%= value_out[loop_variables] %>),
-  .o_value_unmasked (<%= value_out_unmasked %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb

@@ -1,43 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
-  sv_rtl do
-    build do
-      input :set, {
-        name: "i_#{full_name}_set", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      if bit_field.reference?
-        output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
-    end
-
-    def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
-    end
-
-    def value_out_unmasked
-      (bit_field.reference? || nil) &&
-        value_unmasked[loop_variables]
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb

@@ -1,3 +0,0 @@
-rggen_bit_field_reserved u_bit_field (
-  .bit_field_if (<%= bit_field_if %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
-  sv_rtl do
-    main_code :bit_field, from_template: true
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb

@@ -1,13 +0,0 @@
-<%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
-  .SET_VALUE      (<%= set_value %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb

@@ -1,32 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
-  sv_rtl do
-    build do
-      input :clear, {
-        name: "i_#{full_name}_clear", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
-    end
-
-    def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_rwe #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_enable     (<%= enable_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -1,26 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
-  sv_rtl do
-    build do
-      unless bit_field.reference?
-        input :enable, {
-          name: "i_#{full_name}_enable", data_type: :logic, width: 1,
-          array_size: array_size, array_format: array_port_format
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def enable_signal
-      reference_bit_field || enable[loop_variables]
-    end
-  end
-end