rggen-systemverilog 0.21.1 → 0.25.0

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb

@@ -1,11 +1,19 @@
-rggen_bit_field_rw_wo #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .WRITE_ONLY     (<%= write_only %>),
-  .WRITE_ONCE     (<%= write_once %>)
+  .SW_READ_ACTION (<%= read_action %>),
+  .SW_WRITE_ONCE  (<%= write_once %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end
@@ -13,8 +13,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
 
     private
 
-    def write_only
-      bit_field.write_only? && 1 || 0
+    def read_action
+      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
     end
 
     def write_once

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwc #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear_signal %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", data_type: :logic, width: 1,
+          name: "i_#{full_name}_clear", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.erb

@@ -0,0 +1,18 @@
+rggen_bit_field #(
+  .WIDTH                    (<%= width %>),
+  .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_ENABLE_POLARITY (<%= polarity %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= control_signal %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: :enable, rwl: :lock }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+
+    def polarity
+      { rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,11 +1,17 @@
-rggen_bit_field_rws #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_set        (<%= set_signal %>),
-  .i_value      (<%= value_in[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= set_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -5,16 +5,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", data_type: :logic, width: 1,
+          name: "i_#{full_name}_set", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", data_type: :logic, width: width,
+        name: "i_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(
+  :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
+) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      read_set? && 'RGGEN_READ_SET' || 'RGGEN_READ_CLEAR'
+    end
+
+    def read_set?
+      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+    end
+
+    def write_action
+      {
+        w0crs: 'RGGEN_WRITE_0_CLEAR',
+        w0src: 'RGGEN_WRITE_0_SET',
+        w1crs: 'RGGEN_WRITE_1_CLEAR',
+        w1src: 'RGGEN_WRITE_1_SET',
+        wcrs: 'RGGEN_WRITE_CLEAR',
+        wsrc: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,18 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0t_w1t.rb}

@@ -1,10 +1,10 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
 
     private
 
-    def clear_value
-      value = (bit_field.type == :w0crs && 0) || 1
-      bin(value, 1)
+    def write_action
+      {
+        w0t: 'RGGEN_WRITE_0_TOGGLE',
+        w1t: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.type]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", data_type: :logic, width: width,
+        name: "o_#{full_name}_trigger", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,18 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (<%= read_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → wrc_wrs.rb}

@@ -1,10 +1,10 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
+        name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format
       }
     end
@@ -13,9 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
 
     private
 
-    def set_value
-      value = (bit_field.type == :w0src && 0) || 1
-      bin(value, 1)
+    def read_action
+      {
+        wrc: 'RGGEN_READ_CLEAR',
+        wrs: 'RGGEN_READ_SET'
+      }[bit_field.type]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module BitFieldIndex
+        EXPORTED_METHODS = [
+          :local_index, :local_indices, :loop_variables, :array_size
+        ].freeze
+
+        def self.included(feature)
+          feature.module_eval do
+            EXPORTED_METHODS.each { |m| export m }
+          end
+        end
+
+        def local_index
+          create_identifier(local_index_name)
+        end
+
+        def local_indices
+          [*register.local_indices, local_index_name]
+        end
+
+        def loop_variables
+          (inside_loop? || nil) &&
+            [*register.loop_variables, local_index].compact
+        end
+
+        def array_size
+          (inside_loop? || nil) &&
+            [
+              *register_files.flat_map(&:array_size),
+              *register.array_size,
+              *bit_field.sequence_size
+            ].compact
+        end
+
+        private
+
+        def local_index_name
+          (bit_field.sequential? || nil) &&
+            loop_index((register.loop_variables&.size || 0) + 1)
+        end
+
+        def inside_loop?
+          register.inside_loop? || bit_field.sequential?
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -16,10 +16,12 @@ module RgGen
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes, &block)
-          DataObject.new(
-            :argument, attributes.merge(direction: direction), &block
-          )
+        def create_port(direction, attributes, &block)
+          attributes =
+            { data_type: 'logic' }
+              .merge(attributes)
+              .merge(direction: direction)
+          DataObject.new(:argument, attributes, &block)
         end
 
         def create_if_port(_, attributes, &block)
@@ -34,8 +36,8 @@ module RgGen
 
         define_entity :logic, :create_variable, :variable, -> { component }
         define_entity :interface, :create_if_instance, :variable, -> { component }
-        define_entity :input, :create_argument, :port, -> { register_block }
-        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :input, :create_port, :port, -> { register_block }
+        define_entity :output, :create_port, :port, -> { register_block }
         define_entity :interface_port, :create_if_port, :port, -> { register_block }
         define_entity :parameter, :create_parameter, :parameter, -> { register_block }
         define_entity :localparam, :create_parameter, :parameter, -> { component }

data/lib/rggen/systemverilog/rtl/indirect_index.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module IndirectIndex
+        private
+
+        def index_fields
+          @index_fields ||=
+            register.collect_index_fields(register_block.bit_fields)
+        end
+
+        def index_width
+          @index_width ||= index_fields.sum(&:width)
+        end
+
+        def index_values
+          loop_variables = register.local_loop_variables
+          register.index_entries.zip(index_fields).map do |entry, field|
+            if entry.array_index?
+              loop_variables.shift[0, field.width]
+            else
+              hex(entry.value, field.width)
+            end
+          end
+        end
+
+        def indirect_index_assignment
+          assign(indirect_index, concat(index_fields.map(&:value)))
+        end
+      end
+    end
+  end
+end