rggen-systemverilog 0.15.0 → 0.20.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +9 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +8 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +23 -19
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +12 -54
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +92 -16
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +5 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +24 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +13 -16
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +2 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +4 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +30 -5
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +5 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +6 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -9
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +0 -14
@@ -5,17 +5,16 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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5
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export :total_registers
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6
6
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build do
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-
input :
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+
input :clock, {
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name: 'i_clk', data_type: :logic, width: 1
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10
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}
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-
input :
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+
input :reset, {
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name: 'i_rst_n', data_type: :logic, width: 1
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}
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-
interface :
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+
interface :register_if, {
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name: 'register_if', interface_type: 'rggen_register_if',
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parameter_values: [address_width, bus_width, value_width],
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-
array_size: [total_registers],
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-
variables: ['value']
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+
array_size: [total_registers], variables: ['value']
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}
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end
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20
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@@ -24,10 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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23
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end
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24
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def total_registers
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-
register_block
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-
.registers
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-
.map(&:count)
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-
.inject(:+)
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+
register_block.files_and_registers.map(&:count).sum
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27
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end
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private
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@@ -68,19 +64,21 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
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end
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65
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def parameters
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-
register_block.declarations
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+
register_block.declarations[:parameter]
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68
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end
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69
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def ports
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-
register_block.declarations
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+
register_block.declarations[:port]
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end
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73
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def variables
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-
register_block.declarations
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+
register_block.declarations[:variable]
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76
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end
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77
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def sv_module_body(code)
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-
register_block
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+
{ register_block: nil, register_file: 1 }.each do |kind, depth|
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+
register_block.generate_code(code, kind, :top_down, depth)
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end
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end
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end
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84
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end
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@@ -0,0 +1,30 @@
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+
# frozen_string_literal: true
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+
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+
RgGen.define_simple_feature(:register_file, :sv_rtl_top) do
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sv_rtl do
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5
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include RgGen::SystemVerilog::RTL::RegisterIndex
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+
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main_code :register_file do
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8
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+
local_scope("g_#{register_file.name}") do |scope|
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9
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scope.top_scope top_scope?
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scope.loop_size loop_size
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scope.body(&method(:body_code))
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end
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end
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+
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private
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+
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def top_scope?
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register_file(:upper).nil?
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end
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+
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def loop_size
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22
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(register_file.array? || nil) &&
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local_loop_variables.zip(register_file.array_size).to_h
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+
end
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+
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+
def body_code(code)
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register_file.generate_code(code, :register_file, :top_down, 1)
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end
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29
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end
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end
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@@ -0,0 +1,112 @@
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1
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+
# frozen_string_literal: true
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+
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3
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+
module RgGen
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module SystemVerilog
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5
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module RTL
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6
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+
module RegisterIndex
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7
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include PartialSum
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8
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+
|
9
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EXPORTED_METHODS = [
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10
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:loop_variables, :local_loop_variables,
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:local_index, :local_indices,
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12
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:index, :inside_roop?
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].freeze
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14
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+
|
15
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+
def self.included(feature)
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feature.module_eval do
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EXPORTED_METHODS.each { |m| export m }
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+
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+
pre_build do
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20
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@base_index = files_and_registers.sum(&:count)
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+
end
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22
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+
end
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23
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+
end
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24
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+
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+
def loop_variables
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26
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(inside_roop? || nil) &&
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27
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+
[*upper_register_file&.loop_variables, *local_loop_variables]
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+
end
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29
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+
|
30
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+
def local_loop_variables
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31
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+
(component.array? || nil) &&
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32
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+
begin
|
33
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+
start_depth = (upper_register_file&.loop_variables&.size || 0) + 1
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34
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+
Array.new(component.array_size.size) do |i|
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35
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create_identifier(loop_index(i + start_depth))
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end
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37
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+
end
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+
end
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39
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+
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+
def local_index
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41
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+
(component.array? || nil) &&
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42
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+
local_index_coefficients
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43
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+
.zip(local_loop_variables)
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44
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+
.map { |operands| product(operands, false) }
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+
.join('+')
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46
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+
end
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47
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+
|
48
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+
def local_indices
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49
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+
[*upper_register_file&.local_indices, local_index]
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+
end
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51
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+
|
52
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+
def index(offset_or_offsets = nil)
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53
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+
operands = index_operands(offset_or_offsets)
|
54
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+
partial_indices = partial_sums(operands)
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55
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+
if partial_indices.empty? || partial_indices.all?(&method(:integer?))
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56
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+
partial_indices.sum
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57
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+
else
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58
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+
partial_indices.join('+')
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59
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+
end
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60
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+
end
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61
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+
|
62
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+
def inside_roop?
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63
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+
component.array? || upper_register_file&.inside_roop? || false
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64
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+
end
|
65
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+
|
66
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+
private
|
67
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+
|
68
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+
def upper_register_file
|
69
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+
component.register_file
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70
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+
end
|
71
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+
|
72
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+
def local_index_coefficients
|
73
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+
coefficients = []
|
74
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+
component.array_size.reverse.inject(1) do |total, size|
|
75
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+
coefficients.unshift(total)
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76
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+
total * size
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77
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+
end
|
78
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+
coefficients
|
79
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+
end
|
80
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+
|
81
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+
def index_operands(offset_or_offsets)
|
82
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+
offsets = offset_or_offsets && Array(offset_or_offsets)
|
83
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+
[
|
84
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+
*upper_register_file&.index(offsets&.slice(0..-2)),
|
85
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+
@base_index,
|
86
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+
*local_register_index(offsets&.slice(-1))
|
87
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+
]
|
88
|
+
end
|
89
|
+
|
90
|
+
def local_register_index(offset)
|
91
|
+
(component.array? || nil) &&
|
92
|
+
begin
|
93
|
+
operands = [component.count(false), offset || local_index]
|
94
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+
product(operands, true)
|
95
|
+
end
|
96
|
+
end
|
97
|
+
|
98
|
+
def product(operands, need_bracket)
|
99
|
+
if operands.all?(&method(:integer?))
|
100
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+
operands.reduce(:*)
|
101
|
+
elsif operands.first == 1
|
102
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+
operands.last
|
103
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+
elsif need_bracket
|
104
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+
"#{operands.first}*(#{operands.last})"
|
105
|
+
else
|
106
|
+
operands.join('*')
|
107
|
+
end
|
108
|
+
end
|
109
|
+
end
|
110
|
+
end
|
111
|
+
end
|
112
|
+
end
|
@@ -8,6 +8,7 @@ RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
|
|
8
8
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]
|
9
9
|
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
10
10
|
builder.enable :register_block, :protocol, [:apb, :axi4lite]
|
11
|
+
builder.enable :register_file, [:sv_rtl_top]
|
11
12
|
builder.enable :register, [:sv_rtl_top]
|
12
13
|
builder.enable :bit_field, [:sv_rtl_top]
|
13
14
|
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
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name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.20.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2020-07-06 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: docile
|
@@ -54,7 +54,7 @@ dependencies:
|
|
54
54
|
version: '0'
|
55
55
|
description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
|
56
56
|
|
57
|
-
'
|
57
|
+
'
|
58
58
|
email:
|
59
59
|
- rggen@googlegroups.com
|
60
60
|
executables: []
|
@@ -93,8 +93,12 @@ files:
|
|
93
93
|
- lib/rggen/systemverilog/ral/register/type/external.rb
|
94
94
|
- lib/rggen/systemverilog/ral/register/type/indirect.erb
|
95
95
|
- lib/rggen/systemverilog/ral/register/type/indirect.rb
|
96
|
-
- lib/rggen/systemverilog/ral/register_block/
|
96
|
+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb
|
97
|
+
- lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb
|
97
98
|
- lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb
|
99
|
+
- lib/rggen/systemverilog/ral/register_common.rb
|
100
|
+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
|
101
|
+
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
|
98
102
|
- lib/rggen/systemverilog/ral/setup.rb
|
99
103
|
- lib/rggen/systemverilog/rtl.rb
|
100
104
|
- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
|
@@ -109,8 +113,8 @@ files:
|
|
109
113
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
110
114
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
|
111
115
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
|
112
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
113
|
-
- lib/rggen/systemverilog/rtl/bit_field/type/
|
116
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
|
117
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
|
114
118
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
|
115
119
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb
|
116
120
|
- lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb
|
@@ -128,6 +132,7 @@ files:
|
|
128
132
|
- lib/rggen/systemverilog/rtl/feature.rb
|
129
133
|
- lib/rggen/systemverilog/rtl/global/array_port_format.rb
|
130
134
|
- lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
|
135
|
+
- lib/rggen/systemverilog/rtl/partial_sum.rb
|
131
136
|
- lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
|
132
137
|
- lib/rggen/systemverilog/rtl/register/type.rb
|
133
138
|
- lib/rggen/systemverilog/rtl/register/type/default.erb
|
@@ -142,6 +147,8 @@ files:
|
|
142
147
|
- lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
|
143
148
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
|
144
149
|
- lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb
|
150
|
+
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
151
|
+
- lib/rggen/systemverilog/rtl/register_index.rb
|
145
152
|
- lib/rggen/systemverilog/rtl/setup.rb
|
146
153
|
- lib/rggen/systemverilog/version.rb
|
147
154
|
homepage: https://github.com/rggen/rggen-systemverilog
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@@ -160,15 +167,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
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160
167
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requirements:
|
161
168
|
- - ">="
|
162
169
|
- !ruby/object:Gem::Version
|
163
|
-
version: '2.
|
170
|
+
version: '2.4'
|
164
171
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required_rubygems_version: !ruby/object:Gem::Requirement
|
165
172
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requirements:
|
166
173
|
- - ">="
|
167
174
|
- !ruby/object:Gem::Version
|
168
175
|
version: '0'
|
169
176
|
requirements: []
|
170
|
-
rubygems_version: 3.
|
177
|
+
rubygems_version: 3.1.2
|
171
178
|
signing_key:
|
172
179
|
specification_version: 4
|
173
|
-
summary: rggen-systemverilog-0.
|
180
|
+
summary: rggen-systemverilog-0.20.0
|
174
181
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test_files: []
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@@ -1,11 +0,0 @@
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|
1
|
-
function new(string name);
|
2
|
-
super.new(name);
|
3
|
-
endfunction
|
4
|
-
function void build();
|
5
|
-
<% reg_model_constructors.each do |constructor| %>
|
6
|
-
<%= constructor %>
|
7
|
-
<% end %>
|
8
|
-
endfunction
|
9
|
-
function uvm_reg_map create_default_map();
|
10
|
-
return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
|
11
|
-
endfunction
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@@ -1,14 +0,0 @@
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|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
|
4
|
-
sv_rtl do
|
5
|
-
build do
|
6
|
-
output :register_block, :value_out, {
|
7
|
-
name: "o_#{full_name}", data_type: :logic, width: width,
|
8
|
-
array_size: array_size, array_format: array_port_format
|
9
|
-
}
|
10
|
-
end
|
11
|
-
|
12
|
-
main_code :bit_field, from_template: true
|
13
|
-
end
|
14
|
-
end
|