rggen-systemverilog 0.15.0 → 0.20.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/systemverilog/common.rb +2 -2
- data/lib/rggen/systemverilog/common/component.rb +2 -6
- data/lib/rggen/systemverilog/common/feature.rb +39 -26
- data/lib/rggen/systemverilog/common/utility.rb +9 -4
- data/lib/rggen/systemverilog/common/utility/data_object.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_instance.rb +2 -2
- data/lib/rggen/systemverilog/common/utility/interface_port.rb +9 -5
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +8 -2
- data/lib/rggen/systemverilog/common/utility/structure_definition.rb +3 -5
- data/lib/rggen/systemverilog/ral.rb +4 -1
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +23 -19
- data/lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb +1 -11
- data/lib/rggen/systemverilog/ral/feature.rb +5 -7
- data/lib/rggen/systemverilog/ral/register/type.rb +12 -54
- data/lib/rggen/systemverilog/ral/register/type/default.erb +1 -1
- data/lib/rggen/systemverilog/ral/register/type/external.rb +6 -10
- data/lib/rggen/systemverilog/ral/register/type/indirect.erb +3 -3
- data/lib/rggen/systemverilog/ral/register/type/indirect.rb +5 -2
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb +36 -0
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb +1 -32
- data/lib/rggen/systemverilog/ral/register_common.rb +46 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb +8 -0
- data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb +57 -0
- data/lib/rggen/systemverilog/ral/setup.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +5 -2
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +92 -16
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +5 -8
- data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb} +4 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb +24 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb +3 -3
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb +1 -1
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +13 -16
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +2 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +4 -0
- data/lib/rggen/systemverilog/rtl/partial_sum.rb +29 -0
- data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb +10 -47
- data/lib/rggen/systemverilog/rtl/register/type.rb +30 -5
- data/lib/rggen/systemverilog/rtl/register/type/external.rb +15 -15
- data/lib/rggen/systemverilog/rtl/register/type/indirect.rb +3 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +14 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +5 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb +14 -15
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +6 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb +23 -25
- data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb +11 -13
- data/lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb +30 -0
- data/lib/rggen/systemverilog/rtl/register_index.rb +112 -0
- data/lib/rggen/systemverilog/rtl/setup.rb +1 -0
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +16 -9
- data/lib/rggen/systemverilog/ral/register_block/sv_ral_block_model.erb +0 -11
- data/lib/rggen/systemverilog/rtl/bit_field/type/rw_wo.rb +0 -14
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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-
data.tar.gz:
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+
metadata.gz: 2074da98933b8ffc3d433d76d62acf272535b39d75db5322d4268ff4e80a9aa2
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data.tar.gz: 17b8d6a0250efcf5f1f29f12445b1b08940b6abb2dc9811b77a5ed0865e92693
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: fcb60eb491c928338cc398fab428b80c3b3a132d3f6395b4ac73765d1503c2d403653d4285f8740079cc9f8155ef8d36042bf2c3f1b0d481fef2f3d08ab0a6f2
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7
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data.tar.gz: 97f26f59a360bfcd36fb47e2aa1455396d5b93e978c3de18a0395cb65bbdeab5ac3820f28a57dec8401af836064b3aace1f34241541ef59bb8fbd236cdf0e896
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data/LICENSE
CHANGED
data/README.md
CHANGED
@@ -1,5 +1,5 @@
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[![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
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[![
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[![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
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[![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
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[![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
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[![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen-systemverilog&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
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@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
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Copyright © 2019 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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@@ -28,10 +28,10 @@ module RgGen
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def self.register_component(builder, name, feature_class)
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builder.output_component_registry(name) do
|
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register_component [
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-
:
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+
:root, :register_block, :register_file, :register, :bit_field
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] do |category|
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component Component, ComponentFactory
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-
feature feature_class, FeatureFactory if category != :
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+
feature feature_class, FeatureFactory if category != :root
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end
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end
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end
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@@ -4,12 +4,8 @@ module RgGen
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module SystemVerilog
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module Common
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class Component < Core::OutputBase::Component
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def declarations
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-
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[
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@features.each_value.map(&body),
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@children.map(&body)
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-
].flatten
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+
def declarations
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@declarations ||= Hash.new { |h, k| h[k] = [] }
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9
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end
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def package_imports(domain)
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@@ -8,26 +8,25 @@ module RgGen
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template_engine Core::OutputBase::ERBEngine
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EntityContext =
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Struct.new(:entity_type, :
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+
Struct.new(:entity_type, :method, :declaration_type, :default_layer)
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class << self
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private
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def define_entity(entity_type,
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def define_entity(entity_type, method, declaration_type, default_layer)
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context =
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EntityContext.new(entity_type,
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define_method(entity_type) do |
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-
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-
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-
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EntityContext.new(entity_type, method, declaration_type, default_layer)
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define_method(entity_type) do |name, *args, &block|
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+
if args.size >= 3
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message = 'wrong number of arguments ' \
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"(given #{args.size + 1}, expected 1..3)"
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raise ArgumentError.new(message)
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end
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define_entity(context, name, args, &block)
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end
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end
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end
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def declarations(domain, type)
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@declarations[domain][type]
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-
end
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-
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def package_imports(domain)
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@package_imports[domain]
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end
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@@ -36,30 +35,44 @@ module RgGen
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def post_initialize
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super
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@declarations = Hash.new do |h0, k0|
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h0[k0] = Hash.new { |h1, k1| h1[k1] = [] }
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-
end
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@package_imports = Hash.new { |h, k| h[k] = [] }
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end
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-
def
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-
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-
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-
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def define_entity(context, name, args, &block)
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layer, attributes = parse_entity_arguments(args)
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entity = create_entity(context, name, attributes, &block)
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add_entity(context, entity, name, layer)
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end
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def parse_entity_arguments(args)
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if args.empty?
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[nil, nil]
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elsif args.size == 1 && args.first.is_a?(Hash)
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[nil, args.first]
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elsif args.size == 1
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[args.first, nil]
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else
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args[0..1]
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end
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end
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def create_entity(context, name, attributes, &block)
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merged_attributes = { name: name }.merge(Hash(attributes))
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__send__(context.method, context.entity_type, merged_attributes, &block)
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end
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def add_entity(
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add_declaration(context,
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add_identifier(
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def add_entity(context, entity, name, layer)
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add_declaration(context, entity, layer)
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add_identifier(entity, name)
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end
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def add_declaration(context,
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-
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-
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def add_declaration(context, entity, layer)
|
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(layer || instance_exec(&context.default_layer))
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.declarations[context.declaration_type] << entity.declaration
|
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end
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-
def add_identifier(
|
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instance_variable_set("@#{name}", identifier)
|
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+
def add_identifier(entity, name)
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instance_variable_set("@#{name}", entity.identifier)
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attr_singleton_reader(name)
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export(name)
|
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end
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@@ -24,8 +24,13 @@ module RgGen
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"{#{Array(expressions).join(', ')}}"
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end
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def
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"
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def repeat(count, expression)
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"{#{count}{#{expression}}}"
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end
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def array(expressions = nil, default: nil)
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default_item = default && "default: #{default}"
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"'#{concat([*Array(expressions), default_item].compact)}"
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end
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def function_call(name, expressions = nil)
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@@ -74,7 +79,7 @@ module RgGen
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[width, bit_length].max
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end
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-
def argument(name,
|
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+
def argument(name, attribute = {})
|
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DataObject.new(:argument, attribute.merge(name: name)).declaration
|
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end
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@@ -85,7 +90,7 @@ module RgGen
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module_definition: ModuleDefinition,
|
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package_definition: PackageDefinition
|
87
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}.each do |method_name, definition|
|
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-
define_method(method_name) do |name,
|
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+
define_method(method_name) do |name, attributes = {}, &block|
|
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definition.new(attributes.merge(name: name), &block).to_code
|
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end
|
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end
|
@@ -7,9 +7,9 @@ module RgGen
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class DataObject
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include Core::Utility::AttributeSetter
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9
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-
def initialize(object_type,
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+
def initialize(object_type, default_attributes = {})
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@object_type = object_type
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12
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apply_attributes(default_attributes)
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+
apply_attributes(**default_attributes)
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block_given? && yield(self)
|
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end
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@@ -7,8 +7,8 @@ module RgGen
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class InterfaceInstance
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include Core::Utility::AttributeSetter
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9
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def initialize(
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-
apply_attributes(default_attributes)
|
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+
def initialize(default_attributes = {})
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apply_attributes(**default_attributes)
|
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block_given? && yield(self)
|
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end
|
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@@ -7,8 +7,8 @@ module RgGen
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class InterfacePort
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include Core::Utility::AttributeSetter
|
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9
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10
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-
def initialize(
|
11
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-
apply_attributes(default_attributes)
|
10
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def initialize(default_attributes = {})
|
11
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+
apply_attributes(**default_attributes)
|
12
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block_given? && yield(self)
|
13
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end
|
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@@ -17,9 +17,13 @@ module RgGen
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17
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define_attribute :modport
|
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define_attribute :array_size
|
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|
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-
def modport(
|
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-
@modport_name =
|
22
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-
|
20
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+
def modport(name_and_ports, ports = nil)
|
21
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+
@modport_name, @modport_ports =
|
22
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+
if ports
|
23
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[name_and_ports, ports]
|
24
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+
else
|
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Array(name_and_ports)[0..1]
|
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+
end
|
23
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|
end
|
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def declaration
|
@@ -6,11 +6,12 @@ module RgGen
|
|
6
6
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module Utility
|
7
7
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class LocalScope < StructureDefinition
|
8
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define_attribute :name
|
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+
define_attribute :parameters
|
9
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define_attribute :variables
|
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11
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define_attribute :loop_size
|
11
12
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|
12
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-
def top_scope
|
13
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-
@top_scope =
|
13
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+
def top_scope(value = true)
|
14
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@top_scope = value
|
14
15
|
end
|
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private
|
@@ -28,6 +29,7 @@ module RgGen
|
|
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def pre_body_code(code)
|
29
30
|
genvar_declarations(code)
|
30
31
|
generate_for_header(code)
|
32
|
+
parameter_declarations(code)
|
31
33
|
variable_declarations(code)
|
32
34
|
end
|
33
35
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|
@@ -47,6 +49,10 @@ module RgGen
|
|
47
49
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"for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
|
48
50
|
end
|
49
51
|
|
52
|
+
def parameter_declarations(code)
|
53
|
+
add_declarations_to_body(code, Array(parameters))
|
54
|
+
end
|
55
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+
|
50
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|
def variable_declarations(code)
|
51
57
|
add_declarations_to_body(code, Array(variables))
|
52
58
|
end
|
@@ -4,13 +4,11 @@ module RgGen
|
|
4
4
|
module SystemVerilog
|
5
5
|
module Common
|
6
6
|
module Utility
|
7
|
-
class StructureDefinition <
|
8
|
-
Core::Utility::CodeUtility::StructureDefinition
|
9
|
-
|
7
|
+
class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
|
10
8
|
include Core::Utility::AttributeSetter
|
11
9
|
|
12
|
-
def initialize(
|
13
|
-
apply_attributes(default_attributes)
|
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|
+
def initialize(default_attributes = {}, &block)
|
11
|
+
apply_attributes(**default_attributes)
|
14
12
|
super(&block)
|
15
13
|
end
|
16
14
|
|
@@ -2,6 +2,7 @@
|
|
2
2
|
|
3
3
|
require_relative 'common'
|
4
4
|
require_relative 'ral/feature'
|
5
|
+
require_relative 'ral/register_common'
|
5
6
|
|
6
7
|
module RgGen
|
7
8
|
module SystemVerilog
|
@@ -15,7 +16,9 @@ module RgGen
|
|
15
16
|
'ral/register/type',
|
16
17
|
'ral/register/type/external',
|
17
18
|
'ral/register/type/indirect',
|
18
|
-
'ral/register_block/
|
19
|
+
'ral/register_block/sv_ral_model',
|
20
|
+
'ral/register_block/sv_ral_package',
|
21
|
+
'ral/register_file/sv_ral_model'
|
19
22
|
].freeze
|
20
23
|
|
21
24
|
def self.version
|
@@ -17,11 +17,9 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
17
17
|
export :constructors
|
18
18
|
|
19
19
|
build do
|
20
|
-
variable :
|
21
|
-
name: bit_field.name,
|
22
|
-
|
23
|
-
array_size: array_size,
|
24
|
-
random: true
|
20
|
+
variable :ral_model, {
|
21
|
+
name: bit_field.name, data_type: model_name,
|
22
|
+
array_size: array_size, random: true
|
25
23
|
}
|
26
24
|
end
|
27
25
|
|
@@ -30,18 +28,13 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
30
28
|
end
|
31
29
|
|
32
30
|
def model_name
|
33
|
-
|
34
|
-
|
35
|
-
else
|
36
|
-
helper.model_name || :rggen_ral_field
|
37
|
-
end
|
31
|
+
name = helper.model_name
|
32
|
+
name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
|
38
33
|
end
|
39
34
|
|
40
35
|
def constructors
|
41
36
|
(bit_field.sequence_size&.times || [nil]).map do |index|
|
42
|
-
macro_call(
|
43
|
-
:rggen_ral_create_field_model, arguments(index)
|
44
|
-
)
|
37
|
+
macro_call(:rggen_ral_create_field, arguments(index))
|
45
38
|
end
|
46
39
|
end
|
47
40
|
|
@@ -53,8 +46,8 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
53
46
|
|
54
47
|
def arguments(index)
|
55
48
|
[
|
56
|
-
ral_model[index], bit_field.lsb(index), bit_field.width,
|
57
|
-
|
49
|
+
ral_model[index], bit_field.lsb(index), bit_field.width, string(access),
|
50
|
+
volatile, reset_value(index), valid_reset, index || -1, string(reference)
|
58
51
|
]
|
59
52
|
end
|
60
53
|
|
@@ -62,21 +55,32 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
62
55
|
bit_field.volatile? && 1 || 0
|
63
56
|
end
|
64
57
|
|
65
|
-
def reset_value
|
66
|
-
|
58
|
+
def reset_value(index)
|
59
|
+
value =
|
60
|
+
bit_field.initial_values&.at(index) || bit_field.initial_value || 0
|
61
|
+
hex(value, bit_field.width)
|
67
62
|
end
|
68
63
|
|
69
64
|
def valid_reset
|
70
65
|
bit_field.initial_value? && 1 || 0
|
71
66
|
end
|
67
|
+
|
68
|
+
def reference
|
69
|
+
if bit_field.reference?
|
70
|
+
reference_field = bit_field.reference
|
71
|
+
[reference_field.register.full_name('.'), reference_field.name].join('.')
|
72
|
+
else
|
73
|
+
''
|
74
|
+
end
|
75
|
+
end
|
72
76
|
end
|
73
77
|
|
74
78
|
default_feature do
|
75
79
|
end
|
76
80
|
|
77
81
|
factory do
|
78
|
-
def
|
79
|
-
|
82
|
+
def target_feature_key(_configuration, bit_field)
|
83
|
+
bit_field.type
|
80
84
|
end
|
81
85
|
end
|
82
86
|
end
|
@@ -3,17 +3,7 @@
|
|
3
3
|
RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
|
4
4
|
sv_ral do
|
5
5
|
model_name do
|
6
|
-
"rggen_ral_#{bit_field.type}_field
|
7
|
-
end
|
8
|
-
|
9
|
-
private
|
10
|
-
|
11
|
-
def reference_names
|
12
|
-
reference = bit_field.reference
|
13
|
-
register = reference&.register
|
14
|
-
[register&.name, reference&.name]
|
15
|
-
.map { |name| string(name) }
|
16
|
-
.join(', ')
|
6
|
+
"rggen_ral_#{bit_field.type}_field"
|
17
7
|
end
|
18
8
|
end
|
19
9
|
end
|
@@ -6,20 +6,18 @@ module RgGen
|
|
6
6
|
class Feature < Common::Feature
|
7
7
|
private
|
8
8
|
|
9
|
-
def create_variable(_, attributes, block)
|
9
|
+
def create_variable(_, attributes, &block)
|
10
10
|
DataObject.new(
|
11
11
|
:variable, attributes.merge(array_format: :unpacked), &block
|
12
12
|
)
|
13
13
|
end
|
14
14
|
|
15
|
-
def create_parameter(_, attributes, block)
|
16
|
-
DataObject.new(
|
17
|
-
:parameter, attributes, &block
|
18
|
-
)
|
15
|
+
def create_parameter(_, attributes, &block)
|
16
|
+
DataObject.new(:parameter, attributes, &block)
|
19
17
|
end
|
20
18
|
|
21
|
-
define_entity :variable, :create_variable, :variable
|
22
|
-
define_entity :parameter, :create_parameter, :parameter
|
19
|
+
define_entity :variable, :create_variable, :variable, -> { component.parent }
|
20
|
+
define_entity :parameter, :create_parameter, :parameter, -> { component.parent }
|
23
21
|
end
|
24
22
|
end
|
25
23
|
end
|