rggen-systemverilog 0.15.0 → 0.20.0

data/lib/rggen/systemverilog/ral/register/type.rb

@@ -3,6 +3,8 @@
 RgGen.define_list_feature(:register, :type) do
   sv_ral do
     base_feature do
+      include RgGen::SystemVerilog::RAL::RegisterCommon
+
       define_helpers do
         def model_name(&body)
           @model_name = body if block_given?
@@ -14,14 +16,6 @@ RgGen.define_list_feature(:register, :type) do
           @offset_address
         end
 
-        def unmapped
-          @unmapped = true
-        end
-
-        def unmapped?
-          !@unmapped.nil?
-        end
-
         def constructor(&body)
           @constructor = body if block_given?
           @constructor
@@ -31,18 +25,14 @@ RgGen.define_list_feature(:register, :type) do
       export :constructors
 
       build do
-        variable :register_block, :ral_model, {
-          name: register.name,
-          data_type: model_name,
-          array_size: register.array_size,
-          random: true
+        variable :ral_model, {
+          name: register.name, data_type: model_name,
+          array_size: register.array_size, random: true
         }
       end
 
       def constructors
-        (array_index_list || [nil]).map.with_index do |array_index, i|
-          constructor_code(array_index, i)
-        end
+        array_indices.map.with_index(&method(:constructor_code))
       end
 
       private
@@ -51,45 +41,25 @@ RgGen.define_list_feature(:register, :type) do
         if helper.model_name
           instance_eval(&helper.model_name)
         else
-          "#{register.name}_reg_model"
+          "#{register.full_name('_')}_reg_model"
         end
       end
 
-      def array_index_list
-        (register.array? || nil) &&
-          begin
-            index_table = register.array_size.map { |size| (0...size).to_a }
-            index_table[0].product(*index_table[1..-1])
-          end
-      end
-
       def constructor_code(array_index, index)
         if helper.constructor
           instance_exec(array_index, index, &helper.constructor)
         else
-          macro_call(
-            :rggen_ral_create_reg_model, arguments(array_index, index)
-          )
+          macro_call(:rggen_ral_create_reg, arguments(array_index, index))
         end
       end
 
       def arguments(array_index, index)
         [
           ral_model[array_index], array(array_index), offset_address(index),
-          access_rights, unmapped, hdl_path(array_index)
+          string(access_rights), string(hdl_path(array_index))
         ]
       end
 
-      def offset_address(index = 0)
-        address =
-          if helper.offset_address
-            instance_exec(index, &helper.offset_address)
-          else
-            register.offset_address + register.byte_width * index
-          end
-        hex(address, register_block.local_address_width)
-      end
-
       def access_rights
         if read_only?
           'RO'
@@ -108,20 +78,8 @@ RgGen.define_list_feature(:register, :type) do
         register.writable? && !register.readable?
       end
 
-      def unmapped
-        helper.unmapped? && 1 || 0
-      end
-
-      def hdl_path(array_index)
-        [
-          "g_#{register.name}",
-          *Array(array_index).map { |i| "g[#{i}]" },
-          'u_register'
-        ].join('.')
-      end
-
       def variables
-        register.declarations(:register, :variable)
+        register.declarations[:variable]
       end
 
       def field_model_constructors
@@ -146,8 +104,8 @@ RgGen.define_list_feature(:register, :type) do
     end
 
     factory do
-      def select_feature(_configuration, register)
-        target_features[register.type]
+      def target_feature_key(_configuration, register)
+        register.type
       end
     end
   end

data/lib/rggen/systemverilog/ral/register/type/default.erb

@@ -4,5 +4,5 @@ endfunction
 function void build();
 <% field_model_constructors.each do |constructor| %>
   <%= constructor %>
-<% end%>
+<% end %>
 endfunction

data/lib/rggen/systemverilog/ral/register/type/external.rb

@@ -3,15 +3,11 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   sv_ral do
     build do
-      parameter :register_block, :model_type, {
-        name: model_name,
-        data_type: 'type',
-        default: 'rggen_ral_block'
+      parameter :model_type, {
+        name: model_name, data_type: 'type', default: 'rggen_ral_block'
       }
-      parameter :register_block, :integrate_model, {
-        name: "INTEGRATE_#{model_name}",
-        data_type: 'bit',
-        default: 1
+      parameter :integrate_model, {
+        name: "INTEGRATE_#{model_name}", data_type: 'bit', default: 1
       }
     end
 
@@ -19,8 +15,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     constructor do
       macro_call(
-        'rggen_ral_create_block_model',
-        [ral_model, offset_address, 'this', integrate_model]
+        'rggen_ral_create_block',
+        [ral_model, offset_address(0), 'this', integrate_model]
       )
     end
   end

data/lib/rggen/systemverilog/ral/register/type/indirect.erb

@@ -4,10 +4,10 @@ endfunction
 function void build();
 <% field_model_constructors.each do |constructor| %>
   <%= constructor %>
-<% end%>
+<% end %>
 endfunction
 function void setup_index_fields();
-<% index_properties.each do |reg_name, field_name, value| %>
-  setup_index_field("<%= reg_name %>", "<%= field_name%>", <%= value %>);
+<% index_properties.each do |field_name, value| %>
+  setup_index_field("<%= field_name %>", <%= value %>);
 <% end %>
 endfunction

data/lib/rggen/systemverilog/ral/register/type/indirect.rb

@@ -2,7 +2,6 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_ral do
-    unmapped
     offset_address { register.offset_address }
 
     main_code :ral_package do
@@ -24,12 +23,16 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
           else
             "array_index[#{array_position += 1}]"
           end
-        [field.register.name, field.name, value]
+        [field_full_name(field), value]
       end
     end
 
     def index_fields
       register.collect_index_fields(register_block.bit_fields)
     end
+
+    def field_full_name(field)
+      [field.register.full_name('.'), field.name].join('.')
+    end
   end
 end

data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.erb

@@ -0,0 +1,8 @@
+function new(string name);
+  super.new(name, <%= byte_width %>, 0);
+endfunction
+function void build();
+<% child_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end %>
+endfunction

data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_ral_model) do
+  sv_ral do
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_block'
+        sv_class.parameters parameters
+        sv_class.variables variables
+        sv_class.body { process_template }
+      end
+    end
+
+    private
+
+    def model_name
+      "#{register_block.name}_block_model"
+    end
+
+    def parameters
+      register_block.declarations[:parameter]
+    end
+
+    def variables
+      register_block.declarations[:variable]
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def child_model_constructors
+      register_block.children.flat_map(&:constructors)
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb

@@ -8,23 +8,12 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
           package.package_imports packages
           package.include_files include_files
           package.body do |code|
-            register_block.generate_code(:ral_package, :bottom_up, code)
+            register_block.generate_code(code, :ral_package, :bottom_up)
           end
         end
       end
     end
 
-    main_code :ral_package do
-      class_definition(model_name) do |sv_class|
-        sv_class.base 'rggen_ral_block'
-        sv_class.parameters parameters
-        sv_class.variables variables
-        sv_class.body do
-          process_template(File.join(__dir__, 'sv_ral_block_model.erb'))
-        end
-      end
-    end
-
     private
 
     def package_name
@@ -41,25 +30,5 @@ RgGen.define_simple_feature(:register_block, :sv_ral_package) do
     def include_files
       ['uvm_macros.svh', 'rggen_ral_macros.svh']
     end
-
-    def model_name
-      "#{register_block.name}_block_model"
-    end
-
-    def parameters
-      register_block.declarations(:register_block, :parameter)
-    end
-
-    def variables
-      register_block.declarations(:register_block, :variable)
-    end
-
-    def reg_model_constructors
-      register_block.registers.flat_map(&:constructors)
-    end
-
-    def byte_width
-      configuration.byte_width
-    end
   end
 end

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -0,0 +1,46 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RAL
+      module RegisterCommon
+        private
+
+        def array_indices
+          if component.array?
+            index_table = component.array_size.map { |size| (0...size).to_a }
+            index_table[0].product(*index_table[1..-1])
+          else
+            [nil]
+          end
+        end
+
+        def offset_address(index)
+          address =
+            if register? && helper.offset_address
+              instance_exec(index, &helper.offset_address)
+            else
+              default_offset_address(index)
+            end
+          hex(address, register_block.local_address_width)
+        end
+
+        def default_offset_address(index)
+          component.offset_address + component.byte_size(false) * index
+        end
+
+        def hdl_path(array_index)
+          [
+            "g_#{component.name}",
+            *Array(array_index).map { |i| "g[#{i}]" },
+            *unit_instance_name
+          ].join('.')
+        end
+
+        def unit_instance_name
+          register? && 'u_register' || nil
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb

@@ -0,0 +1,8 @@
+function new(string name);
+  super.new(name, <%= byte_width %>, 0);
+endfunction
+function void build();
+<% child_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end %>
+endfunction

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :sv_ral_model) do
+  sv_ral do
+    include RgGen::SystemVerilog::RAL::RegisterCommon
+
+    export :constructors
+
+    build do
+      variable :ral_model, {
+        name: register_file.name, data_type: model_name,
+        array_size: register_file.array_size, random: true
+      }
+    end
+
+    def constructors
+      array_indices.map.with_index(&method(:constructor_code))
+    end
+
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_reg_file'
+        sv_class.variables variables
+        sv_class.body { process_template }
+      end
+    end
+
+    private
+
+    def model_name
+      "#{register_file.full_name('_')}_reg_file_model"
+    end
+
+    def constructor_code(array_index, index)
+      macro_call(:rggen_ral_create_reg_file, arguments(array_index, index))
+    end
+
+    def arguments(array_index, index)
+      [
+        ral_model[array_index], array(array_index), offset_address(index),
+        string(hdl_path(array_index))
+      ]
+    end
+
+    def variables
+      register_file.declarations[:variable]
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def child_model_constructors
+      register_file.children.flat_map(&:constructors)
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/setup.rb

@@ -3,5 +3,6 @@
 require 'rggen/systemverilog/ral'
 
 RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
-  builder.enable :register_block, [:sv_ral_package]
+  builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
+  builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -2,6 +2,8 @@
 
 require_relative 'common'
 require_relative 'rtl/feature'
+require_relative 'rtl/partial_sum'
+require_relative 'rtl/register_index'
 
 module RgGen
   module SystemVerilog
@@ -14,7 +16,7 @@ module RgGen
         'rtl/bit_field/type/ro',
         'rtl/bit_field/type/rof',
         'rtl/bit_field/type/rs_w0s_w1s',
-        'rtl/bit_field/type/rw_wo',
+        'rtl/bit_field/type/rw_w1_wo_wo1',
         'rtl/bit_field/type/rwc',
         'rtl/bit_field/type/rwe',
         'rtl/bit_field/type/rwl',
@@ -31,7 +33,8 @@ module RgGen
         'rtl/register_block/protocol',
         'rtl/register_block/protocol/apb',
         'rtl/register_block/protocol/axi4lite',
-        'rtl/register_block/sv_rtl_top'
+        'rtl/register_block/sv_rtl_top',
+        'rtl/register_file/sv_rtl_top'
       ].freeze
 
       def self.version