rggen-systemverilog 0.15.0 → 0.20.0

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -3,12 +3,26 @@
 RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
   sv_rtl do
     export :local_index
+    export :local_indices
     export :loop_variables
     export :array_size
     export :value
 
     build do
-      interface :bit_field, :bit_field_sub_if, {
+      if fixed_initial_value?
+        localparam :initial_value, {
+          name: initial_value_name, data_type: :bit, width: bit_field.width,
+          array_size: initial_value_size, array_format: initial_value_format,
+          default: initial_value_lhs
+        }
+      elsif initial_value?
+        parameter :initial_value, {
+          name: initial_value_name, data_type: :bit, width: bit_field.width,
+          array_size: initial_value_size, array_format: initial_value_format,
+          default: initial_value_lhs
+        }
+      end
+      interface :bit_field_sub_if, {
         name: 'bit_field_sub_if',
         interface_type: 'rggen_bit_field_if',
         parameter_values: [bit_field.width]
@@ -18,6 +32,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     main_code :register do
       local_scope("g_#{bit_field.name}") do |scope|
         scope.loop_size loop_size
+        scope.parameters parameters
         scope.variables variables
         scope.body(&method(:body_code))
       end
@@ -28,13 +43,12 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def local_index
-      (bit_field.sequential? || nil) &&
+      (index_name = local_index_name) &&
         create_identifier(index_name)
     end
 
-    def index_name
-      depth = (register.loop_variables&.size || 0) + 1
-      loop_index(depth)
+    def local_indices
+      [*register.local_indices, local_index_name]
     end
 
     def loop_variables
@@ -44,34 +58,96 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     def array_size
       (inside_loop? || nil) &&
-        [*register.array_size, bit_field.sequence_size].compact
+        [
+          *register_files.flat_map(&:array_size),
+          *register.array_size,
+          *bit_field.sequence_size
+        ].compact
     end
 
-    def value(register_offset = nil, bit_field_offset = nil, width = nil)
-      bit_field_offset ||= local_index
-      width ||= bit_field.width
-      register_block
-        .register_if[register.index(register_offset)]
-        .value[bit_field.lsb(bit_field_offset), width]
+    def value(offsets = nil, width = nil)
+      value_lsb = bit_field.lsb(offsets&.last || local_index_name)
+      value_width = width || bit_field.width
+      register_if(offsets&.slice(0..-2)).value[value_lsb, value_width]
     end
 
     private
 
+    [:fixed_initial_value?, :initial_value_array?, :initial_value?].each do |m|
+      define_method(m) { bit_field.__send__(__method__) }
+    end
+
+    def local_index_name
+      (bit_field.sequential? || nil) &&
+        begin
+          depth = (register.loop_variables&.size || 0) + 1
+          loop_index(depth)
+        end
+    end
+
+    def register_if(offsets)
+      index = register.index(offsets || register.local_indices)
+      register_block.register_if[index]
+    end
+
+    def initial_value_name
+      identifiers = []
+      identifiers << bit_field.full_name('_') unless fixed_initial_value?
+      identifiers << 'initial_value'
+      identifiers.join('_').upcase
+    end
+
+    def initial_value_size
+      initial_value_array? && [bit_field.sequence_size] || nil
+    end
+
+    def initial_value_format
+      fixed_initial_value? && :unpacked ||
+        configuration.array_port_format
+    end
+
+    def initial_value_lhs
+      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    end
+
+    def initial_value_array_lhs
+      if fixed_initial_value?
+        array(sized_initial_values)
+      elsif initial_value_format == :unpacked
+        array(default: sized_initial_value)
+      else
+        repeat(bit_field.sequence_size, sized_initial_value)
+      end
+    end
+
+    def sized_initial_value
+      bit_field.initial_value &&
+        hex(bit_field.initial_value, bit_field.width)
+    end
+
+    def sized_initial_values
+      bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
+    end
+
     def inside_loop?
       register.array? || bit_field.sequential?
     end
 
     def loop_size
-      (bit_field.sequential? || nil) &&
-        { index_name => bit_field.sequence_size }
+      (loop_variable = local_index_name) &&
+        { loop_variable => bit_field.sequence_size }
+    end
+
+    def parameters
+      bit_field.declarations[:parameter]
     end
 
     def variables
-      bit_field.declarations(:bit_field, :variable)
+      bit_field.declarations[:variable]
     end
 
     def body_code(code)
-      bit_field.generate_code(:bit_field, :top_down, code)
+      bit_field.generate_code(code, :bit_field, :top_down)
     end
 
     def bit_field_if_connection

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -30,7 +30,8 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        hex(bit_field.initial_value, bit_field.width)
+        index = bit_field.initial_value_array? && bit_field.local_index || nil
+        bit_field.initial_value[index]
       end
 
       def mask
@@ -42,11 +43,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(
-              register.local_index,
-              bit_field.local_index,
-              bit_field.reference_width
-            )
+            .value(bit_field.local_indices, bit_field.reference_width)
       end
 
       def bit_field_if
@@ -59,8 +56,8 @@ RgGen.define_list_feature(:bit_field, :type) do
     end
 
     factory do
-      def select_feature(_configuration, bit_field)
-        target_features[bit_field.type] || (
+      def target_feature_key(_configuration, bit_field)
+        target_features.key?(bit_field.type) && bit_field.type || (
           error "code generator for #{bit_field.type} " \
                 'bit field type is not implemented'
         )

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb

@@ -3,16 +3,16 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
   sv_rtl do
     build do
-      input :register_block, :set, {
+      input :set, {
         name: "i_#{full_name}_set", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
       if bit_field.reference?
-        output :register_block, :value_unmasked, {
+        output :value_unmasked, {
           name: "o_#{full_name}_unmasked", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :value_in, {
+        input :value_in, {
           name: "i_#{full_name}", data_type: :logic, width: width,
           array_size: array_size, array_format: array_port_format
         }

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb

@@ -3,11 +3,11 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
   sv_rtl do
     build do
-      input :register_block, :clear, {
+      input :clear, {
         name: "i_#{full_name}_clear", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/{rw_wo.erb → rw_w1_wo_wo1.erb}

@@ -1,6 +1,8 @@
-rggen_bit_field_<%= bit_field.type %> #(
+rggen_bit_field_rw_wo #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
+  .WRITE_ONCE     (<%= write_once %>)
 ) u_bit_field (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def write_only
+      bit_field.write_only? && 1 || 0
+    end
+
+    def write_once
+      [:w1, :wo1].include?(bit_field.type) && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :clear, {
+        input :clear, {
           name: "i_#{full_name}_clear", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :enable, {
+        input :enable, {
           name: "i_#{full_name}_enable", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :lock, {
+        input :lock, {
           name: "i_#{full_name}_lock", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -4,16 +4,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :register_block, :set, {
+        input :set, {
           name: "i_#{full_name}_set", data_type: :logic, width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :register_block, :value_in, {
+      input :value_in, {
         name: "i_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
   sv_rtl do
     build do
-      output :register_block, :value_out, {
+      output :value_out, {
         name: "o_#{full_name}", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
-      output :register_block, :trigger, {
+      output :trigger, {
         name: "o_#{full_name}_trigger", data_type: :logic, width: width,
         array_size: array_size, array_format: array_port_format
       }

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,42 +6,39 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes, block)
+        def create_variable(data_type, attributes, &block)
           DataObject.new(
             :variable, attributes.merge(data_type: data_type), &block
           )
         end
 
-        def create_interface(_, attributes, block)
+        def create_if_instance(_, attributes, &block)
           InterfaceInstance.new(attributes, &block)
         end
 
-        def create_argument(direction, attributes, block)
+        def create_argument(direction, attributes, &block)
           DataObject.new(
             :argument, attributes.merge(direction: direction), &block
           )
         end
 
-        def create_interface_port(_, attributes, block)
+        def create_if_port(_, attributes, &block)
           InterfacePort.new(attributes, &block)
         end
 
-        def create_parameter(_, attributes, block)
+        def create_parameter(parameter_type, attributes, &block)
           DataObject.new(
-            :parameter, attributes.merge(parameter_type: :parameter), &block
+            :parameter, attributes.merge(parameter_type: parameter_type), &block
           )
         end
 
-        [
-          [:logic, :create_variable, :variable],
-          [:interface, :create_interface, :variable],
-          [:input, :create_argument, :port],
-          [:output, :create_argument, :port],
-          [:interface_port, :create_interface_port, :port],
-          [:parameter, :create_parameter, :parameter]
-        ].each do |entity, creation_method, declaration_type|
-          define_entity(entity, creation_method, declaration_type)
-        end
+        define_entity :logic, :create_variable, :variable, -> { component }
+        define_entity :interface, :create_if_instance, :variable, -> { component }
+        define_entity :input, :create_argument, :port, -> { register_block }
+        define_entity :output, :create_argument, :port, -> { register_block }
+        define_entity :interface_port, :create_if_port, :port, -> { register_block }
+        define_entity :parameter, :create_parameter, :parameter, -> { register_block }
+        define_entity :localparam, :create_parameter, :parameter, -> { component }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/global/array_port_format.rb

@@ -15,5 +15,7 @@ RgGen.define_simple_feature(:global, :array_port_format) do
           error "illegal input value for array port format: #{value.inspect}"
         end
     end
+
+    printable :array_port_format
   end
 end

data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb

@@ -20,5 +20,9 @@ RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
           error "cannot convert #{value.inspect} into boolean"
         end
     end
+
+    printable :fold_sv_interface_port do
+      fold_sv_interface_port?
+    end
   end
 end