rggen-systemverilog 0.15.0 → 0.20.0

data/lib/rggen/systemverilog/rtl/partial_sum.rb

@@ -0,0 +1,29 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RTL
+      module PartialSum
+        private
+
+        def partial_sums(operands)
+          sums =
+            operands
+              .chunk(&method(:integer?))
+              .flat_map(&method(:calc_partial_sum))
+              .reject { |value| integer?(value) && value.zero? }
+          sums.empty? && [0] || sums
+        end
+
+        def calc_partial_sum(kind_ans_values)
+          kind, values = kind_ans_values
+          kind && values.sum || values
+        end
+
+        def integer?(value)
+          value.is_a?(Integer)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb

@@ -2,18 +2,11 @@
 
 RgGen.define_simple_feature(:register, :sv_rtl_top) do
   sv_rtl do
-    export :index
-    export :local_index
-    export :loop_variables
-
-    pre_build do
-      @base_index =
-        register_block.registers.map(&:count).inject(0, :+)
-    end
+    include RgGen::SystemVerilog::RTL::RegisterIndex
 
     build do
-      if register.bit_fields?
-        interface :register, :bit_field_if, {
+      unless register.bit_fields.empty?
+        interface :bit_field_if, {
           name: 'bit_field_if',
           interface_type: 'rggen_bit_field_if',
           parameter_values: [register.width]
@@ -21,62 +14,32 @@ RgGen.define_simple_feature(:register, :sv_rtl_top) do
       end
     end
 
-    main_code :register_block do
+    main_code :register_file do
       local_scope("g_#{register.name}") do |scope|
-        scope.top_scope
+        scope.top_scope top_scope?
         scope.loop_size loop_size
         scope.variables variables
         scope.body(&method(:body_code))
       end
     end
 
-    def index(offset = nil)
-      operands =
-        register.array? ? [@base_index, offset || local_index] : [@base_index]
-      if operands.all? { |operand| operand.is_a?(Integer) }
-        operands.inject(:+)
-      else
-        operands.join('+')
-      end
-    end
-
-    def local_index
-      (register.array? || nil) &&
-        loop_variables
-          .zip(local_index_coefficients)
-          .map { |v, c| [c, v].compact.join('*') }
-          .join('+')
-    end
-
-    def loop_variables
-      (register.array? || nil) &&
-        register.array_size.map.with_index(1) do |_size, i|
-          create_identifier(loop_index(i))
-        end
-    end
-
     private
 
-    def local_index_coefficients
-      coefficients = []
-      register.array_size.reverse.inject(1) do |total, size|
-        coefficients.unshift(coefficients.size.zero? ? nil : total)
-        total * size
-      end
-      coefficients
+    def top_scope?
+      register_file.nil?
     end
 
     def loop_size
       (register.array? || nil) &&
-        loop_variables.zip(register.array_size).to_h
+        local_loop_variables.zip(register.array_size).to_h
     end
 
     def variables
-      register.declarations(:register, :variable)
+      register.declarations[:variable]
     end
 
     def body_code(code)
-      register.generate_code(:register, :top_down, code)
+      register.generate_code(code, :register, :top_down)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -3,6 +3,8 @@
 RgGen.define_list_feature(:register, :type) do
   sv_rtl do
     base_feature do
+      include RgGen::SystemVerilog::RTL::PartialSum
+
       private
 
       def readable
@@ -22,7 +24,29 @@ RgGen.define_list_feature(:register, :type) do
       end
 
       def offset_address
-        hex(register.offset_address, address_width)
+        offsets = [*register_files, register].flat_map(&method(:collect_offsets))
+        offsets = partial_sums(offsets)
+        format_offsets(offsets)
+      end
+
+      def collect_offsets(component)
+        if component.register_file? && component.array?
+          [component.offset_address, byte_offset(component)]
+        else
+          component.offset_address
+        end
+      end
+
+      def byte_offset(component)
+        "#{component.byte_size(false)}*(#{component.local_index})"
+      end
+
+      def format_offsets(offsets)
+        offsets.map(&method(:format_offset)).join('+')
+      end
+
+      def format_offset(offset)
+        offset.is_a?(Integer) ? hex(offset, address_width) : offset
       end
 
       def width
@@ -53,10 +77,11 @@ RgGen.define_list_feature(:register, :type) do
     end
 
     factory do
-      def select_feature(_configuration, register)
-        target_features[register.type] ||
-          unless register.type == :default
-            error "code generator for #{register.type} register type " \
+      def target_feature_key(_configuration, register)
+        type = register.type
+        (target_features.key?(type) || type == :default) && type ||
+          begin
+            error "code generator for #{type} register type " \
                   'is not implemented'
           end
       end

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -4,49 +4,49 @@ RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :bus_if, {
+        interface_port :bus_if, {
           name: "#{register.name}_bus_if",
           interface_type: 'rggen_bus_if',
           modport: 'master'
         }
       else
-        output :register_block, :valid, {
+        output :valid, {
           name: "o_#{register.name}_valid",
           data_type: :logic, width: 1
         }
-        output :register_block, :address, {
+        output :access, {
+          name: "o_#{register.name}_access",
+          data_type: :logic, width: '$bits(rggen_access)'
+        }
+        output :address, {
           name: "o_#{register.name}_address",
           data_type: :logic, width: address_width
         }
-        output :register_block, :write, {
-          name: "o_#{register.name}_write",
-          data_type: :logic, width: 1
-        }
-        output :register_block, :write_data, {
+        output :write_data, {
           name: "o_#{register.name}_data",
           data_type: :logic, width: bus_width
         }
-        output :register_block, :strobe, {
+        output :strobe, {
           name: "o_#{register.name}_strobe",
           data_type: :logic, width: byte_width
         }
-        input :register_block, :ready, {
+        input :ready, {
           name: "i_#{register.name}_ready",
           data_type: :logic, width: 1
         }
-        input :register_block, :status, {
+        input :status, {
           name: "i_#{register.name}_status",
           data_type: :logic, width: 2
         }
-        input :register_block, :read_data, {
+        input :read_data, {
           name: "i_#{register.name}_data",
           data_type: :logic, width: bus_width
         }
-        interface :register, :bus_if, {
+        interface :bus_if, {
           name: 'bus_if', interface_type: 'rggen_bus_if',
           parameter_values: [address_width, bus_width],
           variables: [
-            'valid', 'address', 'write', 'write_data', 'strobe',
+            'valid', 'access', 'address', 'write_data', 'strobe',
             'ready', 'status', 'read_data'
           ]
         }
@@ -58,8 +58,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       unless configuration.fold_sv_interface_port?
         [
           [valid, bus_if.valid],
+          [access, bus_if.access],
           [address, bus_if.address],
-          [write, bus_if.write],
           [write_data, bus_if.write_data],
           [strobe, bus_if.strobe],
           [bus_if.ready, ready],

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   sv_rtl do
     build do
-      logic :register, :indirect_index, { width: index_width }
+      logic :indirect_index, { width: index_width }
     end
 
     main_code :register do |code|
@@ -19,11 +19,11 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def index_width
-      @index_width ||= index_fields.map(&:width).inject(:+)
+      @index_width ||= index_fields.map(&:width).sum
     end
 
     def index_values
-      loop_variables = register.loop_variables
+      loop_variables = register.local_loop_variables
       register.index_entries.zip(index_fields).map do |entry, field|
         if entry.array_index?
           loop_variables.shift[0, field.width]

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -40,8 +40,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
           (error 'no protocols are available', position)
       end
 
-      def select_feature(data)
-        target_features[data.value]
+      def target_feature_key(data)
+        data.value
       end
 
       private
@@ -64,6 +64,16 @@ RgGen.define_list_feature(:register_block, :protocol) do
     shared_context.feature_registry(registry)
 
     base_feature do
+      build do
+        parameter :error_status, {
+          name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
+        }
+        parameter :default_read_data, {
+          name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
+          default: hex(0, bus_width)
+        }
+      end
+
       private
 
       def address_width
@@ -100,8 +110,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def select_feature(configuration, _register_block)
-        target_features[configuration.protocol]
+      def target_feature_key(configuration, _register_block)
+        configuration.protocol
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -1,7 +1,9 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH  (<%= local_address_width %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .REGISTERS      (<%= total_registers %>)
+  .ADDRESS_WIDTH      (<%= local_address_width %>),
+  .BUS_WIDTH          (<%= bus_width %>),
+  .REGISTERS          (<%= total_registers %>),
+  .ERROR_STATUS       (<%= error_status %>),
+  .DEFAULT_READ_DATA  (<%= default_read_data %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -22,42 +22,41 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
   sv_rtl do
     build do
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :apb_if, {
+        interface_port :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if', modport: 'slave'
         }
       else
-        input :register_block, :psel, {
+        input :psel, {
           name: 'i_psel', data_type: :logic, width: 1
         }
-        input :register_block, :penable, {
+        input :penable, {
           name: 'i_penable', data_type: :logic, width: 1
         }
-        input :register_block, :paddr, {
+        input :paddr, {
           name: 'i_paddr', data_type: :logic, width: address_width
         }
-        input :register_block, :pprot, {
+        input :pprot, {
           name: 'i_pprot', data_type: :logic, width: 3
         }
-        input :register_block, :pwrite, {
+        input :pwrite, {
           name: 'i_pwrite', data_type: :logic, width: 1
         }
-        input :register_block, :pstrb, {
-          name: 'i_pstrb', data_type: :logic,
-          width: byte_width
+        input :pstrb, {
+          name: 'i_pstrb', data_type: :logic, width: byte_width
         }
-        input :register_block, :pwdata, {
+        input :pwdata, {
           name: 'i_pwdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pready, {
+        output :pready, {
           name: 'o_pready', data_type: :logic, width: 1
         }
-        output :register_block, :prdata, {
+        output :prdata, {
           name: 'o_prdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :pslverr, {
+        output :pslverr, {
           name: 'o_pslverr', data_type: :logic, width: 1
         }
-        interface :register_block, :apb_if, {
+        interface :apb_if, {
           name: 'apb_if', interface_type: 'rggen_apb_if',
           parameter_values: [address_width, bus_width],
           variables: [
@@ -82,7 +81,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
           [pready, apb_if.pready],
           [prdata, apb_if.prdata],
           [pslverr, apb_if.pslverr]
-        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
+        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,8 +1,10 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH  (<%= local_address_width %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .REGISTERS      (<%= total_registers %>),
-  .WRITE_FIRST    (<%= write_first %>)
+  .ADDRESS_WIDTH      (<%= local_address_width %>),
+  .BUS_WIDTH          (<%= bus_width %>),
+  .REGISTERS          (<%= total_registers %>),
+  .ERROR_STATUS       (<%= error_status %>),
+  .DEFAULT_READ_DATA  (<%= default_read_data %>),
+  .WRITE_FIRST        (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,75 +13,73 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
-      parameter :register_block, :write_first, {
-        name: 'WRITE_FIRST',
-        data_type: :bit,
-        default: 1
+      parameter :write_first, {
+        name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
       if configuration.fold_sv_interface_port?
-        interface_port :register_block, :axi4lite_if, {
+        interface_port :axi4lite_if, {
           name: 'axi4lite_if',
           interface_type: 'rggen_axi4lite_if', modport: 'slave'
         }
       else
-        input :register_block, :awvalid, {
+        input :awvalid, {
           name: 'i_awvalid', data_type: :logic, width: 1
         }
-        output :register_block, :awready, {
+        output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
-        input :register_block, :awaddr, {
+        input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
-        input :register_block, :awprot, {
+        input :awprot, {
           name: 'i_awprot', data_type: :logic, width: 3
         }
-        input :register_block, :wvalid, {
+        input :wvalid, {
           name: 'i_wvalid', data_type: :logic, width: 1
         }
-        output :register_block, :wready, {
+        output :wready, {
           name: 'o_wready', data_type: :logic, width: 1
         }
-        input :register_block, :wdata, {
+        input :wdata, {
           name: 'i_wdata', data_type: :logic, width: bus_width
         }
-        input :register_block, :wstrb, {
+        input :wstrb, {
           name: 'i_wstrb', data_type: :logic, width: byte_width
         }
-        output :register_block, :bvalid, {
+        output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
-        input :register_block, :bready, {
+        input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
-        output :register_block, :bresp, {
+        output :bresp, {
           name: 'o_bresp', data_type: :logic, width: 2
         }
-        input :register_block, :arvalid, {
+        input :arvalid, {
           name: 'i_arvalid', data_type: :logic, width: 1
         }
-        output :register_block, :arready, {
+        output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
-        input :register_block, :araddr, {
+        input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
-        input :register_block, :arprot, {
+        input :arprot, {
           name: 'i_arprot', data_type: :logic, width: 3
         }
-        output :register_block, :rvalid, {
+        output :rvalid, {
           name: 'o_rvalid', data_type: :logic, width: 1
         }
-        input :register_block, :rready, {
+        input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
-        output :register_block, :rdata, {
+        output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
-        output :register_block, :rresp, {
+        output :rresp, {
           name: 'o_rresp', data_type: :logic, width: 2
         }
-        interface :register_block, :axi4lite_if, {
+        interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
           parameter_values: [address_width, bus_width],
           variables: [