RubyGems - passenger - Versions diffs - 6.1.0 → 6.1.1 - Mend

passenger 6.1.0 → 6.1.1

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Files changed (440) hide show

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/core_arch_ops_gcc_aarch64.hpp CHANGED Viewed

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/core_arch_ops_gcc_aarch64.hpp
@@ -15,7 +15,7 @@
 #define BOOST_ATOMIC_DETAIL_CORE_ARCH_OPS_GCC_AARCH64_HPP_INCLUDED_
 #include <cstddef>
-#include <boost/cstdint.hpp>
+#include <cstdint>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_traits.hpp>
@@ -34,8 +34,8 @@ namespace detail {
 struct core_arch_operations_gcc_aarch64_base
 {
-    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+    static constexpr bool full_cas_based = false;
+    static constexpr bool is_always_lock_free = true;
 };
 // Due to bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 we have to explicitly specify size of the registers
@@ -49,15 +49,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 1u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch64_base
 {
-    typedef typename storage_traits< 1u >::type storage_type;
+    using storage_type = typename storage_traits< 1u >::type;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 1u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 1u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 1u;
+    static constexpr std::size_t storage_alignment = 1u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -74,7 +75,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         }
     }
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -106,12 +107,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -123,7 +126,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
             : "memory"\
         );
 #else
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -140,13 +143,15 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -186,12 +191,15 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -232,11 +240,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -249,7 +260,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -267,12 +278,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = -v;
@@ -288,7 +301,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -306,12 +319,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = ~v;
@@ -326,7 +341,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -344,12 +359,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -362,7 +379,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -380,12 +397,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -398,7 +417,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -416,16 +435,17 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -435,15 +455,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 2u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch64_base
 {
-    typedef typename storage_traits< 2u >::type storage_type;
+    using storage_type = typename storage_traits< 2u >::type;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 2u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 2u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 2u;
+    static constexpr std::size_t storage_alignment = 2u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -460,7 +481,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         }
     }
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -492,12 +513,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -509,7 +532,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
             : "memory"\
         );
 #else
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -526,13 +549,15 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -572,12 +597,15 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -618,11 +646,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -635,7 +666,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -653,12 +684,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = -v;
@@ -674,7 +707,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -692,12 +725,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = ~v;
@@ -712,7 +747,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -730,12 +765,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -748,7 +785,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -766,12 +803,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -784,7 +823,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -802,16 +841,17 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -821,15 +861,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 4u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch64_base
 {
-    typedef typename storage_traits< 4u >::type storage_type;
+    using storage_type = typename storage_traits< 4u >::type;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 4u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 4u;
+    static constexpr std::size_t storage_alignment = 4u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -846,7 +887,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         }
     }
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -878,12 +919,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -895,7 +938,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
             : "memory"\
         );
 #else
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -912,13 +955,15 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -957,12 +1002,15 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -1002,11 +1050,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1019,7 +1070,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1037,12 +1088,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = -v;
@@ -1058,7 +1111,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1076,12 +1129,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = ~v;
@@ -1096,7 +1151,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1114,12 +1169,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1132,7 +1189,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1150,12 +1207,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1168,7 +1227,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1186,16 +1245,17 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -1205,15 +1265,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 8u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch64_base
 {
-    typedef typename storage_traits< 8u >::type storage_type;
+    using storage_type = typename storage_traits< 8u >::type;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 8u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 8u;
+    static constexpr std::size_t storage_alignment = 8u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -1230,7 +1291,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         }
     }
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -1262,12 +1323,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1279,7 +1342,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
             : "memory"\
         );
 #else
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1296,13 +1359,15 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -1341,12 +1406,15 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         original = expected;
@@ -1386,11 +1454,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1403,7 +1474,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1421,12 +1492,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = -v;
@@ -1442,7 +1515,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1460,12 +1533,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
         v = ~v;
@@ -1480,7 +1555,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1498,12 +1573,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1516,7 +1593,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1534,12 +1611,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
 #if defined(BOOST_ATOMIC_DETAIL_AARCH64_HAS_LSE)
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
@@ -1552,7 +1631,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         );
 #else
         storage_type result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1570,16 +1649,17 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original;
     }
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -1604,29 +1684,59 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 16u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch64_base
 {
-    typedef typename storage_traits< 16u >::type storage_type;
+    using storage_type = typename storage_traits< 16u >::type;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 16u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 16u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 16u;
+    static constexpr std::size_t storage_alignment = 16u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
     // Union to convert between two 64-bit registers and a 128-bit storage
     union storage_union
     {
         storage_type as_storage;
-        uint64_t as_uint64[2u];
+        std::uint64_t as_uint64[2u];
     };
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
-        exchange(storage, v, order);
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+        storage_union original;
+        storage_union value = { v };
+        std::uint32_t tmp;
+        if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
+        {
+            __asm__ __volatile__
+            (
+                "1:\n\t"
+                "ldxp %x[original_0], %x[original_1], %[storage]\n\t"
+                "stlxp %w[tmp], %x[value_0], %x[value_1], %[storage]\n\t"
+                "cbnz %w[tmp], 1b\n\t"
+                : [tmp] "=&r" (tmp), [storage] "+Q" (storage), [original_0] "=&r" (original.as_uint64[0u]), [original_1] "=&r" (original.as_uint64[1u])
+                : [value_0] "r" (value.as_uint64[0u]), [value_1] "r" (value.as_uint64[1u])
+                : "memory"
+            );
+        }
+        else
+        {
+            __asm__ __volatile__
+            (
+                "1:\n\t"
+                "ldxp %x[original_0], %x[original_1], %[storage]\n\t"
+                "stxp %w[tmp], %x[value_0], %x[value_1], %[storage]\n\t"
+                "cbnz %w[tmp], 1b\n\t"
+                : [tmp] "=&r" (tmp), [storage] "+Q" (storage), [original_0] "=&r" (original.as_uint64[0u]), [original_1] "=&r" (original.as_uint64[1u])
+                : [value_0] "r" (value.as_uint64[0u]), [value_1] "r" (value.as_uint64[1u])
+                : "memory"
+            );
+        }
     }
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_union v;
-        uint32_t tmp;
+        std::uint32_t tmp;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
         {
             __asm__ __volatile__
@@ -1653,15 +1763,17 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
                 : "memory"
             );
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v.as_storage;
     }
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1677,13 +1789,15 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_union original;
         storage_union e = { expected };
         storage_union d = { desired };
@@ -1709,12 +1823,15 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original.as_storage;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_union original;
         storage_union e = { expected };
         storage_union d = { desired };
@@ -1741,15 +1858,18 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
         expected = original.as_storage;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
         storage_union result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1769,16 +1889,18 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
         storage_union result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1798,16 +1920,18 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
         storage_union result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1827,16 +1951,18 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
         storage_union result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1856,16 +1982,18 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_union original;
         storage_union value = { v };
         storage_union result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
@@ -1885,16 +2013,17 @@ struct core_arch_operations< 16u, Signed, Interprocess > :
         BOOST_ATOMIC_DETAIL_AARCH64_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH64_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return original.as_storage;
     }
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }