passenger 6.1.0 → 6.1.1

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/core_arch_ops_gcc_x86.hpp

@@ -5,7 +5,7 @@
  *
  * Copyright (c) 2009 Helge Bahmann
  * Copyright (c) 2012 Tim Blechmann
- * Copyright (c) 2014 Andrey Semashev
+ * Copyright (c) 2014-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/core_arch_ops_gcc_x86.hpp
@@ -23,7 +23,7 @@
 #include <boost/atomic/detail/core_arch_operations_fwd.hpp>
 #include <boost/atomic/detail/capabilities.hpp>
 #if defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B) || defined(BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B)
-#include <boost/cstdint.hpp>
+#include <cstdint>
 #include <boost/atomic/detail/intptr.hpp>
 #include <boost/atomic/detail/string_ops.hpp>
 #include <boost/atomic/detail/core_ops_cas_based.hpp>
@@ -40,16 +40,16 @@ namespace detail {
 
 struct core_arch_operations_gcc_x86_base
 {
-    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+    static constexpr bool full_cas_based = false;
+    static constexpr bool is_always_lock_free = true;
 
-    static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void fence_before(memory_order order) noexcept
     {
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
             __asm__ __volatile__ ("" ::: "memory");
     }
 
-    static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void fence_after(memory_order order) noexcept
     {
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
             __asm__ __volatile__ ("" ::: "memory");
@@ -60,15 +60,16 @@ template< std::size_t Size, bool Signed, bool Interprocess, typename Derived >
 struct core_arch_operations_gcc_x86 :
     public core_arch_operations_gcc_x86_base
 {
-    typedef typename storage_traits< Size >::type storage_type;
+    using storage_type = typename storage_traits< Size >::type;
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = Size;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = Size;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = Size;
+    static constexpr std::size_t storage_alignment = Size;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if (order != memory_order_seq_cst)
         {
             fence_before(order);
@@ -81,30 +82,31 @@ struct core_arch_operations_gcc_x86 :
         }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v = storage;
         fence_after(order);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
         return Derived::fetch_add(storage, -v, order);
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
         return Derived::compare_exchange_strong(storage, expected, desired, success_order, failure_order);
     }
 
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!Derived::exchange(storage, (storage_type)1, order);
     }
 
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -114,12 +116,13 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 1u, Signed, Interprocess > :
     public core_arch_operations_gcc_x86< 1u, Signed, Interprocess, core_arch_operations< 1u, Signed, Interprocess > >
 {
-    typedef core_arch_operations_gcc_x86< 1u, Signed, Interprocess, core_arch_operations< 1u, Signed, Interprocess > > base_type;
-    typedef typename base_type::storage_type storage_type;
-    typedef typename storage_traits< 4u >::type temp_storage_type;
+    using base_type = core_arch_operations_gcc_x86< 1u, Signed, Interprocess, core_arch_operations< 1u, Signed, Interprocess > >;
+    using storage_type = typename base_type::storage_type;
+    using temp_storage_type = typename storage_traits< 4u >::type;
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "lock; xaddb %0, %1"
@@ -127,11 +130,13 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
             :
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "xchgb %0, %1"
@@ -139,12 +144,14 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
             :
             : "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type previous = expected;
         bool success;
 #if defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -166,6 +173,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
         expected = previous;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
 
@@ -183,24 +191,30 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"\
     )
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("andb", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("orb", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("xorb", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
@@ -211,12 +225,13 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 2u, Signed, Interprocess > :
     public core_arch_operations_gcc_x86< 2u, Signed, Interprocess, core_arch_operations< 2u, Signed, Interprocess > >
 {
-    typedef core_arch_operations_gcc_x86< 2u, Signed, Interprocess, core_arch_operations< 2u, Signed, Interprocess > > base_type;
-    typedef typename base_type::storage_type storage_type;
-    typedef typename storage_traits< 4u >::type temp_storage_type;
+    using base_type = core_arch_operations_gcc_x86< 2u, Signed, Interprocess, core_arch_operations< 2u, Signed, Interprocess > >;
+    using storage_type = typename base_type::storage_type;
+    using temp_storage_type = typename storage_traits< 4u >::type;
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "lock; xaddw %0, %1"
@@ -224,11 +239,13 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
             :
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "xchgw %0, %1"
@@ -236,12 +253,14 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
             :
             : "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type previous = expected;
         bool success;
 #if defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -263,6 +282,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
         expected = previous;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
 
@@ -280,24 +300,30 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"\
     )
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("andw", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("orw", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("xorw", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
@@ -308,11 +334,12 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 4u, Signed, Interprocess > :
     public core_arch_operations_gcc_x86< 4u, Signed, Interprocess, core_arch_operations< 4u, Signed, Interprocess > >
 {
-    typedef core_arch_operations_gcc_x86< 4u, Signed, Interprocess, core_arch_operations< 4u, Signed, Interprocess > > base_type;
-    typedef typename base_type::storage_type storage_type;
+    using base_type = core_arch_operations_gcc_x86< 4u, Signed, Interprocess, core_arch_operations< 4u, Signed, Interprocess > >;
+    using storage_type = typename base_type::storage_type;
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "lock; xaddl %0, %1"
@@ -320,11 +347,13 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
             :
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "xchgl %0, %1"
@@ -332,12 +361,14 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
             :
             : "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type previous = expected;
         bool success;
 #if defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -359,6 +390,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
         expected = previous;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
 
@@ -376,24 +408,30 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"\
     )
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("andl", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("orl", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("xorl", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
@@ -413,28 +451,30 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 template< bool Signed, bool Interprocess >
 struct gcc_dcas_x86
 {
-    typedef typename storage_traits< 8u >::type storage_type;
-    typedef uint32_t BOOST_ATOMIC_DETAIL_MAY_ALIAS aliasing_uint32_t;
+    using storage_type = typename storage_traits< 8u >::type;
+    using aliasing_uint32_t = std::uint32_t BOOST_ATOMIC_DETAIL_MAY_ALIAS;
 #if defined(__SSE2__)
-    typedef uint32_t xmm_t __attribute__((__vector_size__(16)));
+    using xmm_t = std::uint32_t __attribute__((__vector_size__(16)));
 #elif defined(__SSE__)
-    typedef float xmm_t __attribute__((__vector_size__(16)));
+    using xmm_t = float __attribute__((__vector_size__(16)));
 #endif
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 8u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
-    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = true;
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+    static constexpr std::size_t storage_size = 8u;
+    static constexpr std::size_t storage_alignment = 8u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
+    static constexpr bool full_cas_based = true;
+    static constexpr bool is_always_lock_free = true;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+
         if (BOOST_LIKELY(order != memory_order_seq_cst && (((uintptr_t)&storage) & 7u) == 0u))
         {
 #if defined(__SSE__)
 #if defined(__SSE2__)
-            xmm_t value = { static_cast< uint32_t >(v), static_cast< uint32_t >(v >> 32u), 0u, 0u };
+            xmm_t value = { static_cast< std::uint32_t >(v), static_cast< std::uint32_t >(v >> 32u), 0u, 0u };
 #else
             xmm_t value;
             BOOST_ATOMIC_DETAIL_MEMSET(&value, 0, sizeof(value));
@@ -478,7 +518,7 @@ struct gcc_dcas_x86
                 "jne 1b\n\t"
                 "xchgl %%ebx, %%esi\n\t"
                 :
-                : "a" ((uint32_t)v), "c" ((uint32_t)(v >> 32u)), [dest] "D" (&storage)
+                : "a" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u)), [dest] "D" (&storage)
                 : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "edx", "memory"
             );
 #else // defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
@@ -490,14 +530,14 @@ struct gcc_dcas_x86
                 "1: lock; cmpxchg8b %[dest_lo]\n\t"
                 "jne 1b\n\t"
                 : [dest_lo] "=m" (storage), [dest_hi] "=m" (reinterpret_cast< volatile aliasing_uint32_t* >(&storage)[1])
-                : [value_lo] "b" ((uint32_t)v), "c" ((uint32_t)(v >> 32u))
+                : [value_lo] "b" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u))
                 : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "eax", "edx", "memory"
             );
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
         }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type value;
 
@@ -543,7 +583,7 @@ struct gcc_dcas_x86
 
 #if defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-            uint32_t value_bits[2];
+            std::uint32_t value_bits[2];
 
             // We don't care for comparison result here; the previous value will be stored into value anyway.
             // Also we don't care for ebx and ecx values, they just have to be equal to eax and edx before cmpxchg8b.
@@ -575,12 +615,16 @@ struct gcc_dcas_x86
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
         }
 
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
+
         return value;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
+
 #if defined(__clang__)
 
         // Clang cannot allocate eax:edx register pairs but it has sync intrinsics
@@ -599,7 +643,7 @@ struct gcc_dcas_x86
             "lock; cmpxchg8b (%[dest])\n\t"
             "xchgl %%ebx, %%esi\n\t"
             : "+A" (expected), [success] "=@ccz" (success)
-            : "S" ((uint32_t)desired), "c" ((uint32_t)(desired >> 32u)), [dest] "D" (&storage)
+            : "S" ((std::uint32_t)desired), "c" ((std::uint32_t)(desired >> 32u)), [dest] "D" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #else // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -610,7 +654,7 @@ struct gcc_dcas_x86
             "xchgl %%ebx, %%esi\n\t"
             "sete %[success]\n\t"
             : "+A" (expected), [success] "=qm" (success)
-            : "S" ((uint32_t)desired), "c" ((uint32_t)(desired >> 32u)), [dest] "D" (&storage)
+            : "S" ((std::uint32_t)desired), "c" ((std::uint32_t)(desired >> 32u)), [dest] "D" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -626,7 +670,7 @@ struct gcc_dcas_x86
         (
             "lock; cmpxchg8b %[dest]\n\t"
             : "+A" (expected), [dest] "+m" (storage), [success] "=@ccz" (success)
-            : "b" ((uint32_t)desired), "c" ((uint32_t)(desired >> 32u))
+            : "b" ((std::uint32_t)desired), "c" ((std::uint32_t)(desired >> 32u))
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #else // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -635,28 +679,34 @@ struct gcc_dcas_x86
             "lock; cmpxchg8b %[dest]\n\t"
             "sete %[success]\n\t"
             : "+A" (expected), [dest] "+m" (storage), [success] "=qm" (success)
-            : "b" ((uint32_t)desired), "c" ((uint32_t)(desired >> 32u))
+            : "b" ((std::uint32_t)desired), "c" ((std::uint32_t)(desired >> 32u))
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
 
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
 
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
         return compare_exchange_strong(storage, expected, desired, success_order, failure_order);
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+
+        storage_type old_value;
+
 #if defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
 #if defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        uint32_t old_bits[2];
+        std::uint32_t old_bits[2];
         __asm__ __volatile__
         (
             "xchgl %%ebx, %%esi\n\t"
@@ -667,17 +717,14 @@ struct gcc_dcas_x86
             "jne 1b\n\t"
             "xchgl %%ebx, %%esi\n\t"
             : "=a" (old_bits[0]), "=d" (old_bits[1])
-            : "S" ((uint32_t)v), "c" ((uint32_t)(v >> 32u)), [dest] "D" (&storage)
+            : "S" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u)), [dest] "D" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        storage_type old_value;
         BOOST_ATOMIC_DETAIL_MEMCPY(&old_value, old_bits, sizeof(old_value));
-        return old_value;
 
 #else // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        storage_type old_value;
         __asm__ __volatile__
         (
             "xchgl %%ebx, %%esi\n\t"
@@ -688,17 +735,16 @@ struct gcc_dcas_x86
             "jne 1b\n\t"
             "xchgl %%ebx, %%esi\n\t"
             : "=A" (old_value)
-            : "S" ((uint32_t)v), "c" ((uint32_t)(v >> 32u)), [dest] "D" (&storage)
+            : "S" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u)), [dest] "D" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
-        return old_value;
 
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 #else // defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
 #if defined(__MINGW32__) && ((__GNUC__+0) * 100 + (__GNUC_MINOR__+0)) < 407
 
         // MinGW gcc up to 4.6 has problems with allocating registers in the asm blocks below
-        uint32_t old_bits[2];
+        std::uint32_t old_bits[2];
         __asm__ __volatile__
         (
             "movl (%[dest]), %%eax\n\t"
@@ -707,17 +753,15 @@ struct gcc_dcas_x86
             "1: lock; cmpxchg8b (%[dest])\n\t"
             "jne 1b\n\t"
             : "=&a" (old_bits[0]), "=&d" (old_bits[1])
-            : "b" ((uint32_t)v), "c" ((uint32_t)(v >> 32u)), [dest] "DS" (&storage)
+            : "b" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u)), [dest] "DS" (&storage)
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        storage_type old_value;
         BOOST_ATOMIC_DETAIL_MEMCPY(&old_value, old_bits, sizeof(old_value));
-        return old_value;
 
 #elif defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        uint32_t old_bits[2];
+        std::uint32_t old_bits[2];
         __asm__ __volatile__
         (
             "movl %[dest_lo], %%eax\n\t"
@@ -726,17 +770,14 @@ struct gcc_dcas_x86
             "1: lock; cmpxchg8b %[dest_lo]\n\t"
             "jne 1b\n\t"
             : "=&a" (old_bits[0]), "=&d" (old_bits[1]), [dest_lo] "+m" (storage), [dest_hi] "+m" (reinterpret_cast< volatile aliasing_uint32_t* >(&storage)[1])
-            : "b" ((uint32_t)v), "c" ((uint32_t)(v >> 32u))
+            : "b" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u))
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        storage_type old_value;
         BOOST_ATOMIC_DETAIL_MEMCPY(&old_value, old_bits, sizeof(old_value));
-        return old_value;
 
 #else // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        storage_type old_value;
         __asm__ __volatile__
         (
             "movl %[dest_lo], %%eax\n\t"
@@ -745,13 +786,16 @@ struct gcc_dcas_x86
             "1: lock; cmpxchg8b %[dest_lo]\n\t"
             "jne 1b\n\t"
             : "=&A" (old_value), [dest_lo] "+m" (storage), [dest_hi] "+m" (reinterpret_cast< volatile aliasing_uint32_t* >(&storage)[1])
-            : "b" ((uint32_t)v), "c" ((uint32_t)(v >> 32u))
+            : "b" ((std::uint32_t)v), "c" ((std::uint32_t)(v >> 32u))
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
-        return old_value;
 
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_ASM_PRESERVE_EBX)
+
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
+
+        return old_value;
     }
 };
 
@@ -767,11 +811,12 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 8u, Signed, Interprocess > :
     public core_arch_operations_gcc_x86< 8u, Signed, Interprocess, core_arch_operations< 8u, Signed, Interprocess > >
 {
-    typedef core_arch_operations_gcc_x86< 8u, Signed, Interprocess, core_arch_operations< 8u, Signed, Interprocess > > base_type;
-    typedef typename base_type::storage_type storage_type;
+    using base_type = core_arch_operations_gcc_x86< 8u, Signed, Interprocess, core_arch_operations< 8u, Signed, Interprocess > >;
+    using storage_type = typename base_type::storage_type;
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "lock; xaddq %0, %1"
@@ -779,11 +824,13 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
             :
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         __asm__ __volatile__
         (
             "xchgq %0, %1"
@@ -791,12 +838,14 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
             :
             : "memory"
         );
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return v;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type previous = expected;
         bool success;
 #if defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
@@ -818,6 +867,7 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
         expected = previous;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
         return success;
     }
 
@@ -835,24 +885,30 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
         : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"\
     )
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("andq", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("orq", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type res = storage;
         BOOST_ATOMIC_DETAIL_CAS_LOOP("xorq", v, res);
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
         return res;
     }
 
@@ -866,28 +922,30 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 template< bool Signed, bool Interprocess >
 struct gcc_dcas_x86_64
 {
-    typedef typename storage_traits< 16u >::type storage_type;
-    typedef uint64_t BOOST_ATOMIC_DETAIL_MAY_ALIAS aliasing_uint64_t;
+    using storage_type = typename storage_traits< 16u >::type;
+    using aliasing_uint64_t = std::uint64_t BOOST_ATOMIC_DETAIL_MAY_ALIAS;
 #if defined(__AVX__)
-    typedef uint64_t __attribute__((__vector_size__(16))) xmm_t;
+    using xmm_t = std::uint64_t __attribute__((__vector_size__(16)));
 #endif
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 16u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 16u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
-    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = true;
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+    static constexpr std::size_t storage_size = 16u;
+    static constexpr std::size_t storage_alignment = 16u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
+    static constexpr bool full_cas_based = true;
+    static constexpr bool is_always_lock_free = true;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+
 #if defined(__AVX__)
         if (BOOST_LIKELY(order != memory_order_seq_cst && (((uintptr_t)&storage) & 15u) == 0u))
         {
             // According to SDM Volume 3, 8.1.1 Guaranteed Atomic Operations, processors supporting AVX guarantee
             // aligned vector moves to be atomic.
 #if defined(BOOST_HAS_INT128)
-            xmm_t value = { static_cast< uint64_t >(v), static_cast< uint64_t >(v >> 64u) };
+            xmm_t value = { static_cast< std::uint64_t >(v), static_cast< std::uint64_t >(v >> 64u) };
 #else
             xmm_t value;
             BOOST_ATOMIC_DETAIL_MEMCPY(&value, &v, sizeof(v));
@@ -917,7 +975,7 @@ struct gcc_dcas_x86_64
         );
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
 #if defined(__AVX__)
         if (BOOST_LIKELY((((uintptr_t)&storage) & 15u) == 0u))
@@ -940,6 +998,7 @@ struct gcc_dcas_x86_64
             storage_type value;
             BOOST_ATOMIC_DETAIL_MEMCPY(&value, &v, sizeof(v));
 #endif
+            BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
             return value;
         }
 #endif // defined(__AVX__)
@@ -947,9 +1006,11 @@ struct gcc_dcas_x86_64
         // Note that despite const qualification cmpxchg16b below may issue a store to the storage. The storage value
         // will not change, but this prevents the storage to reside in read-only memory.
 
+        storage_type value;
+
 #if defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        uint64_t value_bits[2];
+        std::uint64_t value_bits[2];
 
         // We don't care for comparison result here; the previous value will be stored into value anyway.
         // Also we don't care for rbx and rcx values, they just have to be equal to rax and rdx before cmpxchg16b.
@@ -964,17 +1025,13 @@ struct gcc_dcas_x86_64
         );
 
 #if defined(BOOST_HAS_INT128)
-        storage_type value = static_cast< storage_type >(value_bits[0]) | (static_cast< storage_type >(value_bits[1]) << 64u);
+        value = static_cast< storage_type >(value_bits[0]) | (static_cast< storage_type >(value_bits[1]) << 64u);
 #else
-        storage_type value;
         BOOST_ATOMIC_DETAIL_MEMCPY(&value, value_bits, sizeof(value));
 #endif
-        return value;
 
 #else // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
-        storage_type value;
-
         // We don't care for comparison result here; the previous value will be stored into value anyway.
         // Also we don't care for rbx and rcx values, they just have to be equal to rax and rdx before cmpxchg16b.
         __asm__ __volatile__
@@ -987,20 +1044,24 @@ struct gcc_dcas_x86_64
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        return value;
-
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
+
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
+
+        return value;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order, memory_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
+
 #if defined(__clang__)
 
         // Clang cannot allocate rax:rdx register pairs but it has sync intrinsics
         storage_type old_expected = expected;
         expected = __sync_val_compare_and_swap(&storage, old_expected, desired);
-        return expected == old_expected;
+        const bool success = expected == old_expected;
 
 #elif defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
@@ -1015,8 +1076,6 @@ struct gcc_dcas_x86_64
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        return success;
-
 #else // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
 
         bool success;
@@ -1040,21 +1099,27 @@ struct gcc_dcas_x86_64
         );
 #endif // defined(BOOST_ATOMIC_DETAIL_ASM_HAS_FLAG_OUTPUTS)
 
-        return success;
-
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
+
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
+        return success;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
         return compare_exchange_strong(storage, expected, desired, success_order, failure_order);
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+
+        storage_type old_value;
+
 #if defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
-        uint64_t old_bits[2];
+        std::uint64_t old_bits[2];
         __asm__ __volatile__
         (
             "movq %[dest_lo], %%rax\n\t"
@@ -1068,14 +1133,13 @@ struct gcc_dcas_x86_64
         );
 
 #if defined(BOOST_HAS_INT128)
-        storage_type old_value = static_cast< storage_type >(old_bits[0]) | (static_cast< storage_type >(old_bits[1]) << 64u);
+        old_value = static_cast< storage_type >(old_bits[0]) | (static_cast< storage_type >(old_bits[1]) << 64u);
 #else
-        storage_type old_value;
         BOOST_ATOMIC_DETAIL_MEMCPY(&old_value, old_bits, sizeof(old_value));
 #endif
-        return old_value;
+
 #else // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
-        storage_type old_value;
+
         __asm__ __volatile__
         (
             "movq %[dest_lo], %%rax\n\t"
@@ -1088,8 +1152,11 @@ struct gcc_dcas_x86_64
             : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
         );
 
-        return old_value;
 #endif // defined(BOOST_ATOMIC_DETAIL_X86_NO_ASM_AX_DX_PAIRS)
+
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
+
+        return old_value;
     }
 };