passenger 6.1.0 → 6.1.1

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/core_arch_ops_gcc_aarch32.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/core_arch_ops_gcc_aarch32.hpp
@@ -15,7 +15,7 @@
 #define BOOST_ATOMIC_DETAIL_CORE_ARCH_OPS_GCC_AARCH32_HPP_INCLUDED_
 
 #include <cstddef>
-#include <boost/cstdint.hpp>
+#include <cstdint>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/storage_traits.hpp>
@@ -45,23 +45,24 @@ namespace detail {
 
 struct core_arch_operations_gcc_aarch32_base
 {
-    static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
-    static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+    static constexpr bool full_cas_based = false;
+    static constexpr bool is_always_lock_free = true;
 };
 
 template< bool Signed, bool Interprocess >
 struct core_arch_operations< 1u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch32_base
 {
-    typedef typename storage_traits< 1u >::type storage_type;
+    using storage_type = typename storage_traits< 1u >::type;
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 1u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 1u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 1u;
+    static constexpr std::size_t storage_alignment = 1u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -78,7 +79,7 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -95,14 +96,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -118,13 +121,15 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -147,12 +152,15 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -177,13 +185,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -200,14 +211,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -224,14 +237,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -248,14 +263,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -272,14 +289,16 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -296,16 +315,17 @@ struct core_arch_operations< 1u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
 
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -315,15 +335,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 2u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch32_base
 {
-    typedef typename storage_traits< 2u >::type storage_type;
+    using storage_type = typename storage_traits< 2u >::type;
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 2u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 2u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 2u;
+    static constexpr std::size_t storage_alignment = 2u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -340,7 +361,7 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -357,14 +378,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -380,13 +403,15 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -409,12 +434,15 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -439,13 +467,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -462,14 +493,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -486,14 +519,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -510,14 +545,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -534,14 +571,16 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -558,16 +597,17 @@ struct core_arch_operations< 2u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
 
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -577,15 +617,16 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 4u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch32_base
 {
-    typedef typename storage_traits< 4u >::type storage_type;
+    using storage_type = typename storage_traits< 4u >::type;
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 4u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 4u;
+    static constexpr std::size_t storage_alignment = 4u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
         {
             __asm__ __volatile__
@@ -602,7 +643,7 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type v;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -619,14 +660,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
         {
             v = storage;
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return v;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -642,13 +685,15 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -670,12 +715,15 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -699,13 +747,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
+
         return success;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -722,14 +773,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -746,14 +799,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -770,14 +825,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -794,14 +851,16 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -818,16 +877,17 @@ struct core_arch_operations< 4u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
 
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }
@@ -854,19 +914,49 @@ template< bool Signed, bool Interprocess >
 struct core_arch_operations< 8u, Signed, Interprocess > :
     public core_arch_operations_gcc_aarch32_base
 {
-    typedef typename storage_traits< 8u >::type storage_type;
+    using storage_type = typename storage_traits< 8u >::type;
 
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
-    static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 8u;
-    static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
-    static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
+    static constexpr std::size_t storage_size = 8u;
+    static constexpr std::size_t storage_alignment = 8u;
+    static constexpr bool is_signed = Signed;
+    static constexpr bool is_interprocess = Interprocess;
 
-    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
-        exchange(storage, v, order);
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
+        storage_type original;
+        std::uint32_t tmp;
+        if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
+        {
+            __asm__ __volatile__
+            (
+                "1:\n\t"
+                "ldrexd %1, %H1, %2\n\t"
+                "stlexd %0, %3, %H3, %2\n\t"
+                "teq %0, #0\n\t"
+                "bne 1b\n\t"
+                : "=&r" (tmp), "=&r" (original), "+Q" (storage)
+                : "r" (v)
+                : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
+            );
+        }
+        else
+        {
+            __asm__ __volatile__
+            (
+                "1:\n\t"
+                "ldrexd %1, %H1, %2\n\t"
+                "strexd %0, %3, %H3, %2\n\t"
+                "teq %0, #0\n\t"
+                "bne 1b\n\t"
+                : "=&r" (tmp), "=&r" (original), "+Q" (storage)
+                : "r" (v)
+                : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC_COMMA "memory"
+            );
+        }
     }
 
-    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) noexcept
     {
         storage_type original;
         if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
@@ -887,14 +977,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
                 : "Q" (storage)      // %1
             );
         }
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -910,13 +1002,15 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_weak(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -940,13 +1034,15 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
 
         return success;
     }
 
     static BOOST_FORCEINLINE bool compare_exchange_strong(
-        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+        storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, success_order);
         storage_type original;
         bool success;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
@@ -972,14 +1068,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
 
         expected = original;
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, (success ? success_order : failure_order));
 
         return success;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -997,14 +1095,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -1022,14 +1122,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -1047,14 +1149,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -1072,14 +1176,16 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) noexcept
     {
+        BOOST_ATOMIC_DETAIL_TSAN_RELEASE(&storage, order);
         storage_type original, result;
-        uint32_t tmp;
+        std::uint32_t tmp;
 #define BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN(ld_mo, st_mo)\
         __asm__ __volatile__\
         (\
@@ -1097,16 +1203,17 @@ struct core_arch_operations< 8u, Signed, Interprocess > :
 
         BOOST_ATOMIC_DETAIL_AARCH32_MO_SWITCH(order)
 #undef BOOST_ATOMIC_DETAIL_AARCH32_MO_INSN
+        BOOST_ATOMIC_DETAIL_TSAN_ACQUIRE(&storage, order);
 
         return original;
     }
 
-    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) noexcept
     {
         return !!exchange(storage, (storage_type)1, order);
     }
 
-    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) noexcept
     {
         store(storage, (storage_type)0, order);
     }