passenger 6.1.0 → 6.1.1

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_operations.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_operations.hpp
@@ -26,7 +26,7 @@ namespace boost {
 namespace atomics {
 namespace detail {
 
-typedef fence_operations_emulated fence_arch_operations;
+using fence_arch_operations = fence_operations_emulated;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_aarch32.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_aarch32.hpp
@@ -14,7 +14,6 @@
 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_AARCH32_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_AARCH32_HPP_INCLUDED_
 
-#include <boost/cstdint.hpp>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/capabilities.hpp>
@@ -31,7 +30,7 @@ namespace detail {
 //! Fence operations for AArch32
 struct fence_arch_operations_gcc_aarch32
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
         {
@@ -42,14 +41,14 @@ struct fence_arch_operations_gcc_aarch32
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_arch_operations_gcc_aarch32 fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_aarch32;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_aarch64.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_aarch64.hpp
@@ -29,7 +29,7 @@ namespace detail {
 //! Fence operations for AArch64
 struct fence_arch_operations_gcc_aarch64
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
         {
@@ -40,14 +40,14 @@ struct fence_arch_operations_gcc_aarch64
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_arch_operations_gcc_aarch64 fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_aarch64;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_alpha.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_alpha.hpp
@@ -29,20 +29,20 @@ namespace detail {
 //! Fence operations for Alpha
 struct fence_arch_operations_gcc_alpha
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("mb" ::: "memory");
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_arch_operations_gcc_alpha fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_alpha;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_arm.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_arm.hpp
@@ -14,7 +14,7 @@
 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
 
-#include <boost/cstdint.hpp>
+#include <cstdint>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/capabilities.hpp>
@@ -32,27 +32,27 @@ namespace detail {
 //! Fence operations for legacy ARM
 struct fence_arch_operations_gcc_arm
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             hardware_full_fence();
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 
-    static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void hardware_full_fence() noexcept
     {
         // A memory barrier is effected using a "co-processor 15" instruction,
         // though a separate assembler mnemonic is available for it in v7.
 
 #if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
         // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
-        // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
-        // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
+        // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See
+        // ARM Architecture Reference Manual, A8.8.43. Since we cannot detect binutils version at compile time, we'll have to always use this hack.
         __asm__ __volatile__
         (
 #if defined(__thumb2__)
@@ -65,7 +65,7 @@ struct fence_arch_operations_gcc_arm
             : "memory"
         );
 #else
-        uint32_t tmp;
+        std::uint32_t tmp;
         __asm__ __volatile__
         (
             BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
@@ -79,7 +79,7 @@ struct fence_arch_operations_gcc_arm
     }
 };
 
-typedef fence_arch_operations_gcc_arm fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_arm;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_ppc.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_ppc.hpp
@@ -29,7 +29,7 @@ namespace detail {
 //! Fence operations for PowerPC
 struct fence_arch_operations_gcc_ppc
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
         {
@@ -44,7 +44,7 @@ struct fence_arch_operations_gcc_ppc
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
         {
@@ -57,7 +57,7 @@ struct fence_arch_operations_gcc_ppc
     }
 };
 
-typedef fence_arch_operations_gcc_ppc fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_ppc;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_sparc.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_sparc.hpp
@@ -29,7 +29,7 @@ namespace detail {
 //! Fence operations for SPARC
 struct fence_arch_operations_gcc_sparc
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         switch (order)
         {
@@ -52,14 +52,14 @@ struct fence_arch_operations_gcc_sparc
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_arch_operations_gcc_sparc fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_sparc;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_gcc_x86.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_gcc_x86.hpp
@@ -29,7 +29,7 @@ namespace detail {
 //! Fence operations for x86
 struct fence_arch_operations_gcc_x86
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order == memory_order_seq_cst)
         {
@@ -51,14 +51,14 @@ struct fence_arch_operations_gcc_x86
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_arch_operations_gcc_x86 fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_gcc_x86;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_msvc_arm.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_msvc_arm.hpp
@@ -35,7 +35,7 @@ namespace detail {
 //! Fence operations for ARM
 struct fence_arch_operations_msvc_arm
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         BOOST_ATOMIC_DETAIL_COMPILER_BARRIER();
         if (order != memory_order_relaxed)
@@ -43,19 +43,19 @@ struct fence_arch_operations_msvc_arm
         BOOST_ATOMIC_DETAIL_COMPILER_BARRIER();
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             BOOST_ATOMIC_DETAIL_COMPILER_BARRIER();
     }
 
-    static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void hardware_full_fence() noexcept
     {
         __dmb(0xB); // _ARM_BARRIER_ISH, see armintr.h from MSVC 11 and later
     }
 };
 
-typedef fence_arch_operations_msvc_arm fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_msvc_arm;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_arch_ops_msvc_x86.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_arch_ops_msvc_x86.hpp
@@ -14,7 +14,7 @@
 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_MSVC_X86_HPP_INCLUDED_
 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_MSVC_X86_HPP_INCLUDED_
 
-#include <boost/cstdint.hpp>
+#include <cstdint>
 #include <boost/memory_order.hpp>
 #include <boost/atomic/detail/config.hpp>
 #include <boost/atomic/detail/interlocked.hpp>
@@ -32,14 +32,14 @@ namespace detail {
 //! Fence operations for x86
 struct fence_arch_operations_msvc_x86
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order == memory_order_seq_cst)
         {
             // See the comment in fence_ops_gcc_x86.hpp as to why we're not using mfence here.
             // We're not using __faststorefence() here because it generates an atomic operation
             // on [rsp]/[esp] location, which may alias valid data and cause false data dependency.
-            boost::uint32_t dummy;
+            std::uint32_t dummy;
             BOOST_ATOMIC_INTERLOCKED_INCREMENT(&dummy);
         }
         else if (order != memory_order_relaxed)
@@ -48,14 +48,14 @@ struct fence_arch_operations_msvc_x86
         }
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             BOOST_ATOMIC_DETAIL_COMPILER_BARRIER();
     }
 };
 
-typedef fence_arch_operations_msvc_x86 fence_arch_operations;
+using fence_arch_operations = fence_arch_operations_msvc_x86;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_operations.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_operations.hpp
@@ -26,7 +26,7 @@ namespace boost {
 namespace atomics {
 namespace detail {
 
-typedef fence_arch_operations fence_operations;
+using fence_operations = fence_arch_operations;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_operations_emulated.hpp

@@ -30,12 +30,12 @@ namespace detail {
 //! Fence operations based on lock pool
 struct fence_operations_emulated
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order) noexcept
     {
         atomics::detail::lock_pool::thread_fence();
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order) noexcept
     {
         atomics::detail::lock_pool::signal_fence();
     }

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_ops_gcc_atomic.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_ops_gcc_atomic.hpp
@@ -40,9 +40,9 @@ namespace detail {
 //! Fence operations based on gcc __atomic* intrinsics
 struct fence_operations_gcc_atomic
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
-#if defined(__x86_64__) || defined(__i386__)
+#if !defined(BOOST_ATOMIC_DETAIL_TSAN) && (defined(__x86_64__) || defined(__i386__))
         if (order != memory_order_seq_cst)
         {
             __atomic_thread_fence(atomics::detail::convert_memory_order_to_gcc(order));
@@ -58,13 +58,13 @@ struct fence_operations_gcc_atomic
 #endif
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         __atomic_signal_fence(atomics::detail::convert_memory_order_to_gcc(order));
     }
 };
 
-typedef fence_operations_gcc_atomic fence_operations;
+using fence_operations = fence_operations_gcc_atomic;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_ops_gcc_sync.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2020 Andrey Semashev
+ * Copyright (c) 2020-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_ops_gcc_sync.hpp
@@ -29,20 +29,20 @@ namespace detail {
 //! Fence operations based on gcc __sync* intrinsics
 struct fence_operations_gcc_sync
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __sync_synchronize();
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 };
 
-typedef fence_operations_gcc_sync fence_operations;
+using fence_operations = fence_operations_gcc_sync;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fence_ops_linux_arm.hpp

@@ -7,7 +7,7 @@
  * Copyright (c) 2009 Phil Endecott
  * Copyright (c) 2013 Tim Blechmann
  * Linux-specific code by Phil Endecott
- * Copyright (c) 2014 Andrey Semashev
+ * Copyright (c) 2014-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fence_ops_linux_arm.hpp
@@ -33,27 +33,27 @@ namespace detail {
 //! Fence operations based on Linux-specific system routines
 struct fence_operations_linux_arm
 {
-    static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void thread_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             hardware_full_fence();
     }
 
-    static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void signal_fence(memory_order order) noexcept
     {
         if (order != memory_order_relaxed)
             __asm__ __volatile__ ("" ::: "memory");
     }
 
-    static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE void hardware_full_fence() noexcept
     {
         // See the comment in core_ops_linux_arm.hpp regarding the function pointer below
-        typedef void (*kernel_dmb_t)(void);
-        ((kernel_dmb_t)0xffff0fa0)();
+        using kernel_dmb_t = void (void);
+        ((kernel_dmb_t*)0xffff0fa0)();
     }
 };
 
-typedef fence_operations_linux_arm fence_operations;
+using fence_operations = fence_operations_linux_arm;
 
 } // namespace detail
 } // namespace atomics

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fp_ops_emulated.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2018 Andrey Semashev
+ * Copyright (c) 2018-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fp_ops_emulated.hpp
@@ -34,12 +34,12 @@ template< typename Base, typename Value, std::size_t Size >
 struct fp_operations_emulated :
     public Base
 {
-    typedef Base base_type;
-    typedef typename base_type::storage_type storage_type;
-    typedef Value value_type;
-    typedef typename base_type::scoped_lock scoped_lock;
+    using base_type = Base;
+    using storage_type = typename base_type::storage_type;
+    using value_type = Value;
+    using scoped_lock = typename base_type::scoped_lock;
 
-    static value_type fetch_add(storage_type volatile& storage, value_type v, memory_order) BOOST_NOEXCEPT
+    static value_type fetch_add(storage_type volatile& storage, value_type v, memory_order) noexcept
     {
         static_assert(!base_type::is_interprocess, "Boost.Atomic: operation invoked on a non-lock-free inter-process atomic object");
         storage_type& s = const_cast< storage_type& >(storage);
@@ -50,7 +50,7 @@ struct fp_operations_emulated :
         return old_val;
     }
 
-    static value_type fetch_sub(storage_type volatile& storage, value_type v, memory_order) BOOST_NOEXCEPT
+    static value_type fetch_sub(storage_type volatile& storage, value_type v, memory_order) noexcept
     {
         static_assert(!base_type::is_interprocess, "Boost.Atomic: operation invoked on a non-lock-free inter-process atomic object");
         storage_type& s = const_cast< storage_type& >(storage);

data/src/cxx_supportlib/vendor-modified/boost/atomic/detail/fp_ops_generic.hpp

@@ -3,7 +3,7 @@
  * (See accompanying file LICENSE_1_0.txt or copy at
  * http://www.boost.org/LICENSE_1_0.txt)
  *
- * Copyright (c) 2018 Andrey Semashev
+ * Copyright (c) 2018-2025 Andrey Semashev
  */
 /*!
  * \file   atomic/detail/fp_ops_generic.hpp
@@ -35,11 +35,11 @@ template< typename Base, typename Value, std::size_t Size >
 struct fp_operations_generic :
     public Base
 {
-    typedef Base base_type;
-    typedef typename base_type::storage_type storage_type;
-    typedef Value value_type;
+    using base_type = Base;
+    using storage_type = typename base_type::storage_type;
+    using value_type = Value;
 
-    static BOOST_FORCEINLINE value_type fetch_add(storage_type volatile& storage, value_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE value_type fetch_add(storage_type volatile& storage, value_type v, memory_order order) noexcept
     {
         storage_type old_storage, new_storage;
         value_type old_val, new_val;
@@ -54,7 +54,7 @@ struct fp_operations_generic :
         return old_val;
     }
 
-    static BOOST_FORCEINLINE value_type fetch_sub(storage_type volatile& storage, value_type v, memory_order order) BOOST_NOEXCEPT
+    static BOOST_FORCEINLINE value_type fetch_sub(storage_type volatile& storage, value_type v, memory_order order) noexcept
     {
         storage_type old_storage, new_storage;
         value_type old_val, new_val;