metasm 1.0.0 → 1.0.5

data/{lib/metasm → metasm/cpu}/x86_64/debug.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/x86_64/opcodes'
+require 'metasm/cpu/x86_64/opcodes'
 
 module Metasm
 class X86_64
@@ -15,7 +15,7 @@ class X86_64
 		@dbg_register_flags ||= :rflags
 	end
 
-	def dbg_register_list 
+	def dbg_register_list
 		@dbg_register_list ||= [:rax, :rbx, :rcx, :rdx, :rsi, :rdi, :rbp, :rsp, :r8, :r9, :r10, :r11, :r12, :r13, :r14, :r15, :rip]
 	end
 
@@ -40,10 +40,10 @@ class X86_64
 	end
 	def dbg_func_arg_set(dbg, argnr, arg)
 		if dbg.class.name =~ /win/i
-			list = []
+			list = [:rcx, :rdx, :r8, :r9]
 			off = 0x20
 		else
-			list = []
+			list = [:rdi, :rsi, :rdx, :rcx, :r8, :r9]
 			off = 0
 		end
 		if r = list[argnr]

data/{lib/metasm → metasm/cpu}/x86_64/decode.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/x86_64/opcodes'
+require 'metasm/cpu/x86_64/opcodes'
 require 'metasm/decode'
 
 module Metasm
@@ -15,7 +15,7 @@ class X86_64
 			rm = byte & 7
 
 			if m == 3
-				rm |= 8 if pfx[:rex_b]
+				rm |= 8 if pfx[:rex_b] and (regclass != SimdReg or opsz != 64)	# mm8 -> mm0
 				return regclass.new(rm, opsz)
 			end
 
@@ -33,7 +33,12 @@ class X86_64
 				ii |= 8 if pfx[:rex_x]
 				if ii != 4
 					s = 1 << ((sib >> 6) & 3)
-					i = Reg.new(ii, adsz)
+					if pfx[:mrmvex]
+						i = SimdReg.new(ii, pfx[:mrmvex])
+					else
+						i = Reg.new(ii, adsz)
+					end
+
 				end
 
 				bb = sib & 7
@@ -62,6 +67,7 @@ class X86_64
 				imm = Expression[imm.reduce & ((1 << adsz) - 1)]
 			end
 
+			opsz = pfx[:argsz] if pfx[:argsz]
 			new adsz, opsz, s, i, b, imm, seg
 		end
 	end
@@ -103,7 +109,26 @@ class X86_64
 			v
 		}
 
-		opsz = op.props[:argsz] || (pfx[:rex_w] ? 64 : (pfx[:opsz] ? 16 : (op.props[:auto64] ? 64 : 32)))
+		pfx[:rex_r] = 1 if op.fields[:vex_r] and field_val[:vex_r] == 0
+		pfx[:rex_b] = 1 if op.fields[:vex_b] and field_val[:vex_b] == 0
+		pfx[:rex_x] = 1 if op.fields[:vex_x] and field_val[:vex_x] == 0
+		pfx[:rex_w] = 1 if op.fields[:vex_w] and field_val[:vex_w] == 1
+		di.instruction.prefix = pfx if not di.instruction.prefix and not pfx.empty?	# for opsz(di) + vex_w
+
+		case op.props[:needpfx]
+		when 0x66; pfx.delete :opsz
+		when 0x67; pfx.delete :adsz
+		when 0xF2, 0xF3; pfx.delete :rep
+		end
+
+		if op.props[:setip] and not op.props[:stopexec] and pfx[:seg]
+			case pfx.delete(:seg).val
+			when 1; pfx[:jmphint] = 'hintnojmp'
+			when 3; pfx[:jmphint] = 'hintjmp'
+			end
+		end
+
+		opsz = op.props[:argsz] || opsz(di)
 		adsz = pfx[:adsz] ? 32 : 64
 		mmxsz = (op.props[:xmmx] && pfx[:opsz]) ? 128 : 64
 
@@ -112,22 +137,31 @@ class X86_64
 			when :reg;    Reg.new     field_val_r[a], opsz
 			when :eeec;   CtrlReg.new field_val_r[a]
 			when :eeed;   DbgReg.new  field_val_r[a]
+			when :eeet;   TstReg.new  field_val_r[a]
 			when :seg2, :seg2A, :seg3, :seg3A; SegReg.new field_val[a]
-			when :regmmx; SimdReg.new field_val_r[a], mmxsz
+			when :regmmx; SimdReg.new field_val[a], mmxsz	# rex_r ignored
 			when :regxmm; SimdReg.new field_val_r[a], 128
+			when :regymm; SimdReg.new field_val_r[a], 256
 
 			when :farptr; Farptr.decode edata, @endianness, opsz
 			when :i8, :u8, :i16, :u16, :i32, :u32, :i64, :u64; Expression[edata.decode_imm(a, @endianness)]
 			when :i		# 64bit constants are sign-extended from :i32
 				type = (opsz == 64 ? op.props[:imm64] ? :a64 : :i32 : "#{op.props[:unsigned_imm] ? 'a' : 'i'}#{opsz}".to_sym )
- 				v = edata.decode_imm(type, @endianness)
+				v = edata.decode_imm(type, @endianness)
 				v &= 0xffff_ffff_ffff_ffff if opsz == 64 and op.props[:unsigned_imm] and v.kind_of? Integer
 				Expression[v]
 
-			when :mrm_imm;  ModRM.new(adsz, opsz, nil, nil, nil, Expression[edata.decode_imm("a#{adsz}".to_sym, @endianness)], pfx[:seg])
-			when :modrm, :modrmA; ModRM.decode edata, field_val[a], @endianness, adsz, opsz, pfx[:seg], Reg, pfx
-			when :modrmmmx; ModRM.decode edata, field_val[:modrm], @endianness, adsz, mmxsz, pfx[:seg], SimdReg, pfx
-			when :modrmxmm; ModRM.decode edata, field_val[:modrm], @endianness, adsz, 128, pfx[:seg], SimdReg, pfx
+			when :mrm_imm;  ModRM.new(adsz, opsz, nil, nil, nil, Expression[edata.decode_imm("a#{adsz}".to_sym, @endianness)], pfx.delete(:seg))
+			when :modrm; ModRM.decode edata, field_val[:modrm], @endianness, adsz, opsz, pfx.delete(:seg), Reg, pfx
+			when :modrmmmx; ModRM.decode edata, field_val[:modrm], @endianness, adsz, mmxsz, pfx.delete(:seg), SimdReg, pfx.merge(:argsz => op.props[:argsz])
+			when :modrmxmm; ModRM.decode edata, field_val[:modrm], @endianness, adsz, 128, pfx.delete(:seg), SimdReg, pfx.merge(:argsz => op.props[:argsz], :mrmvex => op.props[:mrmvex])
+			when :modrmymm; ModRM.decode edata, field_val[:modrm], @endianness, adsz, 256, pfx.delete(:seg), SimdReg, pfx.merge(:argsz => op.props[:argsz], :mrmvex => op.props[:mrmvex])
+
+			when :vexvreg; Reg.new((field_val[:vex_vvvv] ^ 0xf), opsz)
+			when :vexvxmm; SimdReg.new((field_val[:vex_vvvv] ^ 0xf), 128)
+			when :vexvymm; SimdReg.new((field_val[:vex_vvvv] ^ 0xf), 256)
+			when :i4xmm; SimdReg.new(edata.decode_imm(:u8, @endianness) >> 4, 128)
+			when :i4ymm; SimdReg.new(edata.decode_imm(:u8, @endianness) >> 4, 256)
 
 			when :regfp;  FpReg.new   field_val[a]
 			when :imm_val1; Expression[1]
@@ -142,6 +176,8 @@ class X86_64
 
 		di.bin_length += edata.ptr - before_ptr
 
+		return if edata.ptr > edata.length
+
 		if op.name == 'movsx' or op.name == 'movzx' or op.name == 'movsxd'
 			if op.name == 'movsxd'
 				di.instruction.args[1].sz = 32
@@ -157,12 +193,13 @@ class X86_64
 			else
 				di.instruction.args[0].sz = 32
 			end
+		elsif op.name == 'crc32'
+			di.instruction.args[0].sz = 32
 		end
 
 		# sil => bh
 		di.instruction.args.each { |a| a.val += 12 if a.kind_of? Reg and a.sz == 8 and not pfx[:rex] and a.val >= 4 and a.val <= 8 }
 
-		pfx.delete :seg
 		case pfx.delete(:rep)
 		when :nz
 			if di.opcode.props[:strop]
@@ -194,18 +231,24 @@ class X86_64
 		di
 	end
 
-	def opsz(di)
+	def opsz(di, op=nil)
 		if di and di.instruction.prefix and di.instruction.prefix[:rex_w]; 64
-		elsif di and di.instruction.prefix and di.instruction.prefix[:opsz]; 16
-		elsif di and di.opcode.props[:auto64]; 64
+		elsif di and di.instruction.prefix and di.instruction.prefix[:opsz] and (op || di.opcode).props[:needpfx] != 0x66; 16
+		elsif di and (op || di.opcode).props[:auto64]; 64
 		else 32
 		end
 	end
 
+	def adsz(di, op=nil)
+		if di and di.instruction.prefix and di.instruction.prefix[:adsz] and (op || di.opcode).props[:needpfx] != 0x67; 32
+		else 64
+		end
+	end
+
 	def register_symbols
 		[:rax, :rcx, :rdx, :rbx, :rsp, :rbp, :rsi, :rdi, :r8, :r9, :r10, :r11, :r12, :r13, :r14, :r15]
 	end
-	
+
 	# returns a DecodedFunction from a parsed C function prototype
 	def decode_c_function_prototype(cp, sym, orig=nil)
 		sym = cp.toplevel.symbol[sym] if sym.kind_of?(::String)

data/{lib/metasm → metasm/cpu}/x86_64/encode.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/x86_64/opcodes'
+require 'metasm/cpu/x86_64/opcodes'
 require 'metasm/encode'
 
 module Metasm
@@ -64,7 +64,7 @@ class X86_64
 					# sib
 					or_bits[4]
 
-					@b, @i = @i, @b if @s == 1 and (@i.val_enc == 4 or @b.val_enc == 5)
+					@b, @i = @i, @b if @s == 1 and @i.kind_of?(Reg) and (@i.val_enc == 4 or @b.val_enc == 5)
 
 					raise EncodeError, "Invalid ModRM #{self}" if @i.val == 4
 
@@ -76,20 +76,22 @@ class X86_64
 
 				imm ||= 0 if @b.val_enc == 5
 				if imm
+					i32 = :i32
+					i32 = :a32 if (self.b and self.b.sz == 32) or (self.i and self.i.sz == 32)
 					case Expression.in_range?(imm, :i8)
 					when true
 						or_bits[1<<6]
 						[ret << Expression.encode_imm(imm, :i8, endianness)]
 					when false
 						or_bits[2<<6]
-						[ret << Expression.encode_imm(imm, :a32, endianness)]
+						[ret << Expression.encode_imm(imm, i32, endianness)]
 					when nil
 						rets = ret.dup
 						or_bits[1<<6]
 						ret << @imm.encode(:i8, endianness)
 						rets, ret = ret, rets	# or_bits[] modifies ret directly
 						or_bits[2<<6]
-						ret << @imm.encode(:a32, endianness)
+						ret << @imm.encode(i32, endianness)
 						[ret, rets]
 					end
 				else
@@ -116,23 +118,30 @@ class X86_64
 			case k
 			when :jmp;  {:jmp => 0x3e, :nojmp => 0x2e}[v]
 			when :lock; 0xf0
-			when :rep;  {'repnz' => 0xf2, 'repz' => 0xf3, 'rep' => 0xf2}[v] # TODO
+			when :rep;  {'repnz' => 0xf2, 'repz' => 0xf3, 'rep' => 0xf2}[v]
+			when :jmphint; {'hintjmp' => 0x3e, 'hintnojmp' => 0x2e}[v]
+			when :seg; [0x26, 0x2E, 0x36, 0x3E, 0x64, 0x65][v.val]
 			end
 		}.compact.pack 'C*'
-		pfx << op.props[:needpfx] if op.props[:needpfx]
 
-		rex_w = rex_r = rex_x = rex_b = nil
+		rex_w = rex_r = rex_x = rex_b = 0
 		if op.name == 'movsx' or op.name == 'movzx' or op.name == 'movsxd'
 			case i.args[0].sz
 			when 64; rex_w = 1
 			when 32
 			when 16; pfx << 0x66
 			end
+		elsif op.name == 'crc32'
+			case i.args[1].sz
+			when 64; rex_w = 1
+			when 32;
+			when 16; pfx << 0x66
+			end
 		else
 			opsz = op.props[:argsz] || i.prefix[:sz]
 			oi.each { |oa, ia|
 				case oa
-				when :reg, :reg_eax, :modrm, :modrmA, :mrm_imm
+				when :reg, :reg_eax, :modrm, :mrm_imm
 					raise EncodeError, "Incompatible arg size in #{i}" if ia.sz and opsz and opsz != ia.sz
 					opsz = ia.sz
 				end
@@ -140,7 +149,7 @@ class X86_64
 			opsz ||= 64 if op.props[:auto64]
 			opsz = op.props[:opsz] if op.props[:opsz]	# XXX ?
 			case opsz
-			when 64; rex_w = 1 if not op.props[:auto64]
+			when 64; rex_w = 1 if not op.props[:auto64] and (not op.props[:argsz] or op.props[:opsz] == 64)
 			when 32; raise EncodeError, "Incompatible arg size in #{i}" if op.props[:auto64]
 			when 16; pfx << 0x66
 			end
@@ -168,25 +177,27 @@ class X86_64
 			when :reg
 				set_field[oa, ia.val_enc]
 				if op.fields[:reg][1] == 3
-					rex_r = ia.val_rex
+					rex_r = ia.val_rex || 0
 				else
-					rex_b = ia.val_rex
+					rex_b = ia.val_rex || 0
 				end
-			when :seg3, :seg3A, :seg2, :seg2A, :eeec, :eeed, :regfp, :regxmm, :regmmx
+			when :seg3, :seg3A, :seg2, :seg2A, :eeec, :eeed, :eeet, :regfp, :regmmx, :regxmm, :regymm
 				set_field[oa, ia.val & 7]
 				rex_r = 1 if ia.val > 7
 				pfx << 0x66 if oa == :regmmx and op.props[:xmmx] and ia.sz == 128
+			when :vexvreg, :vexvxmm, :vexvymm
+				set_field[:vex_vvvv, ia.val ^ 0xf]
 			when :imm_val1, :imm_val3, :reg_cl, :reg_eax, :reg_dx, :regfp0
 				# implicit
-			when :modrm, :modrmA, :modrmmmx, :modrmxmm
+			when :modrm, :modrmmmx, :modrmxmm, :modrmymm
 				# postpone, but we must set rex now
 				case ia
 				when ModRM
 					ia.encode(0, @endianness)	# could swap b/i
-					rex_x = ia.i.val_rex if ia.i
-					rex_b = ia.b.val_rex if ia.b
+					rex_x = ia.i.val_rex || 0 if ia.i
+					rex_b = ia.b.val_rex || 0 if ia.b
 				when Reg
-					rex_b = ia.val_rex
+					rex_b = ia.val_rex || 0
 				else
 					rex_b = ia.val >> 3
 				end
@@ -196,7 +207,7 @@ class X86_64
 			end
 		}
 
-		if !(op.args & [:modrm, :modrmA, :modrmxmm, :modrmmmx]).empty?
+		if !(op.args & [:modrm, :modrmmmx, :modrmxmm, :modrmymm]).empty?
 			# reg field of modrm
 			regval = (base[-1] >> 3) & 7
 			base.pop
@@ -210,20 +221,26 @@ class X86_64
 			postponed.first[1] = Expression[target, :-, postlabel]
 		end
 
-		if rex_w == 1 or rex_r == 1 or rex_b == 1 or rex_x == 1 or i.args.grep(Reg).find { |r| r.sz == 8 and r.val >= 4 and r.val < 8 }
-			rex ||= 0x40
-			rex |= 1 if rex_b.to_i > 0
-			rex |= 2 if rex_x.to_i > 0
-			rex |= 4 if rex_r.to_i > 0
-			rex |= 8 if rex_w.to_i > 0
+		pfx << op.props[:needpfx] if op.props[:needpfx]
+
+		if op.fields[:vex_r]
+			set_field[:vex_r, rex_r ^ 1]
+			set_field[:vex_x, rex_x ^ 1] if op.fields[:vex_x]
+			set_field[:vex_b, rex_b ^ 1] if op.fields[:vex_b]
+			set_field[:vex_w, rex_w] if op.fields[:vex_w]
+		elsif rex_r + rex_x + rex_b + rex_w >= 1 or i.args.grep(Reg).find { |r| r.sz == 8 and r.val >= 4 and r.val < 8 }
+			rex = 0x40
+			rex |= 1 if rex_b == 1
+			rex |= 2 if rex_x == 1
+			rex |= 4 if rex_r == 1
+			rex |= 8 if rex_w == 1
+			pfx << rex
 		end
-		pfx << rex if rex
 		ret = EncodedData.new(pfx + base.pack('C*'))
 
 		postponed.each { |oa, ia|
 			case oa
-			when :farptr; ed = ia.encode(@endianness, "a#{opsz}".to_sym)
-			when :modrm, :modrmA, :modrmmmx, :modrmxmm
+			when :modrm, :modrmmmx, :modrmxmm, :modrmymm
 				if ia.kind_of? ModRM
 					ed = ia.encode(regval, @endianness)
 					if ed.kind_of?(::Array)
@@ -243,8 +260,22 @@ class X86_64
 			when :mrm_imm; ed = ia.imm.encode("a#{op.props[:adsz] || 64}".to_sym, @endianness)
 			when :i8, :u8, :i16, :u16, :i32, :u32, :i64, :u64; ed = ia.encode(oa, @endianness)
 			when :i
-				type = (opsz == 64 ? op.props[:imm64] ? :a64 : :i32 : "#{op.props[:unsigned_imm] ? 'a' : 'i'}#{opsz}".to_sym)
-			       	ed = ia.encode(type, @endianness)
+				type = if opsz == 64
+					if op.props[:imm64]
+						:a64
+					else
+						if _ia = ia.reduce and _ia.kind_of?(Integer) and _ia > 0 and (_ia >> 63) == 1
+							# handle 0xffffffff_ffffffff -> -1, which should fit in i32
+							ia = Expression[_ia - (1 << 64)]
+						end
+						:i32
+					end
+				else
+					"a#{opsz}".to_sym
+				end
+				ed = ia.encode(type, @endianness)
+			when :i4xmm, :i4ymm
+				ed = ia.val << 4	# u8
 			else raise SyntaxError, "Internal error: want to encode field #{oa.inspect} as arg in #{i}"
 			end
 

data/{lib/metasm → metasm/cpu}/x86_64/main.rb

@@ -5,19 +5,27 @@
 
 
 require 'metasm/main'
-require 'metasm/ia32'
+require 'metasm/cpu/ia32'
 
 module Metasm
 
 # The x86_64, 64-bit extension of the x86 CPU (x64, em64t, amd64...)
 class X86_64 < Ia32
 	# FpReg, SegReg, Farptr unchanged
-	# XXX ST(15) ?
 
-	# Simd extended to 16 regs, xmm only (mmx gone with 80387)
+	# XMM extended to 16 regs, YMM
 	class SimdReg < Ia32::SimdReg
-		double_map  64 => (0..15).map { |n| "mm#{n}" },
-   			   128 => (0..15).map { |n| "xmm#{n}" }
+		double_map  64 => (0..7).map { |n| "mm#{n}" },
+			   128 => (0..15).map { |n| "xmm#{n}" },
+			   256 => (0..15).map { |n| "ymm#{n}" }
+
+		def val_enc
+			@val & 7
+		end
+
+		def val_rex
+			@val >> 3
+		end
 	end
 
 	# general purpose registers, all sizes
@@ -94,6 +102,10 @@ class X86_64 < Ia32
 		simple_map((0..15).map { |i| [i, "cr#{i}"] })
 	end
 
+	class TstReg < Ia32::TstReg
+		simple_map((0..15).map { |i| [i, "tr#{i}"] })
+	end
+
 	# Create a new instance of an X86 cpu
 	# arguments (any order)
 	# - instruction set (386, 486, sse2...) [latest]
@@ -121,7 +133,7 @@ class X86_64 < Ia32
 
 	def str_to_reg(str)
 		# X86_64::Reg != Ia32::Reg
-		Reg.from_str(str) if Reg.s_to_i.has_key? str
+		Reg.s_to_i.has_key?(str) ? Reg.from_str(str) : SimdReg.s_to_i.has_key?(str) ? SimdReg.from_str(str) : nil
 	end
 
 	def shortname

data/metasm/cpu/x86_64/opcodes.rb

@@ -0,0 +1,138 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/cpu/x86_64/main'
+require 'metasm/cpu/ia32/opcodes'
+
+module Metasm
+class X86_64
+	def init_cpu_constants
+		super()
+		[:i32, :u32, :i64, :u64].each { |a| @valid_args[a] = true }
+	end
+
+	def init_386_common_only
+		super()
+		# :imm64 => accept a real int64 as :i argument
+		# :auto64 => ignore rex_w, always 64-bit op
+		# :op32no64 => if write to a 32-bit reg, dont zero the top 32-bits of dest
+		[:imm64, :auto64, :op32no64].each { |a| @valid_props[a] = true }
+		@opcode_list.delete_if { |o| o.bin[0].to_i & 0xf0 == 0x40 }	# now REX prefix
+		@opcode_list.each { |o|
+			o.props[:imm64] = true if o.bin == [0xB8]	# mov reg, <true imm64>
+			o.props[:auto64] = true if o.name =~ /^(j.*|loop.*|call|enter|leave|push|pop|ret)$/
+		}
+		addop 'movsxd', [0x63], :mrm
+		addop('cdqe', [0x98]) { |o| o.props[:opsz] = 64 }
+		addop('cqo',  [0x99]) { |o| o.props[:opsz] = 64 }
+	end
+
+	# all x86_64 cpu understand <= sse2 instrs
+	def init_x8664_only
+		init_386_common_only
+		init_386_only
+		init_387_only
+		init_486_only
+		init_pentium_only
+		init_p6_only
+		init_sse_only
+		init_sse2_only
+
+		@opcode_list.delete_if { |o|
+			o.args.include?(:seg2) or
+			o.args.include?(:seg2A) or
+			o.args.include?(:farptr) or
+			%w[aaa aad aam aas bound daa das into jcxz jecxz
+			 lds les loadall arpl pusha pushad popa popad pushfd popfd
+			].include?(o.name.split('.')[0])
+			 # split needed for lds.a32
+		}
+
+		@opcode_list.each { |o|
+			o.props[:auto64] = true if o.name =~ /^(enter|leave|[sl]gdt|[sl]idt|[sl]ldt|[sl]tr|push|pop|syscall)$/
+		}
+
+		addop('cmpxchg16b', [0x0F, 0xC7], 1) { |o| o.props[:opsz] = 64 ; o.props[:argsz] = 128 }
+		addop('iretq', [0xCF], nil, :stopexec, :setip) { |o| o.props[:opsz] = 64 } ; opcode_list.unshift opcode_list.pop
+		addop('pushfq', [0x9C]) { |o| o.props[:auto64] = true }
+		addop('popfq',  [0x9D]) { |o| o.props[:auto64] = true }
+		addop 'swapgs', [0x0F, 0x01, 0xF8]
+
+		addop('movq',  [0x0F, 0x6E], :mrmmmx, {:d => [1, 4]}) { |o| o.args = [:regmmx, :modrm] ; o.props[:opsz] = o.props[:argsz] = 64 }
+		addop('movq',  [0x0F, 0x6E], :mrmxmm, {:d => [1, 4]}) { |o| o.args = [:regxmm, :modrm] ; o.props[:opsz] = o.props[:argsz] = 64 ; o.props[:needpfx] = 0x66 }
+		addop('jecxz', [0xE3], nil, :setip, :i8) { |o| o.props[:adsz] = 32 }
+		addop('jrcxz', [0xE3], nil, :setip, :i8) { |o| o.props[:adsz] = 64 }
+	end
+
+	def init_sse3
+		init_x8664_only
+		init_sse3_only
+	end
+
+	def init_sse41_only
+		super()
+		addop('pextrq', [0x0F, 0x3A, 0x16], :mrmxmm, :u8) { |o| o.props[:needpfx] = 0x66; o.args[o.args.index(:modrmxmm)] = :modrm; o.props[:opsz] = o.props[:argsz] = 64 }
+		addop('pinsrq', [0x0F, 0x3A, 0x22], :mrmxmm, :u8) { |o| o.props[:needpfx] = 0x66; o.args[o.args.index(:modrmxmm)] = :modrm; o.props[:opsz] = o.props[:argsz] = 64 }
+	end
+
+	def init_avx_only
+		super()
+		addop('rdfsbase', [0x0F, 0xAE], 0, :modrmR) { |o| o.props[:needpfx] = 0xF3 }
+		addop('rdgsbase', [0x0F, 0xAE], 1, :modrmR) { |o| o.props[:needpfx] = 0xF3 }
+		addop('wrfsbase', [0x0F, 0xAE], 2, :modrmR) { |o| o.props[:needpfx] = 0xF3 }
+		addop('wrgsbase', [0x0F, 0xAE], 3, :modrmR) { |o| o.props[:needpfx] = 0xF3 }
+	end
+
+	def addop_macrostr(name, bin, type)
+		super(name, bin, type)
+		bin = bin.dup
+		bin[0] |= 1
+		addop(name+'q', bin) { |o| o.props[:opsz] = 64 ; o.props[type] = true }
+	end
+
+	def addop_macroret(name, bin, *args)
+		addop(name + '.i64', bin, nil, :stopexec, :setip, *args) { |o| o.props[:opsz] = 64 }
+		super(name, bin, *args)
+	end
+
+	def addop_post(op)
+		if op.fields[:d] or op.fields[:w] or op.fields[:s] or op.args.first == :regfp0
+			return super(op)
+		end
+
+		if op.props[:needpfx]
+			@opcode_list.unshift op
+		else
+			@opcode_list << op
+		end
+
+		if op.args == [:i] or op.name == 'ret'
+			# define opsz-override version for ambiguous opcodes
+			op16 = op.dup
+			op16.name << '.i16'
+			op16.props[:opsz] = 16
+			@opcode_list << op16
+			# push call ret jz  can't 32bit
+			op64 = op.dup
+			op64.name << '.i64'
+			op64.props[:opsz] = 64
+			@opcode_list << op64
+		elsif op.props[:strop] or op.props[:stropz] or op.args.include? :mrm_imm or
+				op.args.include? :modrm or op.name =~ /loop|xlat/
+			# define adsz-override version for ambiguous opcodes (movsq)
+			# XXX loop pfx 67 = rip+ecx, 66/rex ignored
+			op32 = op.dup
+			op32.name << '.a32'
+			op32.props[:adsz] = 32
+			@opcode_list << op32
+			op64 = op.dup
+			op64.name << '.a64'
+			op64.props[:adsz] = 64
+			@opcode_list << op64
+		end
+	end
+end
+end