metasm 1.0.0 → 1.0.5

data/metasm/cpu/mips.rb

@@ -0,0 +1,14 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+class Metasm::MIPS < Metasm::CPU
+end
+
+require 'metasm/main'
+require 'metasm/cpu/mips/parse'
+require 'metasm/cpu/mips/encode'
+require 'metasm/cpu/mips/decode'
+require 'metasm/cpu/mips/render'
+require 'metasm/cpu/mips/debug'

data/metasm/cpu/mips/debug.rb

@@ -0,0 +1,42 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/main'
+
+module Metasm
+class MIPS
+	def dbg_register_pc
+		@dbg_register_pc ||= :pc
+	end
+	def dbg_register_flags
+		@dbg_register_flags ||= :flags
+	end
+
+	def dbg_register_list
+		@dbg_register_list ||= %w[z0 at v0 v1 a0 a1 a2 a3
+					t0 t1 t2 t3 t4 t5 t6 t7
+					s0 s1 s2 s3 s4 s5 s6 s7
+					t8 t9 k0 k1 gp sp fp ra
+					sr mullo mulhi badva cause pc].map { |r| r.to_sym }
+	end
+
+	def dbg_flag_list
+		@dbg_flag_list ||= []
+	end
+
+	def dbg_register_size
+		@dbg_register_size ||= Hash.new(@size)
+	end
+
+	def dbg_need_stepover(dbg, addr, di)
+		di and di.opcode.props[:saveip]
+	end
+
+	def dbg_end_stepout(dbg, addr, di)
+		di and di.opcode.name == 'foobar'	# TODO
+	end
+end
+end

data/{lib/metasm → metasm/cpu}/mips/decode.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/mips/opcodes'
+require 'metasm/cpu/mips/opcodes'
 require 'metasm/decode'
 
 module Metasm
@@ -35,30 +35,46 @@ class MIPS
 	end
 
 	def decode_findopcode(edata)
-		return if edata.ptr >= edata.data.length
-		# TODO handle relocations !!
 		di = DecodedInstruction.new(self)
 		val = edata.decode_imm(:u32, @endianness)
 		edata.ptr -= 4
-		di if di.opcode = @bin_lookaside[val >> 24].find { |op|
-			(op.bin & op.bin_mask) == (val & op.bin_mask)
-		}
+		if val.kind_of?(Expression)
+			# relocations
+			hval = Expression[val, :&, 0xff000000].reduce
+			if hval.kind_of?(Expression)
+				# reloc_i26
+				if hval.kind_of?(Expression) and pat = hval.match(Expression[['a', :&, 0x300_0000], :|, 'b'], 'a', 'b')
+					hval = pat['b']
+				end
+			end
+			di if di.opcode = @bin_lookaside[hval >> 24].find { |op|
+				(op.bin & op.bin_mask) == Expression[val, :&, op.bin_mask].reduce
+			}
+		else
+			di if di.opcode = @bin_lookaside[val >> 24].find { |op|
+				(op.bin & op.bin_mask) == (val & op.bin_mask)
+			}
+		end
 	end
 
 	def decode_instr_op(edata, di)
-		# TODO handle relocations !!
 		before_ptr = edata.ptr
 		op = di.opcode
 		di.instruction.opname = op.name
 		val = edata.decode_imm(:u32, @endianness)
 
 		field_val = lambda { |f|
-			r = (val >> @fields_shift[f]) & @fields_mask[f]
-			# XXX do that cleanly (Expr.decode_imm)
+			if val.kind_of?(Expression)
+				r = Expression[[val, :>>, @fields_shift[f]], :&, @fields_mask[f]].reduce
+			else
+				r = (val >> @fields_shift[f]) & @fields_mask[f]
+			end
+
+			next r if r.kind_of?(Expression)
 			case f
-			when :sa, :i16, :it; r = Expression.make_signed(r, 16)
+			when :msbd; r += 1
+			when :i16; r = Expression.make_signed(r, 16)
 			when :i20; r = Expression.make_signed(r, 20)
-			when :i26; r = Expression.make_signed(r, 26)
 			else r
 			end
 		}
@@ -66,15 +82,23 @@ class MIPS
 		op.args.each { |a|
 			di.instruction.args << case a
 			when :rs, :rt, :rd; Reg.new field_val[a]
-			when :sa, :i16, :i20, :i26, :it; Expression[field_val[a]]
-			when :rs_i16; Memref.new Reg.new(field_val[:rs]), Expression[field_val[:i16]]
+			when :sa, :i16, :i20, :i26, :it, :msbd, :sel, :idb; Expression[field_val[a]]
+			when :rs_i16
+				len = 32
+				len = 64 if op.props[:m64]
+				len = 16 if op.props[:mi16] or op.props[:mu16]
+				len = 8  if op.props[:mi8 ] or op.props[:mu8]
+				Memref.new Reg.new(field_val[:rs]), Expression[field_val[:i16]], len
 			when :ft; FpReg.new field_val[a]
-			when :idm1, :idb; Expression['unsupported']
+			when :idm1; Expression['unsupported']
 			else raise SyntaxError, "Internal error: invalid argument #{a} in #{op.name}"
 			end
 		}
+
 		di.bin_length += edata.ptr - before_ptr
 
+		return false if edata.ptr > edata.length
+
 		di
 	end
 
@@ -86,7 +110,13 @@ class MIPS
 		if di.opcode.props[:setip] and di.instruction.args.last.kind_of? Expression and di.opcode.name[0] != ?t
 			delta = Expression[di.instruction.args.last, :<<, 2].reduce
 			if di.opcode.args.include? :i26
-				arg = Expression[[[addr, :+, di.bin_length], :&, 0xfc00_0000], :+, delta].reduce
+				# absolute jump in the 0x3ff_ffff region surrounding next_pc
+				if delta.kind_of? Expression and delta.op == :& and delta.rexpr == 0xfff_fffc
+					# relocated arg: assume the linker mapped so that instr&target are in the same region
+					arg = Expression[delta.lexpr].reduce
+				else
+					arg = Expression[[[addr, :+, di.bin_length], :&, 0xf000_0000], :+, delta].reduce
+				end
 			else
 				arg = Expression[[addr, :+, di.bin_length], :+, delta].reduce
 			end
@@ -96,12 +126,6 @@ class MIPS
 		di
 	end
 
-	# hash opname => lambda { |di, *sym_args| binding }
-	def backtrace_binding
-		@backtrace_binding ||= init_backtrace_binding
-	end
-	def backtrace_binding=(b) @backtrace_binding = b end
-
 	def init_backtrace_binding
 		@backtrace_binding ||= {}
 		opcode_list.map { |ol| ol.name }.uniq.each { |op|
@@ -112,18 +136,19 @@ class MIPS
 				{ :$ra => Expression[Expression[di.address, :+, 2*di.bin_length].reduce] }
 			}
 			when 'nop', 'j', 'jr', /^b/; lambda { |di, *a| {} }
-			when 'lui'; lambda { |di, a0, a1| { a0 => Expression[a1, :<<, 16] } }
+			when 'lui'; lambda { |di, a0, a1| { a0 => Expression[[a1, :&, 0xffff], :<<, 16] } }
 			when 'add', 'addu', 'addi', 'addiu'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :+, a2] } }	# XXX addiu $sp, -40h should be addiu $sp, 0xffc0 from the books, but..
 			when 'sub', 'subu'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :-, a2] } }
 			when 'slt', 'slti'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :<, a2] } }
 			when 'and', 'andi'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :&, a2] } }
 			when 'or', 'ori';   lambda { |di, a0, a1, a2|   { a0 => Expression[a1, :|, a2] } }
 			when 'nor'; lambda { |di, a0, a1, a2| { a0 => Expression[:~, [a1, :|, a2]] } }
+			when 'not'; lambda { |di, a0, a1| { a0 => Expression[:~, a1] } }
 			when 'xor'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :^, a2] } }
 			when 'sll', 'sllv'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :>>, a2] } }
 			when 'srl', 'srlv', 'sra', 'srav'; lambda { |di, a0, a1, a2| { a0 => Expression[a1, :<<, a2] } }	# XXX sign-extend
-			when 'lw';        lambda { |di, a0, a1| { a0 => Expression[a1] } }
-			when 'sw';        lambda { |di, a0, a1| { a1 => Expression[a0] } }
+			when 'lw', 'lwl', 'lwr'; lambda { |di, a0, a1| { a0 => Expression[a1] } }
+			when 'sw', 'swl', 'swr'; lambda { |di, a0, a1| { a1 => Expression[a0] } }
 			when 'lh', 'lhu'; lambda { |di, a0, a1| { a0 => Expression[a1] } }	# XXX sign-extend
 			when 'sh';        lambda { |di, a0, a1| { a1 => Expression[a0] } }
 			when 'lb', 'lbu'; lambda { |di, a0, a1| { a0 => Expression[a1] } }
@@ -131,11 +156,12 @@ class MIPS
 			when /^slti?u?/;  lambda { |di, a0, a1, a2| { a0 => Expression[a1, :<, a2] } }	# XXX signedness
 			when 'mfhi'; lambda { |di, a0| { a0 => Expression[:hi] } }
 			when 'mflo'; lambda { |di, a0| { a0 => Expression[:lo] } }
-			when 'mult'; lambda { |di, a0, a1| { :hi => Expression[[a0, :*, a1], :>>, 32], :lo => Expression[[a0, :*, a1], :&, 0xffff_ffff] } }
-			when 'div';  lambda { |di, a0, a1| { :hi => Expression[a0, :%, a1], :lo => Expression[a0, :/, a1] } }
+			when 'mult', 'multu'; lambda { |di, a0, a1| { :hi => Expression[[a0, :*, a1], :>>, 32], :lo => Expression[[a0, :*, a1], :&, 0xffff_ffff] } }
+			when 'div', 'divu';  lambda { |di, a0, a1| { :hi => Expression[a0, :%, a1], :lo => Expression[a0, :/, a1] } }
 			when 'jal', 'jalr'; lambda { |di, a0| { :$ra => Expression[Expression[di.address, :+, 2*di.bin_length].reduce] } }
 			when 'li', 'mov'; lambda { |di, a0, a1| { a0 => Expression[a1] } }
 			when 'syscall'; lambda { |di, *a| { :$v0 => Expression::Unknown } }
+			when /^b/; lambda { |di, *a| {} }
 			end
 
 			@backtrace_binding[op] ||= binding if binding
@@ -146,25 +172,20 @@ class MIPS
 	def get_backtrace_binding(di)
 		a = di.instruction.args.map { |arg|
 			case arg
-			when Memref; arg.symbolic(di.address)
+			when Memref; arg.symbolic(di)
 			when Reg; arg.symbolic
 			else arg
 			end
 		}
 
-		binding = if binding = backtrace_binding[di.instruction.opname]
-			binding[di, *a]
+		if binding = backtrace_binding[di.instruction.opname]
+			bd = binding[di, *a]
+			bd.delete 0	# allow add $zero, 42 => nop
+			bd
 		else
-			if di.instruction.opname[0] == ?b and di.opcode.props[:setip]
-			else
-				puts "unknown instruction to emu #{di}" if $VERBOSE
-			end
-			{}
+			puts "unhandled instruction to backtrace: #{di}" if $VERBOSE
+			{:incomplete_binding => Expression[1]}
 		end
-
-		binding.delete 0	# allow add $zero, 42 => nop
-
-		binding
 	end
 
 	def get_xrefs_x(dasm, di)

data/{lib/metasm → metasm/cpu}/mips/encode.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/mips/opcodes'
+require 'metasm/cpu/mips/opcodes'
 require 'metasm/encode'
 
 module Metasm
@@ -40,12 +40,13 @@ class MIPS
 			when :rs_i16
 				set_field[:rs, arg.base.i]
 				val, mask, shift = arg.offset, @fields_mask[:i16], @fields_shift[:i16]
-			when :sa, :i16, :i20, :i26
+			when :sa, :i16, :i20, :i26, :it, :msbd, :sel, :idb
 				val, mask, shift = arg, @fields_mask[sym], @fields_shift[sym]
+				val = Expression[val, :-, 1] if sym == :msbd
 			end
 		}
 
-		Expression[base, :+, [[val, :&, mask], :<<, shift]].encode(:u32, @endianness) << postdata
+		Expression[base, :|, [[val, :&, mask], :<<, shift]].encode(:u32, @endianness) << postdata
 	end
 end
 end

data/{lib/metasm → metasm/cpu}/mips/main.rb

@@ -26,7 +26,7 @@ class MIPS < CPU
 		end
 
 		Sym = @i_to_s.sort.map { |k, v| v.to_sym }
-		def symbolic ; @i == 0 ? 0 : Sym[@i] end
+		def symbolic(di=nil) ; @i == 0 ? 0 : Sym[@i] end
 	end
 
 	class FpReg
@@ -43,16 +43,16 @@ class MIPS < CPU
 	end
 
 	class Memref
-		attr_accessor :base, :offset
-		def initialize(base, offset)
-			@base, @offset = base, offset
+		attr_accessor :base, :offset, :sz
+		def initialize(base, offset, sz=32)
+			@base, @offset, @sz = base, offset, sz
 		end
 
-		def symbolic(orig)
+		def symbolic(di=nil)
 			p = nil
 			p = Expression[p, :+, @base.symbolic] if base
 			p = Expression[p, :+, @offset] if offset
-			Indirection[p.reduce, 4, orig]
+			Indirection[p.reduce, @sz/8, (di.address if di)]
 		end
 	end
 
@@ -68,5 +68,12 @@ class MIPS < CPU
 		@opcode_list
 	end
 end
+
+class MIPS64 < MIPS
+	def initialize(endianness = :big, family = :latest)
+		super(endianness, family)
+		@size = 64
+	end
+end
 end
 

data/{lib/metasm → metasm/cpu}/mips/opcodes.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/mips/main'
+require 'metasm/cpu/mips/main'
 
 # TODO coprocessors, floating point, 64bits, thumb mode
 
@@ -13,8 +13,10 @@ module Metasm
 class MIPS
 	def addop(name, bin, *args)
 		o = Opcode.new name, bin
-		o.args.concat(args & @fields_mask.keys)
-		(args & @valid_props).each { |p| o.props[p] = true }
+		args.each { |a|
+			o.args << a if @fields_mask[a]
+			o.props[a] = true if @valid_props[a]
+		}
 		@opcode_list << o
 	end
 
@@ -45,10 +47,11 @@ class MIPS
 		@opcode_list = []
 		@fields_mask.update :rs => 0x1f, :rt => 0x1f, :rd => 0x1f, :sa => 0x1f,
 			:i16 => 0xffff, :i26 => 0x3ffffff, :rs_i16 => 0x3e0ffff, :it => 0x1f,
-			:ft => 0x1f, :idm1 => 0x1f, :idb => 0x1f, :sel => 7, :i20 => 0xfffff #, :i32 => 0
+			:ft => 0x1f, :idm1 => 0x1f, :idb => 0x1f, :sel => 7, :i20 => 0xfffff
 		@fields_shift.update :rs => 21, :rt => 16, :rd => 11, :sa => 6,
 			:i16 => 0, :i26 => 0, :rs_i16 => 0, :it => 16,
-			:ft => 16, :idm1 => 11, :idb => 11, :sel => 0, :i20 => 6 #, :i32 => 0
+			:ft => 16, :idm1 => 11, :idb => 11, :sel => 0, :i20 => 6
+		@valid_props.update :mi8 => true, :mu8 => true, :mi16 => true, :mu16 => true
 
 		init_mips32_obsolete
 		init_mips32_reserved
@@ -58,12 +61,11 @@ class MIPS
 
 		addop 'mov',  0b001000 << 26, :rt, :rs			# rt <- rs+0
 		addop 'addi', 0b001000 << 26, :rt, :rs, :i16		# add		rt <- rs+i
-		addop 'li',   0b001001 << 26, :rt, :i16			# add $0	# XXX liu ?
+		addop 'li',   0b001001 << 26, :rt, :i16			# addiu rt <- zero+i
 		addop 'addiu',0b001001 << 26, :rt, :rs, :i16		# add unsigned
 		addop 'slti', 0b001010 << 26, :rt, :rs, :i16		# set on less than
 		addop 'sltiu',0b001011 << 26, :rt, :rs, :i16		# set on less than unsigned
 		addop 'andi', 0b001100 << 26, :rt, :rs, :i16		# and
-		addop 'li',   0b001101 << 26, :rt, :i16			# or $0
 		addop 'ori',  0b001101 << 26, :rt, :rs, :i16		# or
 		addop 'xori', 0b001110 << 26, :rt, :rs, :i16		# xor
 		addop 'lui',  0b001111 << 26, :rt, :i16			# load upper
@@ -80,16 +82,16 @@ class MIPS
 		addop 'blez', 0b000110 << 26, :rs, :i16, :setip		# <= 0
 		addop 'bgtz', 0b000111 << 26, :rs, :i16, :setip		# > 0
 
-		addop 'lb',   0b100000 << 26, :rt, :rs_i16		# load byte	rs <- [rt+i]
-		addop 'lh',   0b100001 << 26, :rt, :rs_i16		# load halfword
+		addop 'lb',   0b100000 << 26, :rt, :rs_i16, :mi8	# load byte	rs <- [rt+i]
+		addop 'lh',   0b100001 << 26, :rt, :rs_i16, :mi16	# load halfword
 		addop 'lwl',  0b100010 << 26, :rt, :rs_i16		# load word left
 		addop 'lw',   0b100011 << 26, :rt, :rs_i16		# load word
-		addop 'lbu',  0b100100 << 26, :rt, :rs_i16		# load byte unsigned
-		addop 'lhu',  0b100101 << 26, :rt, :rs_i16		# load halfword unsigned
+		addop 'lbu',  0b100100 << 26, :rt, :rs_i16, :mu8	# load byte unsigned
+		addop 'lhu',  0b100101 << 26, :rt, :rs_i16, :mu16	# load halfword unsigned
 		addop 'lwr',  0b100110 << 26, :rt, :rs_i16		# load word right
 
-		addop 'sb',   0b101000 << 26, :rt, :rs_i16		# store byte
-		addop 'sh',   0b101001 << 26, :rt, :rs_i16		# store halfword
+		addop 'sb',   0b101000 << 26, :rt, :rs_i16, :mi8	# store byte
+		addop 'sh',   0b101001 << 26, :rt, :rs_i16, :mi16	# store halfword
 		addop 'swl',  0b101010 << 26, :rt, :rs_i16		# store word left
 		addop 'sw',   0b101011 << 26, :rt, :rs_i16		# store word
 		addop 'swr',  0b101110 << 26, :rt, :rs_i16		# store word right
@@ -179,7 +181,7 @@ class MIPS
 		addop 'teqi', (1<<26) | (0b01100<<16), :rs, :i16, :setip
 		addop 'tnei', (1<<26) | (0b01110<<16), :rs, :i16, :setip
 		addop 'bltzal', (1<<26) | (0b10000<<16), :rs, :i16, :setip, :saveip
-		addop 'bgezal', (1<<26) | (0b10001<<16), :i16, :setip, :stopexec, :saveip	# bgezal $zero => unconditionnal
+		addop 'bgezal', (1<<26) | (0b10001<<16), :i16, :setip, :stopexec, :saveip	# bgezal $zero => unconditional
 		addop 'bgezal', (1<<26) | (0b10001<<16), :rs, :i16, :setip, :saveip
 
 
@@ -195,10 +197,10 @@ class MIPS
 
 
 		# cp0
-		addop 'mfc0', (0b010000<<26) | (0b00000<<21), :rt, :rd
-		addop 'mfc0', (0b010000<<26) | (0b00000<<21), :rt, :rd, :sel
-		addop 'mtc0', (0b010000<<26) | (0b00100<<21), :rt, :rd
-		addop 'mtc0', (0b010000<<26) | (0b00100<<21), :rt, :rd, :sel
+		addop 'mfc0', (0b010000<<26) | (0b00000<<21), :rt, :idb
+		addop 'mfc0', (0b010000<<26) | (0b00000<<21), :rt, :idb, :sel
+		addop 'mtc0', (0b010000<<26) | (0b00100<<21), :rt, :idb
+		addop 'mtc0', (0b010000<<26) | (0b00100<<21), :rt, :idb, :sel
 
 		addop 'tlbr', (0b010000<<26) | (1<<25) | 0b000001
 		addop 'tlbwi',(0b010000<<26) | (1<<25) | 0b000010
@@ -235,6 +237,73 @@ class MIPS
 	end
 	alias init_latest init_mips32r2
 end
+
+class MIPS64
+	def init_mips64
+		init_mips32r2
+		@valid_props.update :mi64 => true
+
+		addop 'ld',     0b110111 << 26, :rt, :rs_i16, :m64
+		addop 'lwu',    0b100111 << 26, :rt, :rs_i16
+		addop 'sd',     0b111111 << 26, :rt, :rs_i16, :m64
+		addop 'scd',    0b111100 << 26, :rt, :rs_i16, :m64
+		addop 'ldl',    0b011010 << 26, :rt, :rs_i16
+		addop 'ldr',    0b011011 << 26, :rt, :rs_i16
+		addop 'sdl',    0b101100 << 26, :rt, :rs_i16
+		addop 'sdr',    0b101101 << 26, :rt, :rs_i16
+		addop 'lld',    0b110100 << 26, :rt, :rs_i16
+		addop 'daddi',  0b011000 << 26, :rt, :rs, :i16
+		addop 'daddiu', 0b011001 << 26, :rt, :rs, :i16
+
+		addop 'dclo',  (0b011100 << 26) | (0b100101), :rd, :rt, :rs
+		addop 'dclz',  (0b011100 << 26) | (0b100100), :rd, :rt, :rs
+
+		addop 'dadd',   0b101100, :rd, :rs, :rt
+		addop 'daddu',  0b101101, :rd, :rs, :rt
+		addop 'dsub',   0b101110, :rd, :rs, :rt
+		addop 'dsubu',  0b101111, :rd, :rs, :rt
+		addop 'dsll',   0b111000, :rd, :rt, :sa
+		addop 'dsll32', 0b111100, :rd, :rt, :sa
+		addop 'dsllv',  0b010100, :rd, :rt, :rs
+		addop 'dsra',   0b111011, :rd, :rt, :sa
+		addop 'dsra32', 0b111111, :rd, :rt, :sa
+		addop 'dsrav',  0b010111, :rd, :rt, :rs
+		addop 'dsrl',   0b111010, :rd, :rt, :sa
+		addop 'dsrl32', 0b111110, :rd, :rt, :sa
+		addop 'dsrlv',  0b010110, :rd, :rt, :rs
+		addop 'ddiv',   0b011110, :rs, :rt
+		addop 'ddivu',  0b011111, :rs, :rt
+		addop 'dmult',  0b011100, :rs, :rt
+		addop 'dmultu', 0b011101, :rs, :rt
+
+		addop 'dmfc0', (0b010000<<26) | (0b00001<<21), :rt, :idb
+		addop 'dmfc0', (0b010000<<26) | (0b00001<<21), :rt, :idb, :sel
+		addop 'dmtc0', (0b010000<<26) | (0b00101<<21), :rt, :idb
+		addop 'dmtc0', (0b010000<<26) | (0b00101<<21), :rt, :idb, :sel
+	end
+
+	def init_mips64r2
+		init_mips64
+		@fields_mask.update :msbd => 0x1f
+		@fields_shift.update :msbd => 11
+
+		addop 'dext',  (0b011111 << 26) | 0b000011, :rt, :rs, :sa, :msbd	# sa => lsb
+		addop 'dextm', (0b011111 << 26) | 0b000001, :rt, :rs, :sa, :msbd
+		addop 'dextu', (0b011111 << 26) | 0b000010, :rt, :rs, :sa, :msbd
+		addop 'dins',  (0b011111 << 26) | 0b000111, :rt, :rs, :sa, :msbd
+		addop 'dinsm', (0b011111 << 26) | 0b000101, :rt, :rs, :sa, :msbd
+		addop 'dinsu', (0b011111 << 26) | 0b000110, :rt, :rs, :sa, :msbd
+
+		addop 'drotr',   (1 << 21) | 0b111010, :rd, :rt, :sa
+		addop 'drotr32', (1 << 21) | 0b111110, :rd, :rt, :sa
+		addop 'drotrv',  (1 <<  6) | 0b010110, :rd, :rt, :rs
+
+		addop 'dsbh', (0b011111 << 26) | (0b00010 << 6) | 0b100100, :rd, :rt
+		addop 'dshd', (0b011111 << 26) | (0b00101 << 6) | 0b100100, :rd, :rt
+	end
+
+	alias init_latest init_mips64r2
+end
 end
 __END__
 	def macro_addop_cop1(name, bin, *aprops)