metasm 1.0.0 → 1.0.5

data/{lib/metasm → metasm/cpu}/sh4.rb

@@ -5,4 +5,4 @@
 
 
 require 'metasm/main'
-require 'metasm/sh4/decode'
+require 'metasm/cpu/sh4/decode'

data/{lib/metasm → metasm/cpu}/sh4/decode.rb

@@ -3,7 +3,7 @@
 #
 #    Licence is LGPL, see LICENCE in the top-level directory
 
-require 'metasm/sh4/opcodes'
+require 'metasm/cpu/sh4/opcodes'
 require 'metasm/decode'
 
 module Metasm
@@ -39,7 +39,7 @@ class Sh4
 	end
 
 	def decode_findopcode(edata)
-		return if edata.ptr >= edata.data.length
+		return if edata.ptr >= edata.length
 
 		di = DecodedInstruction.new(self)
 		val = edata.decode_imm(:u16, @endianness)
@@ -110,7 +110,6 @@ class Sh4
 			when :pr; PR.new
 			when :fpul; FPUL.new
 			when :fpscr; FPSCR.new
-			when :dbr; DBR.new
 			when :pc; PC.new
 
 			when :@rm, :@rn, :@disppc
@@ -137,25 +136,49 @@ class Sh4
 		}
 
 		di.bin_length += edata.ptr - before_ptr
+
+		return if edata.ptr > edata.length
+
 		di
 	end
 
 	def disassembler_default_func
 		df = DecodedFunction.new
 		df.backtrace_binding = {}
-		15.times { |i| df.backtrace_binding["r#{i}".to_sym] = Expression::Unknown }
+		(0..7 ).each { |i| r = "r#{i}".to_sym ; df.backtrace_binding[r] = Expression::Unknown }
+		(8..15).each { |i| r = "r#{i}".to_sym ; df.backtrace_binding[r] = Expression[r] }
 		df.backtracked_for = [BacktraceTrace.new(Expression[:pr], :default, Expression[:pr], :x)]
 		df.btfor_callback = lambda { |dasm, btfor, funcaddr, calladdr|
 			if funcaddr != :default
 				btfor
 			elsif di = dasm.decoded[calladdr] and di.opcode.props[:saveip]
 				btfor
-			else []
+			else
+				[]
 			end
 		}
 		df
 	end
 
+	def backtrace_update_function_binding(dasm, faddr, f, retaddrlist, *wantregs)
+		retaddrlist.map! { |retaddr| dasm.decoded[retaddr] ? dasm.decoded[retaddr].block.list.last.address : retaddr } if retaddrlist
+		b = f.backtrace_binding
+
+		bt_val = lambda { |r|
+			next if not retaddrlist
+			bt = []
+			b[r] = Expression::Unknown	# break recursive dep
+			retaddrlist.each { |retaddr|
+				bt |= dasm.backtrace(Expression[r], retaddr,
+					:include_start => true, :snapshot_addr => faddr, :origin => retaddr)
+			}
+			b[r] = ((bt.length == 1) ? bt.first : Expression::Unknown)
+		}
+		wantregs = GPR::Sym if wantregs.empty?
+		wantregs.map { |r| r.to_sym }.each(&bt_val)
+	end
+
+
 	# interprets a condition code (in an opcode name) as an expression
 	def decode_cmp_expr(di, a0, a1)
 		case di.opcode.name
@@ -174,10 +197,6 @@ class Sh4
 		end
 	end
 
-	def backtrace_binding
-		@backtrace_binding ||= init_backtrace_binding
-	end
-
 	def opsz(di)
 		ret = @size
 		ret = 8 if di and di.opcode.name =~ /\.b/
@@ -197,6 +216,7 @@ class Sh4
 			when 'stc.w', 'stc.b', 'mov.w', 'mov.b'
 				lambda { |di, a0, a1| { a1 => Expression[a0, :&, mask[di]] }}
 			when 'movt'; lambda { |di, a0| { a0 => :t_bit }}
+			when 'mova'; lambda { |di, a0, a1| { a1 => Expression[a0] }}
 			when 'exts.b', 'exts.w', 'extu.w'
 				lambda { |di, a0, a1| { a1 => Expression[a0, :&, mask[di]] }}
 			when 'cmp/eq', 'cmp/ge', 'cmp/ge', 'cmp/gt', 'cmp/hi', 'cmp/hs'
@@ -212,12 +232,12 @@ class Sh4
 			when 'clrt'; lambda { |di| { :t_bit => 0 }}
 			when 'clrmac'; lambda { |di| { :macl => 0, :mach => 0 }}
 			when 'jmp'; lambda { |di, a0| { :pc => a0 }}
-			when 'jsr'; lambda { |di, a0| { :pc => Expression[a0], :pr => Expression[di.address+2*2] }}
+			when 'jsr', 'bsr', 'bsrf'; lambda { |di, a0| { :pc => Expression[a0], :pr => Expression[di.address, :+, 2*2] }}
 			when 'dt'; lambda { |di, a0|
 				res = Expression[a0, :-, 1]
 				{ :a0 => res, :t_bit => Expression[res, :==, 0] }
 			}
-			when 'add' ; lambda { |di, a0, a1| { a1 => Expression[a0, :+, a1] }}
+			when 'add' ; lambda { |di, a0, a1| { a1 => Expression[[a0, :+, a1], :&, 0xffff_ffff] }}
 			when 'addc' ; lambda { |di, a0, a1|
 				res = Expression[[a0, :&, mask[di]], :+, [[a1, :&, mask[di]], :+, :t_bit]]
 				{ a1 => Expression[a0, :+, [a1, :+, :t_bit]], :t_bit => Expression[res, :>, mask[di]] }
@@ -252,17 +272,16 @@ class Sh4
 				shift_bit = Expression[a0, :&, 1]
 				{ a0 => Expression[a0, :>>, 1], :t_bit => shift_bit }
 			}
-			when 'sub';  lambda { |di, a0, a1| { a1 => Expression[a0, :-, a1] }}
-			when 'subc'; lambda { |di, a0, a1| { a1 => Expression[a0, :-, [a1, :-, :t_bit]] }}
+			when 'sub';  lambda { |di, a0, a1| { a1 => Expression[[a1, :-, a0], :&, 0xffff_ffff] }}
+			when 'subc'; lambda { |di, a0, a1| { a1 => Expression[a1, :-, [a0, :-, :t_bit]] }}
 			when 'and', 'and.b'; lambda { |di, a0, a1| { a1 => Expression[[a0, :&, mask[di]], :|, [[a1, :&, mask[di]]]] }}
 			when 'or', 'or.b';   lambda { |di, a0, a1| { a1 => Expression[[a0, :|, mask[di]], :|, [[a1, :&, mask[di]]]] }}
 			when 'xor', 'xor.b'; lambda { |di, a0, a1| { a1 => Expression[[a0, :|, mask[di]], :^, [[a1, :&, mask[di]]]] }}
-			when 'add', 'addc', 'addv'; lambda { |di, a0, a1| { a1 => Expression[a0, :+, a1] }}
 			when 'neg' ;  lambda { |di, a0, a1| { a1 => Expression[mask[di], :-, a0] }}
 			when 'negc' ; lambda { |di, a0, a1| { a1 => Expression[[[mask[di], :-, a0], :-, :t_bit], :&, mask[di]] }}
 			when 'not';   lambda { |di, a0, a1| { a1 => Expression[a0, :^, mask[di]] }}
-			when 'nop'; lambda { {} }
-			when /^b/; lambda { {} }	# branches
+			when 'nop'; lambda { |*a| {} }
+			when /^b/; lambda { |*a| {} }	# branches
 			end
 		}
 
@@ -275,7 +294,7 @@ class Sh4
 			when GPR, XFR, XDR, FVR, DR, FR, XMTRX; arg.symbolic
 			when MACH, MACL, PR, FPUL, PC, FPSCR; arg.symbolic
 			when SR, SSR, SPC, GBR, VBR, SGR, DBR; arg.symbolic
-			when Memref; arg.symbolic(di.address, di.opcode.props[:memsz]/8)
+			when Memref; arg.symbolic(di)
 			else arg
 			end
 		}
@@ -283,12 +302,15 @@ class Sh4
 		if binding = backtrace_binding[di.opcode.basename]
 			bd = binding[di, *a] || {}
 			di.instruction.args.grep(Memref).each { |m|
-				if m.post
-					# TODO preincrement/postdecrement
-					bd.each { |k, v| bd[k] = v.bind(r => Expression[r, :+, 1]) }
-					bd[r] ||= Expression[r, :+, 1]
+				next unless r = m.base and r.kind_of?(GPR)
+				r = r.symbolic
+				case m.action
+				when :post
+					bd[r] ||= Expression[r, :+, di.opcode.props[:memsz]/8]
+				when :pre
+					bd[r] ||= Expression[r, :-, di.opcode.props[:memsz]/8]
 				end
-			} if false
+			}
 			bd
 		else
 			puts "unhandled instruction to backtrace: #{di}" if $VERBOSE
@@ -306,7 +328,12 @@ class Sh4
 
 		val = case val
 		      when Reg; val.symbolic
-		      when Memref; arg.symbolic(di.address, 4)
+		      when Memref; arg.symbolic(di)
+		      else val
+		      end
+
+		val = case di.instruction.opname
+		      when 'braf', 'bsrf'; Expression[[di.address, :+, 4], :+, val]
 		      else val
 		      end
 

data/{lib/metasm → metasm/cpu}/sh4/main.rb

@@ -48,7 +48,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "r#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["r#@i"] end
 	end
@@ -59,7 +59,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "r#{i}_bank".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["r#{@i}_bank"] end
 	end
@@ -71,7 +71,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "fr#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["fr#@i"] end
 	end
@@ -91,7 +91,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "dr#{i*2}".to_sym }
 
-		def symbolic ; Sym[@i/2] end
+		def symbolic(di=nil) ; Sym[@i/2] end
 
 		def render ; ["dr#@i"] end
 	end
@@ -107,7 +107,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..3).map { |i| "fv#{i*4}".to_sym }
 
-		def symbolic ; Sym[@i/4] end
+		def symbolic(di=nil) ; Sym[@i/4] end
 
 		def render ; ["fv#@i"] end
 	end
@@ -119,7 +119,7 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..15).map { |i| "xf#{i}".to_sym }
 
-		def symbolic ; Sym[@i] end
+		def symbolic(di=nil) ; Sym[@i] end
 
 		def render ; ["xf#@i"] end
 	end
@@ -139,14 +139,14 @@ class Sh4 < CPU
 		def initialize(i); @i = i end
 		Sym = (0..7).map { |i| "xd#{i*2}".to_sym }
 
-		def symbolic ; Sym[@i/2] end
+		def symbolic(di=nil) ; Sym[@i/2] end
 
 		def render ; ["xd#@i"] end
 	end
 
 	# Single-precision floating-point extended register matrix
 	class XMTRX < Reg
-		def symbolic ; :xmtrx ; end
+		def symbolic(di=nil) ; :xmtrx ; end
 		def render ; ['xmtrx'] ; end
 	end
 
@@ -154,42 +154,42 @@ class Sh4 < CPU
 	# Multiply-and-accumulate register high
 	class MACH < Reg
 
-		def symbolic ; :mach end
+		def symbolic(di=nil) ; :mach end
 		def render ; ['mach'] end
 	end
 
 	# Multiply-and-accumulate register low
 	class MACL < Reg
 
-		def symbolic ; :macl end
+		def symbolic(di=nil) ; :macl end
 		def render ; ['macl'] end
 	end
 
 	# Procedure register
 	class PR < Reg
 
-		def symbolic ; :pr end
+		def symbolic(di=nil) ; :pr end
 		def render ; ['pr'] end
 	end
 
 	# Floating-point communication register
 	class FPUL < Reg
 
-		def symbolic ; :fpul end
+		def symbolic(di=nil) ; :fpul end
 		def render ; ['fpul'] end
 	end
 
 	# Program counter
 	class PC < Reg
 
-		def symbolic ; :pc end
+		def symbolic(di=nil) ; :pc end
 		def render ; ['pc'] end
 	end
 
 	# Floating-point status/control register
 	class FPSCR < Reg
 
-		def symbolic ; :fpscr end
+		def symbolic(di=nil) ; :fpscr end
 		def render ; ['fpscr'] end
 	end
 
@@ -198,49 +198,49 @@ class Sh4 < CPU
 	# Status register
 	class SR < Reg
 
-		def symbolic ; :sr end
+		def symbolic(di=nil) ; :sr end
 		def render ; ['sr'] end
 	end
 
 	# Saved status register
 	class SSR < Reg
 
-		def symbolic ; :ssr end
+		def symbolic(di=nil) ; :ssr end
 		def render ; ['ssr'] end
 	end
 
 	# Saved program counter
 	class SPC < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['spc'] end
 	end
 
 	# Global base register
 	class GBR < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['gbr'] end
 	end
 
 	# Vector base register
 	class VBR < Reg
 
-		def symbolic ; :spc end
+		def symbolic(di=nil) ; :spc end
 		def render ; ['vbr'] end
 	end
 
 	# Saved general register
 	class SGR < Reg
 
-		def symbolic ; :sgr end
+		def symbolic(di=nil) ; :sgr end
 		def render ; ['sgr'] end
 	end
 
 	# Debug base register
 	class DBR < Reg
 
-		def symbolic ; :dbr end
+		def symbolic(di=nil) ; :dbr end
 		def render ; ['dbr'] end
 	end
 
@@ -253,10 +253,14 @@ class Sh4 < CPU
 			@base, @disp, @action = base, offset, action
 		end
 
-		def symbolic(orig=nil, sz=32)
+		def symbolic(di=nil)
+			sz = 32
+			sz = di.opcode.props[:memsz] if di
 			b = @base
 			b = b.symbolic if b.kind_of? Reg
 
+			b = Expression[b, :-, sz/8] if @action == :pre
+
 			if disp
 				o = @disp
 				o = o.symbolic if o.kind_of? Reg
@@ -265,19 +269,23 @@ class Sh4 < CPU
 				e = Expression[b].reduce
 			end
 
-			Indirection[e, sz, orig]
+			Indirection[e, sz, (di.address if di)]
 		end
 
 		include Renderable
 
 		def render
 			if @disp
-				['@(', @base, ',', @disp, ')']
+				#['@(', @base, ',', @disp, ')']
+				['[', @base, '+', @disp, ']']
 			else
 				case @action
-				when :pre then ['@-', @base]
-				when :post then ['@', @base, '+']
-				else ['@', @base]
+				when :pre then ['[--', @base, ']']
+				when :post then ['[', @base, '++]']
+				else ['[', @base, ']']
+				#when :pre then ['@-', @base]
+				#when :post then ['@', @base, '+']
+				#else ['@', @base]
 				end
 			end
 		end
@@ -288,5 +296,8 @@ class Sh4 < CPU
 		init
 	end
 
+	def dbg_register_list
+		@dbg_register_list ||= GPR::Sym
+	end
 end
 end

data/{lib/metasm → metasm/cpu}/sh4/opcodes.rb

@@ -3,18 +3,17 @@
 #
 #    Licence is LGPL, see LICENCE in the top-level directory
 
-require 'metasm/sh4/main'
+require 'metasm/cpu/sh4/main'
 
 module Metasm
 class Sh4
 	def addop(name, bin, *args)
 		o = Opcode.new name, bin
 
-		o.args.concat(args & @fields_mask.keys)
-		(args & @valid_props).each { |p| o.props[p] = true }
-
-		(args & @fields_mask.keys).each { |f|
-			o.fields[f] = [@fields_mask[f], @fields_shift[f]]
+		args.each { |a|
+			o.args << a if @fields_mask[a]
+			o.props[a] = true if @valid_props[a]
+			o.fields[a] = [@fields_mask[a], @fields_shift[a]] if @fields_mask[a]
 		}
 
 		@opcode_list << o
@@ -74,7 +73,7 @@ class Sh4
 		# implicit operands
 		[:vbr, :gbr, :sr, :ssr, :spc, :sgr, :dbr, :mach, :macl, :pr, :fpul, :fpscr, :dbr, :pc, :r0].each { |a| @fields_mask[a] = @fields_shift[a] = 0 }
 
-		@valid_props = [:setip, :saveip, :stopexec , :delay_slot]
+		@valid_props[:delay_slot] = true
 
 		addop 'add', 0b0011 << 12 | 0b1100, :rm, :rn
 		addop 'add', 0b0111 << 12, :s8, :rn
@@ -275,7 +274,7 @@ class Sh4
 		addop 'mov.w', 0b10000101 << 8, :@disprm, :r0
 
 		addop 'mova', 0b11000111 << 8, :disppc, :r0 # calculates an effective address using PC-relative with displacement addressing
-		addop 'movca.l', 0b0000 << 12 | 11000011, :r0, :@rn # stores the long-word in R0 to memory at the effective address specified in Rn.     
+		addop 'movca.l', 0b0000 << 12 | 11000011, :r0, :@rn # stores the long-word in R0 to memory at the effective address specified in Rn.
 
 		addop 'movt', 0b0000 << 12 | 0b00101001, :rn # copies the T-bit to Rn
 

data/metasm/cpu/st20.rb

@@ -0,0 +1,9 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2006-2009 Yoann GUILLOT
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/main'
+require 'metasm/cpu/st20/decode'
+require 'metasm/cpu/st20/decompile'