metasm 1.0.0 → 1.0.5

data/{lib/metasm → metasm/cpu}/ia32/parse.rb

@@ -4,8 +4,8 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/ia32/opcodes'
-require 'metasm/ia32/encode'
+require 'metasm/cpu/ia32/opcodes'
+require 'metasm/cpu/ia32/encode'
 require 'metasm/parse'
 
 module Metasm
@@ -99,14 +99,18 @@ class ModRM
 				else
 					b = o
 				end
+			when SimdReg
+				raise otok, 'mrm: too many regs' if i
+				i = o
+				s = 1
 			when Expression
-				if o.op == :* and (o.rexpr.kind_of? Reg or o.lexpr.kind_of? Reg)
+				if o.op == :* and (o.rexpr.kind_of?(Reg) or o.lexpr.kind_of?(Reg))
 					# scaled index
 					raise otok, 'mrm: too many indexes' if i
 					s = o.lexpr
 					i = o.rexpr
 					s, i = i, s if s.kind_of? Reg
-					raise otok, 'mrm: bad scale' unless s.kind_of? Integer
+					raise otok, "mrm: bad scale #{s}" unless [1, 2, 4, 8].include?(s)
 				elsif o.op == :+
 					# recurse
 					walker[o.lexpr]
@@ -125,7 +129,11 @@ class ModRM
 		walker[regify[content.reduce]]
 
 		# ensure found immediate is really an immediate
-		raise otok, 'mrm: reg in imm' if imm.kind_of? Expression and not imm.externals.grep(Reg).empty?
+		raise otok, 'mrm: reg in imm' if imm.kind_of?(Expression) and not imm.externals.grep(Reg).empty?
+
+		raise otok, 'mrm: bad reg size' if b.kind_of?(Reg) and i.kind_of?(Reg) and b.sz != i.sz
+
+		raise otok, 'mrm: cannot encode [rip+reg], only [rip+imm]' if (b and b.val == 16 and i) or (i and i.val == 16 and (b or s != 1))
 
 		# find default address size
 		adsz = b ? b.sz : i ? i.sz : nil
@@ -153,7 +161,6 @@ end
 	end
 
 	def parse_prefix(i, pfx)
-		# XXX check for redefinition ?
 		# implicit 'true' return value when assignment occur
 		i.prefix ||= {}
 		case pfx
@@ -163,11 +170,14 @@ end
 		when 'repne', 'repnz'; i.prefix[:rep] = 'repnz'
 		when 'code16';         i.prefix[:sz] = 16
 		when 'code32';         i.prefix[:sz] = 32
+		when 'hintjmp', 'ht';  i.prefix[:jmphint] = 'hintjmp'
+		when 'hintnojmp', 'hnt';i.prefix[:jmphint] = 'hintnojmp'
+		when /^seg_([c-g]s)$/; i.prefix[:seg] = SegReg.new(SegReg.s_to_i[$1])
 		end
 	end
 
 	def parse_argregclasslist
-		[Reg, SimdReg, SegReg, DbgReg, CtrlReg, FpReg]
+		[Reg, SimdReg, SegReg, DbgReg, TstReg, CtrlReg, FpReg]
 	end
 	def parse_modrm(lex, tok, cpu)
 		ModRM.parse(lex, tok, cpu)
@@ -230,17 +240,30 @@ end
 	# check if the argument matches the opcode's argument spec
 	def parse_arg_valid?(o, spec, arg)
 		if o.name ==  'movsx' or o.name == 'movzx'
-			if not arg.kind_of? Reg and not arg.kind_of? ModRM
- 				return
+			if not arg.kind_of?(Reg) and not arg.kind_of?(ModRM)
+				return
 			elsif not arg.sz
 				puts "ambiguous arg size for indirection in #{o.name}" if $VERBOSE
 				return
 			elsif spec == :reg	# reg=dst, modrm=src (smaller)
-				return (arg.kind_of? Reg and arg.sz >= 16)
+				return (arg.kind_of?(Reg) and arg.sz >= 16)
 			elsif o.props[:argsz]
 				return arg.sz == o.props[:argsz]
 			else
-				return arg.sz <= 16
+				return arg.sz == 16
+			end
+		elsif o.name == 'crc32'
+			if not arg.kind_of?(Reg) and not arg.kind_of?(ModRM)
+				return
+			elsif not arg.sz
+				puts "ambiguous arg size for indirection in #{o.name}" if $VERBOSE
+				return
+			elsif spec == :reg
+				return (arg.kind_of?(Reg) and arg.sz >= 32)
+			elsif o.props[:argsz]
+				return arg.sz == o.props[:argsz]
+			else
+				return arg.sz >= 16
 			end
 		end
 
@@ -254,7 +277,7 @@ end
 		cond and
 		case spec
 		when :reg; arg.kind_of? Reg and (arg.sz >= 16 or o.props[:argsz])
-		when :modrm; (arg.kind_of? ModRM or arg.kind_of? Reg) and (!arg.sz or arg.sz >= 16 or o.props[:argsz])
+		when :modrm; (arg.kind_of? ModRM or arg.kind_of? Reg) and (!arg.sz or arg.sz >= 16 or o.props[:argsz]) and (!o.props[:modrmA] or arg.kind_of? ModRM) and (!o.props[:modrmR] or arg.kind_of? Reg)
 		when :i;        arg.kind_of? Expression
 		when :imm_val1; arg.kind_of? Expression and arg.reduce == 1
 		when :imm_val3; arg.kind_of? Expression and arg.reduce == 3
@@ -267,15 +290,22 @@ end
 		when :seg2A;    arg.kind_of? SegReg  and arg.val < 4 and arg.val != 1
 		when :eeec;     arg.kind_of? CtrlReg
 		when :eeed;     arg.kind_of? DbgReg
-		when :modrmA;   arg.kind_of? ModRM
+		when :eeet;     arg.kind_of? TstReg
 		when :mrm_imm;  arg.kind_of? ModRM   and not arg.s and not arg.i and not arg.b
 		when :farptr;   arg.kind_of? Farptr
 		when :regfp;    arg.kind_of? FpReg
 		when :regfp0;   arg.kind_of? FpReg   and (arg.val == nil or arg.val == 0)
-		when :modrmmmx; arg.kind_of? ModRM   or (arg.kind_of? SimdReg and (arg.sz == 64 or (arg.sz == 128 and o.props[:xmmx])))
+		when :modrmmmx; arg.kind_of? ModRM   or (arg.kind_of? SimdReg and (arg.sz == 64 or (arg.sz == 128 and o.props[:xmmx]))) and (!o.props[:modrmA] or arg.kind_of? ModRM) and (!o.props[:modrmR] or arg.kind_of? SimdReg)
 		when :regmmx;   arg.kind_of? SimdReg and (arg.sz == 64 or (arg.sz == 128 and o.props[:xmmx]))
-		when :modrmxmm; arg.kind_of? ModRM   or (arg.kind_of? SimdReg and arg.sz == 128)
+		when :modrmxmm; arg.kind_of? ModRM   or (arg.kind_of? SimdReg and arg.sz == 128) and (!o.props[:modrmA] or arg.kind_of? ModRM) and (!o.props[:modrmR] or arg.kind_of? SimdReg)
 		when :regxmm;   arg.kind_of? SimdReg and arg.sz == 128
+		when :modrmymm; arg.kind_of? ModRM   or (arg.kind_of? SimdReg and arg.sz == 256) and (!o.props[:modrmA] or arg.kind_of? ModRM) and (!o.props[:modrmR] or arg.kind_of? SimdReg)
+		when :regymm;   arg.kind_of? SimdReg and arg.sz == 256
+
+		when :vexvreg;  arg.kind_of? Reg and arg.sz == @size
+		when :vexvxmm, :i4xmm;  arg.kind_of? SimdReg and arg.sz == 128
+		when :vexvymm, :i4ymm;  arg.kind_of? SimdReg and arg.sz == 256
+
 		when :i8, :u8, :u16
 			arg.kind_of? Expression and
 			(o.props[:setip] or Expression.in_range?(arg, spec) != false)	# true or nil allowed
@@ -302,8 +332,8 @@ end
 			else
 				if r = i.args.grep(Reg).first
 					m.sz = r.sz
-				elsif opcode_list_byname[i.opname].all? { |o| o.props[:argsz] }
-					m.sz = opcode_list_byname[i.opname].first.props[:argsz]
+				elsif l = opcode_list_byname[i.opname].map { |o| o.props[:argsz] }.uniq and l.length == 1 and l.first
+					m.sz = l.first
 				else
 					# this is also the size of ctrlreg/dbgreg etc
 					# XXX fpu/simd ?
@@ -320,8 +350,16 @@ end
 		end
 	end
 
+	def check_reserved_name(name)
+		Reg.s_to_i[name]
+	end
+
 	def instr_uncond_jump_to(target)
 		parse_instruction("jmp #{target}")
 	end
+
+	def instr_jump_stop
+		parse_instruction("hlt")
+	end
 end
 end

data/{lib/metasm → metasm/cpu}/ia32/render.rb

@@ -4,7 +4,7 @@
 #    Licence is LGPL, see LICENCE in the top-level directory
 
 
-require 'metasm/ia32/opcodes'
+require 'metasm/cpu/ia32/opcodes'
 require 'metasm/render'
 
 # XXX move context in another file ?
@@ -14,7 +14,7 @@ class Ia32
 		include Renderable
 	end
 
-	[SegReg, DbgReg, CtrlReg, FpReg].each { |c| c.class_eval {
+	[SegReg, DbgReg, TstReg, CtrlReg, FpReg].each { |c| c.class_eval {
 		def render ; [self.class.i_to_s[@val]] end
 	} }
 	[Reg, SimdReg].each { |c| c.class_eval {
@@ -60,12 +60,18 @@ class Ia32
 
 	def render_instruction(i)
 		r = []
-		r << 'lock ' if i.prefix and i.prefix[:lock]
-		r << i.prefix[:rep] << ' ' if i.prefix and i.prefix[:rep]
+		if pfx = i.prefix
+			r << 'lock ' if pfx[:lock]
+			r << pfx[:rep] << ' ' if pfx[:rep]
+			r << pfx[:jmphint] << ' ' if pfx[:jmphint]
+			r << 'seg_' << pfx[:seg] << ' ' if pfx[:seg]
+		end
 		r << i.opname
+		sep = ' '
 		i.args.each { |a|
 			a.instruction = i if a.kind_of? ModRM
-			r << (r.last == i.opname ? ' ' : ', ') << a
+			r << sep << a
+			sep = ', '
 		}
 		r
 	end
@@ -87,5 +93,26 @@ class Ia32
 		h['toggle lock'] = lambda { (i.prefix ||= {})[:lock] = !i.prefix[:lock] }
 		h
 	end
+
+	def gui_hilight_word_regexp_init
+		ret = {}
+
+		%w[a b c d].each { |r|
+			ret["#{r}l"] = "e?#{r}x|#{r}l"
+			ret["#{r}h"] = "e?#{r}x|#{r}h"
+			ret["#{r}x"] = ret["e#{r}x"] = "e?#{r}x|#{r}[hl]"
+		}
+
+		%w[sp bp si di].each { |r|
+			ret[r] = ret["e#{r}"] = "e?#{r}"
+		}
+
+		ret
+	end
+
+	def gui_hilight_word_regexp(word)
+		@gui_hilight_word_hash ||= gui_hilight_word_regexp_init
+		@gui_hilight_word_hash[word] or super(word)
+	end
 end
 end

data/metasm/cpu/mcs51.rb

@@ -0,0 +1,8 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2015 Google
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/main'
+require 'metasm/cpu/mcs51/decode'

data/metasm/cpu/mcs51/decode.rb

@@ -0,0 +1,99 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2015-2016 Google
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/cpu/mcs51/opcodes'
+require 'metasm/decode'
+
+module Metasm
+class MCS51
+
+	def build_opcode_bin_mask(op)
+		op.bin_mask = 0
+		op.fields.each { |f, off|
+			op.bin_mask |= (@fields_mask[f] << off)
+		}
+		op.bin_mask ^= 0xff
+	end
+
+	def build_bin_lookaside
+		lookaside = Array.new(256) { [] }
+		opcode_list.each { |op|
+			build_opcode_bin_mask op
+			b   = op.bin
+			msk = op.bin_mask
+			for i in b..(b | (255^msk))
+				lookaside[i] << op if i & msk == b & msk
+			end
+		}
+		lookaside
+	end
+
+	def decode_findopcode(edata)
+		di = DecodedInstruction.new self
+		byte = edata.data[edata.ptr]
+		byte = byte.unpack('C').first if byte.kind_of?(::String)
+		if not byte
+			return
+		end
+		return di if di.opcode = @bin_lookaside[byte].find { |op|
+			byte & op.bin_mask == op.bin & op.bin_mask
+		}
+	end
+
+	def decode_instr_op(edata, di)
+		before_ptr = edata.ptr
+		op = di.opcode
+		di.instruction.opname = op.name
+		bseq = edata.get_byte
+
+		field_val = lambda { |f|
+			if fld = op.fields[f]
+				(bseq >> fld) & @fields_mask[f]
+			end
+		}
+
+		op.args.each { |a|
+			di.instruction.args << case a
+			when :rel8
+				Expression[edata.decode_imm(:i8, @endianness)]
+			when :d8
+				Immediate.new(edata.decode_imm(:u8, @endianness))
+			when :m8
+				Memref.new(nil, edata.decode_imm(:u8, @endianness))
+			when :rd
+				if (field_val[a] & 0b1110) == 0b0110
+					Memref.new(Reg.new(field_val[a] + 2), nil)
+				else
+					Reg.new(field_val[a])
+				end
+			when :r_a
+				Reg.from_str('A')
+			when :r_b
+				Reg.from_str('B')
+			when :r_c
+				Reg.from_str('C')
+			when :addr_11
+				Memref.new(nil, edata.decode_imm(:u8, @endianness))
+			when :addr_16
+				Memref.new(nil, edata.decode_imm(:u16, @endianness))
+			end
+		}
+
+		di.bin_length += edata.ptr - before_ptr
+
+		di
+	end
+
+	def init_backtrace_binding
+		@backtrace_binding ||= {}
+	end
+
+	def get_xrefs_x(b,c)
+		[]
+	end
+
+end
+end

data/metasm/cpu/mcs51/main.rb

@@ -0,0 +1,87 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2015-2016 Google
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+
+require 'metasm/main'
+
+module Metasm
+class MCS51 < CPU
+
+	class Reg
+		I_TO_S  = { 0x4 => 'A',
+		            0x5 => 'B',
+		            0x8 => 'R0',
+		            0x9 => 'R1',
+		            0xA => 'R2',
+		            0xB => 'R3',
+		            0xC => 'R4',
+		            0xD => 'R5',
+		            0xE => 'R6',
+		            0xF => 'R7'
+		}
+
+		S_TO_I = { 'A' => 0x4,
+		           'B' => 0x5 }
+
+		def initialize(i)
+			@i = i
+		end
+
+		def to_s
+			I_TO_S[@i]
+		end
+
+		def self.from_str(s)
+			new(S_TO_I[s])
+		end
+
+		def symbolic(di=nil)
+			to_s.to_sym
+		end
+	end
+
+	class Immediate
+		def initialize(value)
+			@value = value
+		end
+
+		def to_s
+			"#" + @value.to_s
+		end
+
+		def symbolic(di=nil)
+			Expression[@value]
+		end
+	end
+
+	class Memref
+		attr_accessor :base, :offset
+		def initialize(base, offset)
+			@base = base
+			@offset = offset
+		end
+
+		def to_s
+			@base ? "@" + @base.to_s : @offset.to_s
+		end
+
+		def symbolic(di=nil)
+			Indirection[(@base || @offset), 1, (di.address if di)]
+		end
+	end
+
+	def initialize
+		super()
+		@endianness = :big
+		@size = 8
+	end
+
+	def init_opcode_list
+		init_mcs51
+		@opcode_list
+	end
+end
+end
+

data/metasm/cpu/mcs51/opcodes.rb

@@ -0,0 +1,120 @@
+#    This file is part of Metasm, the Ruby assembly manipulation suite
+#    Copyright (C) 2015-2016 Google
+#
+#    Licence is LGPL, see LICENCE in the top-level directory
+
+require 'metasm/cpu/mcs51/main'
+
+module Metasm
+
+class MCS51
+	def addop(name, bin, *args)
+		o = Opcode.new name, bin
+		args.each { |a|
+			o.args << a if @fields_mask[a] or @valid_args[a]
+			o.fields[a] = @fields_shift[a] if @fields_mask[a]
+			raise "unknown #{a.inspect}" unless @valid_args[a] or @fields_mask[a]
+		}
+		@opcode_list << o
+	end
+
+	def init_mcs51
+		@opcode_list = []
+		@valid_args.update [:rd, :r_a, :r_b, :r_c, :d8, :rel8, :m8,
+		                    :addr_11, :addr_16].inject({}) { |h, v| h.update v => true }
+		@fields_mask.update :rd => 15, :addr_11 => 7
+		@fields_shift.update :rd => 0, :addr_11 => 5
+
+		addop 'nop',   0x00
+		addop 'ret',   0x22
+		addop 'reti',  0x32
+		addop 'swap',  0xc4, :r_a
+		addop '???',   0xa5
+		addop 'rr',    0x03, :r_a
+		addop 'rrc',   0x13, :r_a
+		addop 'rl',    0x23, :r_a
+		addop 'rlc',   0x33, :r_a
+
+		addop 'jc',    0x40, :rel8
+		addop 'jnc',   0x50, :rel8
+		addop 'jz',    0x60, :rel8
+		addop 'jnz',   0x70, :rel8
+		addop 'sjmp',  0x80, :rel8
+
+		addop 'div',   0x84, :r_a, :r_b
+		addop 'mul',   0xa4, :r_a, :r_b
+
+		addop 'push',  0xc0, :m8
+		addop 'pop',   0xd0, :m8
+
+		addop 'clr',   0xc3, :r_c
+		addop 'clr',   0xe4, :r_a
+		addop 'cpl',   0xb3, :r_c
+		addop 'cpl',   0xf4, :r_a
+		addop 'da',    0xd4
+
+		addop 'ajmp',  0x01, :addr_11
+		addop 'acall', 0x11, :addr_11
+		addop 'ljmp',  0x02, :addr_16
+		addop 'lcall', 0x12, :addr_16
+
+		addop 'inc',   0x04, :r_a
+		addop 'inc',   0x05, :m8
+		addop 'inc',   0x00, :rd
+
+		addop 'dec',   0x14, :r_a
+		addop 'dec',   0x15, :m8
+		addop 'dec',   0x10, :rd
+
+		addop 'add',   0x24, :r_a, :d8
+		addop 'add',   0x25, :r_a, :m8
+		addop 'add',   0x20, :r_a, :rd
+
+		addop 'addc',  0x34, :r_a, :d8
+		addop 'addc',  0x35, :r_a, :m8
+		addop 'addc',  0x30, :r_a, :rd
+
+		addop 'orl',   0x42, :m8, :r_a
+		addop 'orl',   0x43, :m8, :d8
+		addop 'orl',   0x44, :r_a, :d8
+		addop 'orl',   0x45, :r_a, :m8
+		addop 'orl',   0x40, :r_a, :rd
+
+		addop 'anl',   0x52, :m8, :r_a
+		addop 'anl',   0x53, :m8, :d8
+		addop 'anl',   0x54, :r_a, :d8
+		addop 'anl',   0x55, :r_a, :m8
+		addop 'anl',   0x50, :r_a, :rd
+
+		addop 'xrl',   0x62, :m8, :r_a
+		addop 'xrl',   0x63, :m8, :d8
+		addop 'xrl',   0x64, :r_a, :d8
+		addop 'xrl',   0x65, :r_a, :m8
+		addop 'xrl',   0x60, :r_a, :rd
+
+		addop 'mov',   0x74, :r_a, :d8
+		addop 'mov',   0x75, :m8, :d8
+		addop 'mov',   0x70, :rd, :d8
+		addop 'mov',   0xa0, :rd, :m8
+		addop 'mov',   0x85, :m8, :m8
+		addop 'mov',   0x80, :m8, :rd
+		addop 'mov',   0xe0, :r_a, :rd
+		addop 'mov',   0xf0, :rd, :r_a
+
+		addop 'subb',  0x94, :r_a, :d8
+		addop 'subb',  0x95, :r_a, :m8
+		addop 'subb',  0x90, :r_a, :rd
+
+		addop 'cnje',  0xb4, :r_a, :d8, :rel8
+		addop 'cnje',  0xb5, :r_a, :m8, :rel8
+		addop 'cnje',  0xb0, :rd, :d8, :rel8
+
+		addop 'xch',   0xc5, :r_a, :m8
+		addop 'xch',   0xc0, :r_a, :rd
+
+		addop 'djnz',  0xd5, :m8, :rel8
+		addop 'djnz',  0xd0, :rd, :rel8
+
+	end
+end
+end