badline 0.13.0 → 0.15.0

data/lib/badline/chips/sid/filter.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require "badline/chips/sid/filter/saved_state"
-
 module Badline
   module Chips
     class SID
@@ -13,8 +11,6 @@ module Badline
       # and the outputs selected by MODE/VOL are summed back together with the
       # unfiltered ones.
       class Filter
-        include SavedState
-
         # Cutoff frequency in Hz at each chip's breakpoints. The 6581 curve was
         # sampled from a real chip by reSID and bends sharply around $300; the
         # 8580's is close to a straight line from 0 to 12.5 kHz. The curve
@@ -95,16 +91,6 @@ module Badline
             @output = 0
           end
 
-          def save_state(out)
-            out.int(@lowpass).int(@highpass).int(@output)
-          end
-
-          def load_state(input)
-            @lowpass = input.int
-            @highpass = input.int
-            @output = input.int
-          end
-
           # Takes the input in 1/2^Filter::FRACTION units, and reads the
           # output out in whole ones. A step of several cycles moves each pole
           # at most onto its input.

data/lib/badline/chips/sid/keyed_parts.rb

@@ -0,0 +1,286 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class SID
+      class Waveform
+        # An oscillator's fields in a keyed snapshot module, under `prefix`:
+        # the phase, the noise register and its pipeline, the delayed
+        # shapers, the sync edge, the floating output and the pulse level.
+        # What the registers set comes from them on load.
+        module KeyedState
+          # The fields reSID keeps for an oscillator between cycles, for VICE's
+          # SIDEXTENDED module: the phase, the noise register, its shift pipeline
+          # and reset countdown, the floating output's countdown and the pulse
+          # level.
+          def resid_fields
+            [@accumulator, @shift_register, @shift_pipeline, @shift_register_reset, @floating_ttl, @pulse]
+          end
+
+          # Takes the fields resid_fields gives from `fields`, from `at` on.
+          def restore_resid_fields(fields, at)
+            @accumulator = fields[at]
+            @shift_register = fields[at + 1]
+            @shift_pipeline = fields[at + 2]
+            @shift_register_reset = fields[at + 3]
+            @floating_ttl = fields[at + 4]
+            @pulse = fields[at + 5]
+            @stale = true
+          end
+
+          def save_fields(out, prefix)
+            out.int("#{prefix}accumulator", @accumulator).int("#{prefix}shift_register", @shift_register)
+            out.int("#{prefix}shift_register_reset", @shift_register_reset)
+            out.int("#{prefix}shift_pipeline", @shift_pipeline).int("#{prefix}delayed_triangle", @delayed_triangle)
+            out.int("#{prefix}delayed_sawtooth", @delayed_sawtooth).bool("#{prefix}msb_rising", @msb_rising)
+            out.int("#{prefix}floating", @floating).int("#{prefix}floating_ttl", @floating_ttl)
+            out.int("#{prefix}pulse", @pulse)
+          end
+
+          def load_fields(input, prefix)
+            @accumulator = input.masked("#{prefix}accumulator", @accumulator, 0xffffff)
+            @shift_register = input.masked("#{prefix}shift_register", @shift_register, 0x7fffff)
+            @shift_register_reset = input.int("#{prefix}shift_register_reset", @shift_register_reset)
+            @shift_pipeline = input.int("#{prefix}shift_pipeline", @shift_pipeline)
+            @delayed_triangle = input.masked("#{prefix}delayed_triangle", @delayed_triangle, 0xfff)
+            @delayed_sawtooth = input.masked("#{prefix}delayed_sawtooth", @delayed_sawtooth, 0xfff)
+            @msb_rising = input.bool("#{prefix}msb_rising", @msb_rising)
+            @floating = input.masked("#{prefix}floating", @floating, 0xfff)
+            @floating_ttl = input.int("#{prefix}floating_ttl", @floating_ttl)
+            @pulse = input.masked("#{prefix}pulse", @pulse, 0xfff)
+          end
+
+          # The frequency, pulse width and control bits as the registers
+          # hold them, without the test bit's or the waveform change's
+          # effects on the noise register, which already happened.
+          def restore_registers(frequency, pulse_width, control)
+            @frequency = frequency
+            @pulse_width = pulse_width & 0xfff
+            @selected = (control >> 4) & 0x0f
+            @test = control.anybits?(0x08)
+            @ring = control.anybits?(0x04)
+            @sync = control.anybits?(0x02)
+            @stale = true
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Envelope
+        # The envelope generator's fields in a keyed snapshot module, under
+        # `prefix`: the state, the counters and pipelines between them. The
+        # rates and the gate come from the registers on load.
+        module KeyedState
+          # The fields reSID keeps for an envelope between cycles, for VICE's
+          # SIDEXTENDED module: the rate and exponential counters, the level, the
+          # state as an index into STATES, whether it holds at zero, the two
+          # periods and the pipeline.
+          def resid_fields
+            [@rate_counter, @exponential_counter, @counter, STATES.index(@state).to_i, @hold_zero ? 1 : 0,
+             @rate_period, @exponential_period, @envelope_pipeline]
+          end
+
+          # Takes the fields resid_fields gives from `fields`, from `at` on.
+          def restore_resid_fields(fields, at)
+            @rate_counter = fields[at]
+            @exponential_counter = fields[at + 1]
+            @counter = @env3 = fields[at + 2]
+            state = fields[at + 3]
+            @state = @next_state = STATES.fetch(state.clamp(0, STATES.length - 1)).to_sym
+            @hold_zero = fields[at + 4] != 0
+            @rate_period = fields[at + 5]
+            @exponential_period = fields[at + 6]
+            @envelope_pipeline = fields[at + 7]
+          end
+
+          def save_fields(out, prefix)
+            out.text("#{prefix}state", @state.to_s).text("#{prefix}next_state", @next_state.to_s)
+            out.int("#{prefix}counter", @counter).int("#{prefix}env3", @env3)
+            out.int("#{prefix}rate_counter", @rate_counter)
+            out.int("#{prefix}rate_period", @rate_period).bool("#{prefix}reset_rate_counter", @reset_rate_counter)
+            out.int("#{prefix}exponential_counter", @exponential_counter)
+            out.int("#{prefix}exponential_period", @exponential_period)
+            out.int("#{prefix}state_pipeline", @state_pipeline).int("#{prefix}envelope_pipeline", @envelope_pipeline)
+            out.int("#{prefix}exponential_pipeline", @exponential_pipeline).bool("#{prefix}hold_zero", @hold_zero)
+          end
+
+          def load_fields(input, prefix)
+            @state = state_named(input.choice("#{prefix}state", STATE_NAMES, @state.to_s))
+            @next_state = state_named(input.choice("#{prefix}next_state", STATE_NAMES, @next_state.to_s))
+            @counter = input.byte("#{prefix}counter", @counter)
+            @env3 = input.byte("#{prefix}env3", @env3)
+            @rate_counter = input.masked("#{prefix}rate_counter", @rate_counter, 0x7fff)
+            @rate_period = input.int("#{prefix}rate_period", @rate_period)
+            @reset_rate_counter = input.bool("#{prefix}reset_rate_counter", @reset_rate_counter)
+            load_pipeline_fields(input, prefix)
+          end
+
+          # The rates and the gate as the registers hold them.
+          def restore_registers(attack_decay, sustain_release, control)
+            @attack = (attack_decay >> 4) & 0x0f
+            @decay = attack_decay & 0x0f
+            @sustain = (sustain_release >> 4) & 0x0f
+            @release = sustain_release & 0x0f
+            @gate = control.anybits?(0x01)
+          end
+
+          private
+
+          def load_pipeline_fields(input, prefix)
+            @exponential_counter = input.int("#{prefix}exponential_counter", @exponential_counter)
+            @exponential_period = input.int("#{prefix}exponential_period", @exponential_period)
+            @state_pipeline = input.int("#{prefix}state_pipeline", @state_pipeline)
+            @envelope_pipeline = input.int("#{prefix}envelope_pipeline", @envelope_pipeline)
+            @exponential_pipeline = input.int("#{prefix}exponential_pipeline", @exponential_pipeline)
+            @hold_zero = input.bool("#{prefix}hold_zero", @hold_zero)
+          end
+
+          def state_named(name)
+            case name
+            when "attack" then :attack
+            when "decay_sustain" then :decay_sustain
+            else :release
+            end
+          end
+        end
+
+        STATE_NAMES = STATES.map(&:to_s).freeze
+
+        include KeyedState
+      end
+
+      class Voice
+        # A voice's oscillator under `prefix`wave. and its envelope under
+        # `prefix`env.
+        module KeyedState
+          def save_fields(out, prefix)
+            @waveform.save_fields(out, "#{prefix}wave.")
+            @envelope.save_fields(out, "#{prefix}env.")
+          end
+
+          def load_fields(input, prefix)
+            @waveform.load_fields(input, "#{prefix}wave.")
+            @envelope.load_fields(input, "#{prefix}env.")
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Filter
+        class External
+          # The output filter's integrators and output, under `prefix`.
+          module KeyedState
+            def save_fields(out, prefix)
+              out.int("#{prefix}lowpass", @lowpass).int("#{prefix}highpass", @highpass).int("#{prefix}output", @output)
+            end
+
+            def load_fields(input, prefix)
+              @lowpass = input.int("#{prefix}lowpass", @lowpass)
+              @highpass = input.int("#{prefix}highpass", @highpass)
+              @output = input.int("#{prefix}output", @output)
+            end
+          end
+
+          include KeyedState
+        end
+
+        # The filter's integrators and its last input, under `prefix`, and
+        # the output filter's under ext. The cutoff, resonance, routing,
+        # mode and volume come from the registers on load.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}highpass", @highpass).int("#{prefix}bandpass", @bandpass)
+            out.int("#{prefix}lowpass", @lowpass).int("#{prefix}unfiltered", @unfiltered).int("#{prefix}input", @input)
+            @external.save_fields(out, "ext.")
+          end
+
+          def load_fields(input, prefix)
+            @highpass = input.int("#{prefix}highpass", @highpass)
+            @bandpass = input.int("#{prefix}bandpass", @bandpass)
+            @lowpass = input.int("#{prefix}lowpass", @lowpass)
+            @unfiltered = input.int("#{prefix}unfiltered", @unfiltered)
+            @input = input.int("#{prefix}input", @input)
+            @external.load_fields(input, "ext.")
+          end
+
+          # $D415 to $D418 as written.
+          def restore_registers(cutoff_low, cutoff_high, resonance, mode_volume)
+            self.cutoff = (cutoff_high << 3) | (cutoff_low & 0x07)
+            write_resonance(resonance)
+            write_mode_volume(mode_volume)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The SID's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers as written, the data bus latch and its decay, each
+      # voice's under voice1. to voice3., and the filter's under filter.
+      # and ext. Saving catches the DSP up first, so no span or deferred
+      # write is left to save. What the registers decode to is worked out
+      # from them on load.
+      module KeyedState
+        def save_fields(out)
+          catch_up
+          out.bytes("registers", @registers.read(0, 0x20)).int("bus_value", @bus_value).int("bus_ttl", @bus_ttl)
+          @voice1.save_fields(out, "voice1.")
+          @voice2.save_fields(out, "voice2.")
+          @voice3.save_fields(out, "voice3.")
+          @filter.save_fields(out, "filter.")
+          out
+        end
+
+        def load_fields(input)
+          @registers.write(0, input.bytes_into("registers", @registers.read(0, 0x20)))
+          @bus_value = input.byte("bus_value", @bus_value)
+          @bus_ttl = input.int("bus_ttl", @bus_ttl)
+          @pending_cycles = 0
+          @deferred_writes.clear
+          @voice1.load_fields(input, "voice1.")
+          @voice2.load_fields(input, "voice2.")
+          @voice3.load_fields(input, "voice3.")
+          @filter.load_fields(input, "filter.")
+        end
+
+        # How far the recording has got into the sample it is averaging,
+        # under `prefix`, for a host that carries on recording from a
+        # snapshot: it calls #record, then #load_recording_fields.
+        def save_recording_fields(out, prefix)
+          decimator = @decimator
+          raise ArgumentError, "the SID isn't recording" if decimator.nil?
+
+          decimator.save_fields(out, prefix)
+        end
+
+        def load_recording_fields(input, prefix)
+          decimator = @decimator
+          raise ArgumentError, "the SID isn't recording" if decimator.nil?
+
+          decimator.load_fields(input, prefix)
+        end
+
+        def restored!
+          restore_voice(@voice1, 0x00)
+          restore_voice(@voice2, 0x07)
+          restore_voice(@voice3, 0x0e)
+          @filter.restore_registers(register(0x15), register(0x16), register(0x17), register(0x18))
+          update_span_rules
+        end
+
+        private
+
+        def restore_voice(voice, base)
+          control = register(base + 4)
+          voice.waveform.restore_registers(register(base) | (register(base + 1) << 8),
+                                           register(base + 2) | (register(base + 3) << 8), control)
+          voice.envelope.restore_registers(register(base + 5), register(base + 6), control)
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/sid/voice.rb

@@ -45,16 +45,6 @@ module Badline
           @envelope = Envelope.new
         end
 
-        def save_state(out)
-          @waveform.save_state(out)
-          @envelope.save_state(out)
-        end
-
-        def load_state(input)
-          @waveform.load_state(input)
-          @envelope.load_state(input)
-        end
-
         def control=(value)
           @waveform.control = value
           @envelope.control = value

data/lib/badline/chips/sid/waveform.rb

@@ -3,7 +3,6 @@
 require "badline/chips/sid/waveform/combined"
 require "badline/chips/sid/waveform/fast_forward"
 require "badline/chips/sid/waveform/noise_writeback"
-require "badline/chips/sid/waveform/saved_state"
 
 module Badline
   module Chips
@@ -29,7 +28,6 @@ module Badline
       class Waveform
         include FastForward
         include NoiseWriteback
-        include SavedState
 
         # All bits high at power up, odd ones stored inverted (SID/oscinit).
         POWER_ON_ACCUMULATOR = 0x555555

data/lib/badline/chips/sid.rb

@@ -6,7 +6,7 @@ require "badline/chips/sid/voice"
 require "badline/chips/sid/filter"
 require "badline/chips/sid/decimator"
 require "badline/chips/sid/catch_up"
-require "badline/chips/sid/saved_state"
+require "badline/chips/sid/keyed_parts"
 
 module Badline
   module Chips
@@ -37,7 +37,6 @@ module Badline
     class SID
       include Addressable
       include CatchUp
-      include SavedState
 
       VOICES = 3
 

data/lib/badline/chips/ted/beam.rb

@@ -0,0 +1,118 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class TED
+      # The raster and the clock the TED gives the CPU, a single clock
+      # cycle at a time.
+      #
+      # A line is 456 dots, horizontal counts 0-455, and a single clock
+      # cycle 8 of them, so a line is 57 cycles; #column counts them, the
+      # cycle at count 8 * column. The line count steps at count 376, in
+      # column 47, and runs 0-311 on PAL and 0-261 with $FF07 bit 6 set
+      # (NTSC). The datasheet's horizontal and vertical decode tables give
+      # those counts.
+      #
+      # The CPU runs once in a single clock cycle and twice in a double
+      # clock one. The datasheet's "System Clock Doubling": in the display
+      # window's lines the clock is single from count 400 round to 344,
+      # columns 50-56 and 0-42, and double in columns 43-49. The window is
+      # lines 0-203: the datasheet says 0-204, but xplus4 runs line 204 at
+      # double clock, as the lines below it. In the other lines it is double
+      # but for the five refresh cycles at counts 304-344, columns 38-42,
+      # which are single everywhere. With $FF06 bit 4 clear (blank) every
+      # line is double but for refresh, and $FF13 bit 1 or $FF07 bit 5
+      # (freeze) makes every cycle single.
+      #
+      # So a display line gives the CPU 64 cycles and a border line 109,
+      # the counts measured on real machines.
+      #
+      # DMA: each character row takes the bus for 40 cycles on two lines,
+      # the line before the row for the attributes and the row's first
+      # line for the character pointers (the datasheet's register 20). A
+      # row starts on the line after one whose low three bits match $FF06
+      # bits 0-2, as the KERNAL's scroll of 3 puts the first row on line 4,
+      # where the datasheet's 25-row window starts, and a row starts only
+      # in lines 0-203. xplus4 takes the bus on the same lines. The fetches run in columns 54-56 and 0-36, and BA
+      # goes low 3 cycles before the first, in column 51, so the CPU stops
+      # at its next read. A DMA line leaves the CPU 24 cycles.
+      module Beam
+        CYCLES_PER_LINE = 57
+        LINE_STEP_COLUMN = 47
+        BA_COLUMN = 51
+        DMA_COLUMN = 54
+        DMA_END_COLUMN = 36
+        REFRESH_COLUMNS = (38..42)
+        DOUBLE_COLUMNS = (43..49)
+        LAST_DISPLAY_LINE = 203
+
+        # The DMA a line makes: none, the attributes or the pointers.
+        NO_DMA = 0
+        ATTRIBUTE_DMA = 1
+        POINTER_DMA = 2
+
+        # The single clock cycle in the line, 0-56.
+        attr_reader :column
+
+        # The raster line.
+        attr_reader :line
+
+        # How many cycles the CPU runs in this cycle: 0 while the TED holds
+        # the bus for DMA, 1 at single clock and 2 at double clock.
+        attr_reader :cpu_slots
+
+        # Whether BA is low, from 3 cycles before DMA to its end.
+        def ba_low? = @ba_low
+
+        # Lines a frame, by $FF07 bit 6.
+        def lines_per_frame = @registers[0x07].anybits?(0x40) ? 262 : 312
+
+        private
+
+        def reset_beam
+          @column = 0
+          @line = 0
+          @ba_low = false
+          @cpu_slots = 1
+        end
+
+        def move_beam
+          column = @column + 1
+          column = 0 if column == CYCLES_PER_LINE
+          @column = column
+          return unless column == LINE_STEP_COLUMN
+
+          line = @line + 1
+          if line >= lines_per_frame
+            line = 0
+            end_frame
+          end
+          step_row_line(line)
+          step_scanline(line)
+          self.line = line
+        end
+
+        # The clock for the cycle. Freeze leaves single clock, without DMA.
+        def decide_clock
+          column = @column
+          if @dma_kind != NO_DMA && (column >= BA_COLUMN || column <= DMA_END_COLUMN) && !frozen?
+            @ba_low = true
+            @cpu_slots = column >= DMA_COLUMN || column <= DMA_END_COLUMN ? 0 : 1
+            return
+          end
+
+          @ba_low = false
+          @cpu_slots = single_clock?(column) ? 1 : 2
+        end
+
+        def single_clock?(column)
+          return true if REFRESH_COLUMNS.include?(column) || @registers[0x13].anybits?(0x02) || frozen?
+
+          display_window? && !DOUBLE_COLUMNS.include?(column)
+        end
+
+        def display_window? = @registers[0x06].anybits?(0x10) && @line <= LAST_DISPLAY_LINE
+      end
+    end
+  end
+end

data/lib/badline/chips/ted/fetches.rb

@@ -0,0 +1,199 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class TED
+      # What the TED reads for the picture, a single clock cycle at a time,
+      # and the counters that say where it reads.
+      #
+      # The two DMA lines of a character row (Beam) fetch a byte a cycle
+      # in phi2, in the 40 cycles of the character window, columns 54-56
+      # and 0-36: the attributes on the line before the row, from the video
+      # matrix base ($FF14 bits 3-7) with A10 clear, and the character
+      # pointers on the row's first line, with A10 set (the datasheet's
+      # video matrix and attribute addresses). The attributes go to a
+      # buffer of their own, and each takes hold as its character's
+      # pointer is fetched, so the row before shows its own colours to its
+      # last line, as xplus4 shows them.
+      #
+      # On every line of a row, from the cycle after each pointer's, the
+      # TED fetches the character's pattern byte in phi1, columns 55-56
+      # and 0-37: from the character base ($FF13 bits 2-7) with the
+      # pointer and the row's line counter, or from the bitmap base ($FF12
+      # bits 3-5) with the character position and the line counter in
+      # bitmap mode. With $FF07 bit 7 clear the pointer's bit 7 asks for
+      # reverse and the character base supplies A10; extended colour mode
+      # forces A9 and A10 low. The byte stays on the bus, where a read of
+      # an address nothing answers finds it (Plus/4 openio's outrun2).
+      #
+      # The matrix fetches see ROM or RAM as the CPU does at $8000-$FFFF,
+      # and the pattern fetches ROM with $FF12 bit 2 set or RAM with it
+      # clear (Plus4::Bus#ted_fetch and #ted_pattern_fetch).
+      #
+      # The counters: the character position reload ($FF1A-$FF1B), the
+      # character position the row starts at, which steps by 40 at the end
+      # of a row's eighth line, at horizontal count 290; and the vertical
+      # sub-address ($FF1F bits 0-2), the row's line, which steps with the
+      # line count on the display window's lines once the frame's first
+      # row is under way, wrapping from 7 to 0 whatever the DMA lines do.
+      # The attribute line reads the row the reload points to after its
+      # own latch: 40 on from it on a row's eighth line, the reload itself
+      # otherwise. The pointer line is the line after an attribute line. A
+      # frame starts with both counters at 0 and no row under way, and the
+      # frame's first pointer line puts a row under way to the end of the
+      # frame. The display window's lines with a row under way and the
+      # display on fetch pattern bytes.
+      module Fetches
+        # The first and last cycles of the pattern fetches.
+        PATTERN_COLUMN = 55
+        PATTERN_END_COLUMN = 37
+
+        # The cycle that latches the next row's character position.
+        LATCH_COLUMN = 36
+
+        # The cycle that counts the blink counter, horizontal count 336.
+        BLINK_COLUMN = 42
+
+        CHARACTERS = 40
+
+        # The pattern bytes, pointers and attributes of the characters on
+        # the line being fetched.
+        attr_reader :patterns, :pointers, :attributes
+
+        # The character position reload, the row's line, and whether a row
+        # is under way.
+        attr_reader :char_position, :row_line, :row_active
+
+        # The bus the TED fetches from, the machine's.
+        def connect(bus)
+          @bus = bus
+        end
+
+        private
+
+        def reset_fetches
+          @patterns = Array.new(CHARACTERS, 0)
+          @pointers = Array.new(CHARACTERS, 0)
+          @attributes = Array.new(CHARACTERS, 0)
+          @fetched_attributes = Array.new(CHARACTERS, 0)
+          @char_position = 0
+          @line_position = 0
+          @row_line = 0
+          @row_active = false
+          @dma_kind = Beam::NO_DMA
+          @pattern_fetches = false
+        end
+
+        # The fetches and counters of the cycle in +column+.
+        def fetch(column)
+          if column <= Beam::DMA_END_COLUMN || column >= Beam::DMA_COLUMN
+            window_fetch(column)
+          elsif column == PATTERN_END_COLUMN
+            pattern_fetch(column) if @pattern_fetches
+          elsif column == Beam::BA_COLUMN
+            start_line_fetches
+          elsif column == BLINK_COLUMN
+            count_blink
+          end
+        end
+
+        # A cycle of the character window.
+        def window_fetch(column)
+          dma_fetch(column) unless @dma_kind == Beam::NO_DMA
+          pattern_fetch(column) if @pattern_fetches && column != Beam::DMA_COLUMN
+          latch_char_position if column == LATCH_COLUMN
+        end
+
+        # The blink counter counts a frame on one line of the vertical
+        # blank, the line xplus4 counts it on.
+        def count_blink
+          return unless @line == (lines_per_frame == 312 ? 256 : 228)
+
+          @blink = (@blink + 1) & 0x0f
+          blink_carry if @blink.zero?
+        end
+
+        # Column 51: what the line fetches, decided where BA is.
+        def start_line_fetches
+          @dma_kind = dma_kind
+          @row_active = true if @dma_kind == Beam::POINTER_DMA
+          @line_position = @char_position
+          @pattern_fetches = @row_active && @line <= Beam::LAST_DISPLAY_LINE && display_enabled? && !@bus.nil?
+        end
+
+        # The attributes on a line whose low three bits match $FF06's
+        # scroll, below line 203, and the pointers on the line after one
+        # that fetched attributes (the datasheet's DMA timing, step 8),
+        # whatever the scroll says by then.
+        def dma_kind
+          return Beam::NO_DMA unless display_enabled?
+          return Beam::POINTER_DMA if @dma_kind == Beam::ATTRIBUTE_DMA
+          return Beam::NO_DMA unless @line < Beam::LAST_DISPLAY_LINE
+
+          (@line - @registers[0x06]).nobits?(0x07) ? Beam::ATTRIBUTE_DMA : Beam::NO_DMA
+        end
+
+        def display_enabled? = @registers[0x06].anybits?(0x10)
+
+        def dma_fetch(column)
+          bus = @bus
+          return if bus.nil?
+
+          index = column >= Beam::DMA_COLUMN ? column - Beam::DMA_COLUMN : column + (Beam::CYCLES_PER_LINE - Beam::DMA_COLUMN)
+          matrix = (@registers[0x14] & 0xf8) << 8
+          if @dma_kind == Beam::ATTRIBUTE_DMA
+            position = latching? ? @char_position + CHARACTERS : @char_position
+            @fetched_attributes[index] = bus.ted_fetch(matrix | ((position + index) & 0x3ff))
+          else
+            @pointers[index] = bus.ted_fetch(matrix | 0x400 | ((@char_position + index) & 0x3ff))
+            @attributes[index] = @fetched_attributes[index]
+          end
+        end
+
+        def pattern_fetch(column)
+          index = column >= PATTERN_COLUMN ? column - PATTERN_COLUMN : column + (Beam::CYCLES_PER_LINE - PATTERN_COLUMN)
+          @patterns[index] = @bus.ted_pattern_fetch(pattern_address(index), @registers[0x12].anybits?(0x04))
+        end
+
+        def pattern_address(index)
+          return bitmap_address(index) if @registers[0x06].anybits?(0x20)
+
+          pointer = @pointers[index]
+          base = @registers[0x13] & 0xf8
+          if @registers[0x06].anybits?(0x40)
+            pointer &= 0x3f
+          elsif !@registers[0x07].anybits?(0x80)
+            pointer = (pointer & 0x7f) | ((@registers[0x13] & 0x04) << 5)
+          end
+          (base << 8) | (pointer << 3) | @row_line
+        end
+
+        def bitmap_address(index)
+          ((@registers[0x12] & 0x38) << 10) | (((@line_position + index) & 0x3ff) << 3) | @row_line
+        end
+
+        # The end of a row's eighth line moves the reload on to the next
+        # row.
+        def latch_char_position
+          @char_position = (@char_position + CHARACTERS) & 0x3ff if latching?
+        end
+
+        # Whether the line ends a row, and latches the next row's position.
+        def latching? = @row_active && @row_line == 7 && @line <= Beam::LAST_DISPLAY_LINE
+
+        # The line count steps to +line+: the row's next line, up to the
+        # last line of the display window.
+        def step_row_line(line)
+          @row_line = (@row_line + 1) & 0x07 if @row_active && line <= Beam::LAST_DISPLAY_LINE
+        end
+
+        # The end of the frame.
+        def end_fetch_frame
+          @char_position = 0
+          @row_line = 0
+          @row_active = false
+        end
+      end
+    end
+  end
+end