badline 0.13.0 → 0.15.0

data/lib/badline/c128/keyed_modules.rb

@@ -0,0 +1,117 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The whole machine as keyed snapshot modules (Snapshot::Keyed), in the
+    # order a load applies them, as C64::KeyedModules: BL-MACHINE with the
+    # last bus access under bus.*, the RAM, both banks of colour RAM, the
+    # MMU, the cartridge, the 8502 with its port, the Z80, the chips, the
+    # datasette, device 8 through the traps and the true drives. The
+    # machine's own fields load after the Z80's, which z80_ahead counts
+    # from.
+    module KeyedModules
+      def save_modules
+        bus = @bus
+        sections = [Snapshot::Keyed.section("BL-MACHINE") do |out|
+          save_machine_fields(out)
+          bus.save_fields(out, "bus.")
+        end]
+        sections << Snapshot::Keyed.section("BL-RAM") { |out| bus.ram.save_fields(out, "ram") }
+        sections << Snapshot::Keyed.section("BL-COLORRAM") { |out| bus.save_color_fields(out) }
+        sections << Snapshot::Keyed.section("BL-MMU") { |out| bus.mmu.save_fields(out) }
+        cartridge = bus.cartridge
+        sections << Snapshot::Keyed.section("BL-CART") { |out| cartridge.save_fields(out) } if cartridge
+        save_chip_modules(sections, bus)
+        sections << Snapshot::Keyed.section("BL-TAPE") { |out| bus.datasette.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-TRAPDOS") { |out| save_trap_dos_fields(out) } if mounted?
+        save_drive_modules(sections)
+      end
+
+      # Raises Snapshot::FormatError for the modules of another model, SID
+      # or mode.
+      def load_modules(modules)
+        machine = modules.machine
+        check_snapshot_setup(Snapshot::C128Setup.read_fields(machine))
+        bus = @bus
+        bus.ram.load_fields(modules.required("BL-RAM"), "ram")
+        bus.load_color_fields(modules.required("BL-COLORRAM"))
+        bus.mmu.load_fields(modules.required("BL-MMU"))
+        load_cartridge_module(modules.optional("BL-CART"))
+        load_chip_modules(modules)
+        bus.load_fields(machine, "bus.")
+        load_machine_fields(machine)
+        bus.datasette.load_fields(modules.required("BL-TAPE"))
+        trap_dos = modules.optional("BL-TRAPDOS")
+        trap_dos ? load_trap_dos_fields(trap_dos, detached: modules.detached?) : unmount
+        load_drive_modules(modules)
+        modules_restored!
+        self
+      end
+
+      private
+
+      def save_chip_modules(sections, bus)
+        sections << Snapshot::Keyed.section("BL-CPU") do |out|
+          @cpu.save_fields(out)
+          bus.save_port_fields(out)
+        end
+        sections << Snapshot::Keyed.section("BL-Z80") { |out| @z80.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-VIC") { |out| @vic.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-VDC") { |out| @vdc.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-CIA1") { |out| @cia1.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-CIA2") { |out| @cia2.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-SID") { |out| @sid.save_fields(out) }
+      end
+
+      # The port goes in ahead of the chips, as the C64's does, and the bus
+      # maps its banks and the keyboard's extra rows once they are in. That
+      # hands the bus to the CPU the MMU names, which resets the Z80's
+      # schedule and can reset the 8502, so the CPUs, the last bus access
+      # and the machine's own fields load after it.
+      def load_chip_modules(modules)
+        cpu = modules.required("BL-CPU")
+        @bus.load_port_fields(cpu)
+        @vic.load_fields(modules.required("BL-VIC"))
+        @vdc.load_fields(modules.required("BL-VDC"))
+        @cia1.load_fields(modules.required("BL-CIA1"))
+        @cia2.load_fields(modules.required("BL-CIA2"))
+        @sid.load_fields(modules.required("BL-SID"))
+        @bus.restored!
+        @cpu.load_fields(cpu)
+        @z80.load_fields(modules.required("BL-Z80"))
+      end
+
+      # The cartridge comes back built afresh from the CRT image the module
+      # holds, before its state goes in. No module means no cartridge.
+      def load_cartridge_module(input)
+        if input
+          cartridge = C64::Cartridge.from_fields(input)
+          connect_cartridge(cartridge)
+          cartridge.load_fields(input)
+        elsif @bus.cartridge
+          @bus.detach_cartridge
+        end
+      end
+
+      def modules_restored!
+        @cpu.restored!
+        @z80.restored!
+        @vic.restored!
+        @vdc.restored!
+        @cia1.restored!
+        @cia2.restored!
+        @sid.restored!
+        machine_restored!
+      end
+
+      def check_snapshot_setup(setup)
+        ours = snapshot_setup
+        return if setup == ours
+
+        raise Snapshot::FormatError, "the snapshot is of a #{setup}, not a #{ours}"
+      end
+    end
+
+    include KeyedModules
+  end
+end

data/lib/badline/c128/keyed_state.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The machine's own fields in a keyed snapshot module (Snapshot::Keyed,
+    # BL-MACHINE): the family, its model, SID and mode by name, the cycle
+    # count, $D030's clock bits on their way, the NMI glue, the two
+    # schedulers' offsets (z80_ahead, the Z80's T-states past when it was
+    # due, and chips_ahead), an 8502 reset waiting for the bus, and under
+    # host.* the host's typing (the codes still to type, whether it is
+    # typing, and where Input::MatrixTypist is in a code on the key
+    # matrix), C= held from power-on and the on_init handlers still to run.
+    # They load after the Z80's own fields, which z80_ahead counts from.
+    module KeyedState
+      # How many more on_init handlers the machine a snapshot was taken of had
+      # yet to run than this one has. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      # Whether a snapshot saves now (Machine::Settling): the 8502 between
+      # instructions or jammed. While the Z80 runs, the 8502 waits at the
+      # boundary it handed the bus over at, and the Z80 runs whole
+      # instructions.
+      def settled_for_snapshot? = @cpu.boundary? || @cpu.jammed?
+
+      # The SID's deferred cycles and writes, run up to this cycle, and the
+      # VIC's sprite collisions latched up to the beam.
+      def settle_chips_for_snapshot
+        sid.catch_up!
+        @vic.fold_collisions!
+      end
+
+      def save_machine_fields(out)
+        out.text("family", "c128").text("written_by", VERSION)
+        snapshot_setup.write_fields(out)
+        out.int("cycles", @cycles).int("clock_bits", @clock_bits).bool("nmi_asserted", @nmi_asserted)
+        out.bool("cartridge_nmi", @cartridge_nmi).bool("restore_pulse", @restore_pulse)
+        out.int("z80_ahead", @z80.cycles - @z80_due).int("chips_ahead", @chips_ahead)
+        out.bool("cpu_reset_pending", @cpu_reset_pending)
+        pending = @pending_keys
+        out.ints("host.pending_keys", pending) if pending
+        out.bool("host.typing", !pending.nil?)
+        out.int("host.init_pending", @cycles <= init_threshold ? @init_handlers.length : 0)
+        out.bool("host.holding_commodore", @holding_commodore)
+        @typist.save_fields(out, "host.typist.")
+      end
+
+      def load_machine_fields(input)
+        @cycles = input.int("cycles", @cycles)
+        @clock_bits = input.int("clock_bits", @clock_bits)
+        @nmi_asserted = input.bool("nmi_asserted", @nmi_asserted)
+        @cartridge_nmi = input.bool("cartridge_nmi", @cartridge_nmi)
+        @restore_pulse = input.bool("restore_pulse", @restore_pulse)
+        @z80_due = @z80.cycles - input.int("z80_ahead", @z80.cycles - @z80_due)
+        @chips_ahead = input.int("chips_ahead", @chips_ahead)
+        @cpu_reset_pending = input.bool("cpu_reset_pending", @cpu_reset_pending)
+        pending = input.ints("host.pending_keys", [])
+        @pending_keys = input.bool("host.typing", !pending.empty?) ? pending.dup : nil
+        @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+        load_holding_fields(input)
+        @typist.load_fields(input, "host.typist.")
+      end
+
+      # Which CPU has the bus and whose turn it is, from the MMU and the
+      # schedulers' offsets, and the serial bus's lines.
+      def machine_restored!
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+        push_serial_lines
+        push_fast_serial
+      end
+
+      private
+
+      # C= held from power-on until the machine reaches C64 mode
+      # (Modes#hold_commodore_key).
+      def load_holding_fields(input)
+        holding = input.bool("host.holding_commodore", @holding_commodore)
+        keyboard.release(:cbm) if @holding_commodore && !holding
+        keyboard.press(:cbm) if holding && !@holding_commodore
+        @holding_commodore = holding
+      end
+
+      # How this machine was built.
+      def snapshot_setup
+        Snapshot::C128Setup.new(model: @model.name, sid_model: @sid.model, mode: @c64_built ? :c64 : :c128)
+      end
+    end
+
+    include KeyedState
+  end
+end

data/lib/badline/c128/keys.rb

@@ -21,6 +21,11 @@ module Badline
         @bus.caps_lock = false
       end
 
+      # Pushes CAPS LOCK, down if it was up and up if it was down.
+      def push_caps_lock
+        @bus.caps_lock = !@bus.caps_lock
+      end
+
       # The 40/80 DISPLAY key locks down and up. The KERNAL reads it at reset
       # and starts the screen editor on the VDC's 80 columns while it is down.
       def press_display_key
@@ -30,6 +35,10 @@ module Badline
       def release_display_key
         @bus.mmu.display_key = false
       end
+
+      def push_display_key
+        @bus.mmu.display_key = !@bus.mmu.display_key
+      end
     end
   end
 end

data/lib/badline/c128/mmu.rb

@@ -151,16 +151,17 @@ module Badline
         end
       end
 
-      # The registers and the P0H and P1H writes waiting for P0L and P1L.
-      # The bus maps the restored registers once its own state is back.
-      def save_state(out)
-        out.ints(@registers).int(@p0h_latch).int(@p1h_latch)
+      # The registers and the page pointers' high bytes waiting for their
+      # low bytes, in a keyed snapshot module (Snapshot::Keyed). The bus
+      # maps its banks from them afterwards.
+      def save_fields(out)
+        out.bytes("registers", @registers).int("p0h_latch", @p0h_latch).int("p1h_latch", @p1h_latch)
       end
 
-      def load_state(input)
-        input.ints_into(@registers)
-        @p0h_latch = input.int
-        @p1h_latch = input.int
+      def load_fields(input)
+        input.bytes_into("registers", @registers)
+        @p0h_latch = input.masked("p0h_latch", @p0h_latch, 0x0f)
+        @p1h_latch = input.masked("p1h_latch", @p1h_latch, 0x0f)
       end
 
       # CR and the LCRs at $FF00-$FF04: an LCR reads its PCR.

data/lib/badline/c128/mmu_pages.rb

@@ -46,6 +46,33 @@ module Badline
           end
         end
 
+        # The system ROM's byte at +addr+, $8000 or above, as CR value 0 maps it.
+        def system_rom_peek(addr)
+          if addr < 0xc000
+            @basic_high_rom.peek(addr)
+          elsif addr < 0xd000
+            @editor_rom.peek(addr)
+          elsif addr < 0xe000
+            @c128_character_rom.peek(addr)
+          else
+            @c128_kernal_rom.peek(addr)
+          end
+        end
+
+        # The chip's byte at +addr+, in $D000-$DFFF, as C128 mode's I/O maps it.
+        def bank_io_peek(addr)
+          lay_out_io(@bank_io_reads, @bank_io_writes)
+          @bank_io_reads[0xd5] = @mmu
+          @bank_io_reads[addr >> 8].peek(addr)
+        end
+
+        # Writes the chip at +addr+, in $D000-$DFFF, as C128 mode's I/O maps it.
+        def bank_io_poke(addr, value)
+          lay_out_io(@bank_io_reads, @bank_io_writes)
+          @bank_io_writes[0xd5] = @mmu
+          @bank_io_writes[addr >> 8].poke(addr, value)
+        end
+
         # The bank CR picks, with common RAM in bank 0, then the pages page 0
         # and page 1 move to.
         def map_ram_pages

data/lib/badline/c128/modes.rb

@@ -46,15 +46,25 @@ module Badline
 
       # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
       # C128 mode BASIC 7.0's.
-      def feed_keyboard
-        c64 = mode == :c64
-        count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
-        return unless ram.peek(count).zero?
-
-        chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
-        ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
-        ram.poke(count, chunk.length)
-        @pending_keys = nil if @pending_keys.empty?
+      def keyboard_buffer
+        mode == :c64 ? Machine::KeyboardBuffer::C64_LAYOUT : Machine::KeyboardBuffer::C128_LAYOUT
+      end
+
+      # Types the text type_text left: into the keyboard buffer, or while
+      # the Z80 runs, as under CP/M, where no KERNAL reads the buffer, on
+      # the key matrix, all of it once begun there.
+      def type_pending
+        if @z80_running || @typist.typing?
+          type_on_matrix
+        else
+          feed_keyboard
+        end
+      end
+
+      def type_on_matrix
+        pending = @pending_keys
+        @typist.cycle!(pending)
+        @pending_keys = nil if pending.empty? && !@typist.typing?
       end
     end
   end

data/lib/badline/c128/z80_turns.rb

@@ -58,7 +58,7 @@ module Badline
       # interrupt lines going to the Z80.
       def clock_chips
         handle_init if @cycles == @init_threshold
-        feed_keyboard if @pending_keys
+        type_pending if @pending_keys
 
         clock_bits = @clock_bits
         @clock_bits = @vic.clock_bits

data/lib/badline/c128.rb

@@ -8,12 +8,14 @@ require "badline/c128/io_pages"
 require "badline/c128/z80_pages"
 require "badline/c128/color_lines"
 require "badline/c128/banks"
-require "badline/c128/bus/saved_state"
+require "badline/c128/bus/keyed_state"
 require "badline/c128/bus"
 require "badline/c128/cpu"
 require "badline/c128/z80"
 require "badline/c128/z80_turns"
-require "badline/c128/saved_state"
+require "badline/snapshot/c128_setup"
+require "badline/c128/keyed_state"
+require "badline/c128/keyed_modules"
 require "badline/c128/keys"
 require "badline/c128/modes"
 require "badline/c128/drives"
@@ -43,8 +45,9 @@ module Badline
   # mirrors, and $D500-$D7FF holds the hidden MMU, the VDC and open bus.
   class C128
     include IntegerHelper
-    include KeyboardBuffer
+    include Machine::KeyboardBuffer
     include Machine::Clocking
+    include Machine::Settling
     include C64::Common
     include C64::Attachments
     include C64::KernalTraps
@@ -67,10 +70,6 @@ module Badline
     # BASIC 7.0's, which is READY by then.
     C128_INIT_THRESHOLD = 2_000_000
 
-    # The C128 KERNAL's keyboard buffer and its count.
-    C128_KEYBOARD_BUFFER = 0x034a
-    C128_KEYBOARD_COUNT = 0xd0
-
     attr_reader :cpu, :cycles, :drive1541, :model, :init_threshold
 
     def family = :c128
@@ -140,6 +139,7 @@ module Badline
       @restore_pulse = false
       @init_handlers = []
       @pending_keys = nil
+      @typist = Input::MatrixTypist.new(@bus.keyboard)
       @capture_output = nil
       init_drives
       enter_c64_mode if @c64_built
@@ -154,7 +154,7 @@ module Badline
       return z80_cycle! if @z80_turn
 
       handle_init if @cycles == @init_threshold
-      feed_keyboard if @pending_keys
+      type_pending if @pending_keys
 
       clock_bits = @clock_bits
       @clock_bits = @vic.clock_bits

data/lib/badline/c64/attachments.rb

@@ -37,50 +37,6 @@ module Badline
       def push_serial_lines
         @iec_bus.host_lines = @cia2.port_a_lines
       end
-
-      def save_cartridge(out)
-        cartridge = address_bus.cartridge
-        out.boolean(!cartridge.nil?)
-        cartridge&.save_setup(out)
-      end
-
-      # A cartridge comes back built afresh from the setup it was built
-      # with, before the address bus puts its state into it.
-      def load_cartridge(input)
-        if input.boolean?
-          connect_cartridge(Cartridge.from_setup(input))
-        elsif address_bus.cartridge
-          address_bus.detach_cartridge
-        end
-      end
-
-      # A true 1541 on the serial bus, then a 1581.
-      def save_serial_bus(out)
-        out.boolean(!@drive1541.nil?)
-        if @drive1541
-          out.int(@drive1541.device)
-          @drive1541.save_state(out)
-        end
-        save_drive1581(out)
-      end
-
-      def load_serial_bus(input)
-        load_drive1541(input)
-        load_drive1581(input)
-      end
-
-      # The REU, which the setup says the machine has, and whether it has
-      # asked for the bus. Its IRQ line reaches the CPU as it was.
-      def save_reu(out)
-        @reu&.save_state(out)
-        out.boolean(@dma)
-      end
-
-      def load_reu(input)
-        @reu&.load_state(input)
-        @reu_irq = @reu ? @reu.irq? : false
-        @dma = input.boolean?
-      end
     end
   end
 end

data/lib/badline/c64/banked_ram/plus256k.rb

@@ -33,18 +33,26 @@ module Badline
 
         def type = :plus256k
 
-        def save_state(out)
-          [@low_ram, @video_ram, @high_ram].each { |bank| out.int(@banks.index(bank)) }
-          out.boolean(@locked)
-          @banks.drop(1).each { |bank| bank.save_state(out) }
+        # $D100 as the banks it picks give it, whether it is locked, and
+        # banks 1 to 3, in a keyed snapshot module.
+        def save_fields(out)
+          low = @banks.index(@low_ram).to_i
+          video = @banks.index(@video_ram).to_i
+          out.int("d100", low | (video << 2) | (@banks.index(@high_ram).to_i << 6)).bool("locked", @locked)
+          @banks[1].save_fields(out, "bank1")
+          @banks[2].save_fields(out, "bank2")
+          @banks[3].save_fields(out, "bank3")
         end
 
-        def load_state(input)
-          @low_ram = @banks.fetch(input.int)
-          @video_ram = @banks.fetch(input.int)
-          @high_ram = @banks.fetch(input.int)
-          @locked = input.boolean?
-          @banks.drop(1).each { |bank| bank.load_state(input) }
+        def load_fields(input)
+          value = input.byte("d100", 0)
+          @low_ram = @banks[value & 0b11]
+          @video_ram = @banks[(value >> 2) & 0b11]
+          @high_ram = @banks[value >> 6]
+          @locked = input.bool("locked", @locked)
+          @banks[1].load_fields(input, "bank1")
+          @banks[2].load_fields(input, "bank2")
+          @banks[3].load_fields(input, "bank3")
         end
 
         def power_on!

data/lib/badline/c64/banked_ram/plus60k.rb

@@ -26,14 +26,16 @@ module Badline
 
         def type = :plus60k
 
-        def save_state(out)
-          out.int(@banks.index(@high_ram))
-          @banks[1].save_state(out)
+        # $D100 as bit 7 picks the bank above $1000, and bank 1, in a
+        # keyed snapshot module.
+        def save_fields(out)
+          out.int("d100", @banks.index(@high_ram).to_i << 7)
+          @banks[1].save_fields(out, "bank1")
         end
 
-        def load_state(input)
-          @high_ram = @banks.fetch(input.int)
-          @banks[1].load_state(input)
+        def load_fields(input)
+          @high_ram = @banks[(input.byte("d100", @banks.index(@high_ram).to_i << 7) >> 7) & 1]
+          @banks[1].load_fields(input, "bank1")
         end
 
         def power_on!

data/lib/badline/c64/banked_ram/unexpanded.rb

@@ -17,9 +17,9 @@ module Badline
 
         def map_io(_read_pages, _write_pages); end
 
-        def save_state(_out); end
+        def save_fields(_out); end
 
-        def load_state(_input); end
+        def load_fields(_input); end
 
         def reset!; end
 

data/lib/badline/c64/bus/debug_register.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The VICE debug cartridge register, mapped at $D7FF on the C64. It is a
+      # VICE facility rather than real hardware, enabled there with -debugcart:
+      # writing a byte ends the run with that value as the exit code. The VICE
+      # test suites write $00 for success and $ff for failure.
+      #
+      # Wraps the SID's top mirror page, so every other access falls through.
+      class DebugRegister
+        ADDRESS = 0xd7ff
+
+        def initialize(sid, &handler)
+          @sid = sid
+          @handler = handler
+        end
+
+        def peek(addr)
+          @sid.peek(addr)
+        end
+
+        def poke(addr, value)
+          return @handler.call(value) if addr == ADDRESS
+
+          @sid.poke(addr, value)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/extra_sids.rb

@@ -7,7 +7,16 @@ module Badline
       # them, each over its 32 bytes of the I/O area (SIDSlots). The SID
       # player's machine has nothing else in I/O 1 and 2, so the rest of a
       # page there reads the open bus.
+      #
+      # A snapshot holds each in its own keyed module, BL-SID2 onwards in the
+      # order they were fitted, with the address it sits at and its model
+      # ahead of the SID's own fields.
       module ExtraSIDs
+        SID_MODEL_NAMES = %w[mos6581 mos8580].freeze
+
+        # The SIDs fitted past the first, in the order they were fitted.
+        attr_reader :extra_sids
+
         # Fits a SID at the address it was built at, where it takes its 32
         # bytes over from whatever maps there.
         def add_sid(sid)
@@ -18,14 +27,85 @@ module Badline
             @sid_slots << slots
           end
           slots.place(sid)
+          @extra_sids << sid
+          update_overlays!
+        end
+
+        # Takes the extra SIDs out, giving their addresses back to what maps
+        # there.
+        def remove_extra_sids
+          @sid_slots.clear
+          @extra_sids.clear
           update_overlays!
         end
 
+        def save_extra_sid_modules(sections)
+          @extra_sids.each_with_index do |sid, index|
+            sections << Snapshot::Keyed.section("BL-SID#{index + 2}") do |out|
+              out.int("address", sid.start).text("model", sid.model.to_s)
+              sid.save_fields(out)
+            end
+          end
+          sections
+        end
+
+        # Fits the extra SIDs the snapshot's modules hold and loads them. A
+        # SID already fitted at the same address stays, on the model the
+        # snapshot names, and one the snapshot hasn't comes out. A module
+        # whose address no SID fits at is left out, and reported.
+        def load_extra_sid_modules(modules)
+          addresses = []
+          inputs = extra_sid_inputs(modules, addresses)
+          models = inputs.map { |input| sid_model_named(input.choice("model", SID_MODEL_NAMES, "mos6581")) }
+          refit_sids(addresses, models)
+          @extra_sids.each_with_index do |sid, index|
+            model = models[index]
+            sid.model = model unless sid.model == model
+            sid.load_fields(inputs[index])
+          end
+        end
+
         private
 
         def map_extra_sids
           @sid_slots.each { |slots| @read_pages[slots.page] = @write_pages[slots.page] = slots }
         end
+
+        def extra_sid_inputs(modules, taken)
+          inputs = []
+          number = 2
+          input = modules.optional("BL-SID2")
+          while input
+            address = input.word("address", 0xd420)
+            if sid_fits?(address) && !taken.include?(address)
+              inputs << input
+              taken << address
+            else
+              input.adjust(format("no SID fits at $%04x, so it's left out", address))
+            end
+            number += 1
+            input = modules.optional("BL-SID#{number}")
+          end
+          inputs
+        end
+
+        # A SID's 32 bytes past the first SID's own, in $D420-$D7FF, or in
+        # I/O 1 or 2.
+        def sid_fits?(address)
+          address.nobits?(0x1f) && ((0xd420..0xd7e0).cover?(address) || (0xde00..0xdfe0).cover?(address))
+        end
+
+        def sid_model_named(name) = name == "mos8580" ? :mos8580 : :mos6581
+
+        def refit_sids(addresses, models)
+          fitted = @extra_sids.dup
+          return if fitted.map(&:start) == addresses
+
+          remove_extra_sids
+          addresses.each_with_index do |address, index|
+            add_sid(fitted.find { |sid| sid.start == address } || Chips::SID.new(model: models[index], at: address))
+          end
+        end
       end
     end
   end