badline 0.13.0 → 0.15.0

data/lib/badline/c64/bus/keyed_state.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The 6510's port under port.* in a keyed snapshot module
+      # (Snapshot::Keyed, BL-CPU), and the bus once its memories, the port
+      # and the cartridge are loaded: the banks the CPU and the VIC see are
+      # worked out again.
+      module KeyedState
+        # The RAM expansion fitted, or an Unexpanded stand-in.
+        attr_reader :ram_expansion
+
+        # Takes the cartridge out of the expansion port, as a restore does for
+        # a snapshot without one.
+        def detach_cartridge
+          @cartridge = nil
+          update_overlays!
+        end
+
+        # The 6510 port's direction and output registers, and the charge left
+        # on its floating bits.
+        def port_state = [@cpu_port.ddr, @cpu_port.data, @cpu_port.floating]
+
+        # Sets the port as port_state reads it, as a snapshot restores it,
+        # leaving the RAM under $00 and $01 alone.
+        def restore_port(ddr, out, floating)
+          @cpu_port.restore(ddr, out, floating)
+        end
+
+        def save_port_fields(out) = @cpu_port.save_fields(out, "port.")
+
+        def load_port_fields(input) = @cpu_port.load_fields(input, "port.")
+
+        def restored! = update_overlays!
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/c64/bus.rb

@@ -1,11 +1,12 @@
 # frozen_string_literal: true
 
-require "badline/c64/bus/saved_state"
+require "badline/c64/bus/keyed_state"
 require "badline/c64/bus/sid_slots"
 require "badline/c64/bus/extra_sids"
 require "badline/c64/bus/pla"
 require "badline/c64/bus/roms"
 require "badline/c64/bus/fittings"
+require "badline/c64/bus/debug_register"
 
 module Badline
   # Memory layout:
@@ -90,6 +91,7 @@ module Badline
         @cia1.on_port_b4_change { |high| @vic.lightpen_level(high) }
         @sid = Chips::SID.new(model: sid_model, pots: @control_ports)
         @sid_slots = []
+        @extra_sids = []
 
         @datasette = Drives::Datasette.new
         @datasette.on_flag { @cia1.flag! }

data/lib/badline/c64/cartridge/action_replay.rb

@@ -22,6 +22,10 @@ module Badline
         include Freezer
 
         CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
+
+        # Ultimax mode with the RAM at ROML and I/O 2 and the first bank at
+        # ROMH, as a freeze leaves the register.
+        FREEZE_CONTROL = 0x23
         IO2_PAGE = 0x1f00
 
         def connect(ram:, open_bus:)
@@ -59,25 +63,11 @@ module Badline
 
         def freeze!
           @active = true
-          @rom = bank(@rom_banks, 0)
-          select(:ultimax, @isolated, io2_ram: true)
+          control(FREEZE_CONTROL)
         end
 
         private
 
-        def save_mapper(out)
-          super
-          out.int(window_index(@rom, windows)).boolean(@active).boolean(@io2_ram).blob(@ram_data)
-        end
-
-        def load_mapper(input)
-          super
-          @rom = window_at(input.int, windows)
-          @active = input.boolean?
-          @io2_ram = input.boolean?
-          input.blob_into(@ram_data)
-        end
-
         def windows = [@through, @isolated, @contended, *@rom_banks, EMPTY_BANK]
 
         def io2_peek(addr)
@@ -85,6 +75,7 @@ module Badline
         end
 
         def control(value)
+          @control = value
           self.nmi = false if value.anybits?(0x40)
           @rom = bank(@rom_banks, (value >> 3) & 0x03)
           configure(value)

data/lib/badline/c64/cartridge/comal80.rb

@@ -37,6 +37,7 @@ module Badline
         def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
 
         def select(number, mode)
+          @bank = number
           @roml = bank(@roml_banks, number)
           @romh = bank(@romh_banks, number)
           self.mode = mode

data/lib/badline/c64/cartridge/dinamic.rb

@@ -12,13 +12,15 @@ module Badline
 
         def peek(addr)
           if addr < 0xde10
-            @roml = bank(@banks, addr & 0x0f)
+            @bank = addr & 0x0f
+            @roml = bank(@banks, @bank)
             changed!
           end
           open_bus(addr)
         end
 
         def reset
+          @bank = 0
           @roml = bank(@banks, 0)
           changed!
         end

data/lib/badline/c64/cartridge/easy_flash.rb

@@ -88,21 +88,6 @@ module Badline
           @romh = @high_flash.window(@bank * BANK_SIZE)
         end
 
-        def save_mapper(out)
-          out.int(@bank).int(@control).blob(@io_ram)
-          @low_flash.save_state(out)
-          @high_flash.save_state(out)
-        end
-
-        def load_mapper(input)
-          @bank = input.int
-          @control = input.int
-          input.blob_into(@io_ram)
-          @low_flash.load_state(input)
-          @high_flash.load_state(input)
-          map_bank
-        end
-
         def apply_control
           game = @control.nobits?(0x04) || @control.anybits?(0x01)
           exrom = @control.anybits?(0x02)

data/lib/badline/c64/cartridge/epyx_fastload.rb

@@ -57,14 +57,6 @@ module Badline
 
         private
 
-        def save_mapper(out)
-          out.int(@discharged_at)
-        end
-
-        def load_mapper(input)
-          @discharged_at = input.int
-        end
-
         def discharge!
           @discharged_at = @clock ? @clock.call : 0
         end

data/lib/badline/c64/cartridge/final_cartridge3.rb

@@ -61,21 +61,10 @@ module Badline
 
         private
 
-        def save_mapper(out)
-          super
-          out.boolean(@register_visible).boolean(@phi1_ultimax)
-        end
-
-        def load_mapper(input)
-          super
-          @io_bank = @roml
-          @register_visible = input.boolean?
-          @phi1_ultimax = input.boolean?
-        end
-
         def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
 
         def select(number)
+          @bank = number
           @io_bank = @roml = bank(@roml_banks, number)
           @romh = bank(@romh_banks, number)
         end

data/lib/badline/c64/cartridge/flash.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require "badline/c64/cartridge/flash/saved_state"
-
 module Badline
   class C64
     class Cartridge
@@ -69,7 +67,9 @@ module Badline
           alias [] peek
         end
 
-        include SavedState
+        # The command states, which a snapshot names.
+        STATES = %i[read program_setup autoselect programming erase_window erasing suspended chip_erase
+                    program_error].freeze
 
         attr_reader :data, :state
         attr_writer :clock

data/lib/badline/c64/cartridge/fun_play.rb

@@ -10,7 +10,8 @@ module Badline
         def poke(addr, value)
           return if addr > 0xdeff
 
-          @roml = bank(@banks, self.class.bank_number(value))
+          @bank = self.class.bank_number(value)
+          @roml = bank(@banks, @bank)
           case value & 0xc6
           when 0x00 then self.mode = :rom8k
           when 0x86 then self.mode = :off

data/lib/badline/c64/cartridge/g_mod2.rb

@@ -48,18 +48,6 @@ module Badline
           changed!
         end
 
-        def save_mapper(out)
-          out.int(@bank).boolean(@flash_writes)
-          @flash.save_state(out)
-        end
-
-        def load_mapper(input)
-          @bank = input.int
-          @flash_writes = input.boolean?
-          @flash.load_state(input)
-          @roml = @flash.window(@bank * BANK_SIZE)
-        end
-
         def install_chips(chips)
           data = Array.new(BANKS * BANK_SIZE, 0xff)
           chips.each do |chip|

data/lib/badline/c64/cartridge/game_system.rb

@@ -27,7 +27,8 @@ module Badline
         private
 
         def select(addr)
-          @roml = bank(@banks, addr & 0x3f)
+          @bank = addr & 0x3f
+          @roml = bank(@banks, @bank)
           changed!
         end
 

data/lib/badline/c64/cartridge/geo_ram.rb

@@ -53,24 +53,8 @@ module Badline
           @block = @page = @window = 0
         end
 
-        # A GEO-RAM is built from its size alone.
-        def save_setup(out)
-          out.int(GEO_RAM_SETUP).int(@size)
-        end
-
         private
 
-        def save_mapper(out)
-          out.blob(@ram_data).int(@block).int(@page).int(@window)
-        end
-
-        def load_mapper(input)
-          input.blob_into(@ram_data)
-          @block = input.int
-          @page = input.int
-          @window = input.int
-        end
-
         def install_chips(_chips)
           @ram_data = Array.new(@size * 1024, 0)
           reset

data/lib/badline/c64/cartridge/kcs_power.rb

@@ -56,14 +56,6 @@ module Badline
 
         private
 
-        def save_mapper(out)
-          out.blob(@io_ram)
-        end
-
-        def load_mapper(input)
-          input.blob_into(@io_ram)
-        end
-
         def install_chips(chips)
           roml, romh = banks_from(chips)
           @roml = roml.first || EMPTY_BANK