badline 0.13.0 → 0.15.0

data/lib/badline/chips/vdc/painter.rb

@@ -56,18 +56,6 @@ module Badline
           [0, 0, shown.clamp(1, @width), (frame_lines - sync_lines).clamp(1, @height)]
         end
 
-        # The display's size and the window's start addresses. The display
-        # starts again cleared, to be painted while the VDC renders.
-        def save_state(out)
-          out.int(@width).int(@height)
-          @window.save_state(out)
-        end
-
-        def load_state(input)
-          resize(input.int, input.int)
-          @window.load_state(input)
-        end
-
         def clear_dirty_lines!
           @dirty_lines.fill(false)
         end

data/lib/badline/chips/vdc/raster.rb

@@ -30,22 +30,6 @@ module Badline
         # Outside the displayed rows, as status bit 5 reads.
         def vertical_blank? = @adjusting || @row >= @registers[6]
 
-        def save_state(out)
-          out.int(@frame).int(@row).int(@row_line).boolean(@adjusting).int(@frame_line).int(@frame_lines)
-          out.int(@sync_start).int(@sync_lines)
-        end
-
-        def load_state(input)
-          @frame = input.int
-          @row = input.int
-          @row_line = input.int
-          @adjusting = input.boolean?
-          @frame_line = input.int
-          @frame_lines = input.int
-          @sync_start = input.int
-          @sync_lines = input.int
-        end
-
         def end_line(render)
           paint_line if render
           @frame_line += 1

data/lib/badline/chips/vdc/window.rb

@@ -57,15 +57,6 @@ module Badline
           @attribute_start = (regs[20] << 8) | regs[21]
         end
 
-        def save_state(out)
-          out.int(@display_start).int(@attribute_start)
-        end
-
-        def load_state(input)
-          @display_start = input.int
-          @attribute_start = input.int
-        end
-
         def paint(line, row, row_line, frame)
           regs = @registers
           lay_out_cell

data/lib/badline/chips/vdc.rb

@@ -4,7 +4,7 @@ require "badline/chips/vdc/memory"
 require "badline/chips/vdc/window"
 require "badline/chips/vdc/painter"
 require "badline/chips/vdc/raster"
-require "badline/chips/vdc/saved_state"
+require "badline/chips/vdc/keyed_parts"
 
 module Badline
   module Chips
@@ -34,7 +34,6 @@ module Badline
     # fills or two per byte it copies.
     class VDC
       include Addressable
-      include SavedState
 
       STATUS_READY = 0x80
       STATUS_VBLANK = 0x20

data/lib/badline/chips/via/control_lines.rb

@@ -56,21 +56,6 @@ module Badline
 
         def active_c1_edge?(high) = high == @control.anybits?(0x01)
 
-        # The lines' levels and mode. Which flags they set, and whether reads
-        # handshake, are the port's wiring.
-        def save_state(out)
-          out.int(@control).boolean(@c1_high).boolean(@c2_high).boolean(@handshake_low).int(@pulse).boolean(@c2_output)
-        end
-
-        def load_state(input)
-          @control = input.int
-          @c1_high = input.boolean?
-          @c2_high = input.boolean?
-          @handshake_low = input.boolean?
-          @pulse = input.int
-          @c2_output = input.boolean?
-        end
-
         # Everything the lines hold, for comparing them at two points.
         def state = [@control, @c1_high, @c2_high, @handshake_low, @pulse, @c2_output]
 

data/lib/badline/chips/via/interrupt_register.rb

@@ -25,15 +25,6 @@ module Badline
           @enable = 0x00
         end
 
-        def save_state(out)
-          out.int(@flags).int(@enable)
-        end
-
-        def load_state(input)
-          @flags = input.int
-          @enable = input.int
-        end
-
         def set(bits)
           @flags |= bits
         end

data/lib/badline/chips/via/keyed_parts.rb

@@ -0,0 +1,163 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VIA
+      class Timer1
+        # Timer 1's fields in a keyed snapshot module, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}latch", @latch).bool("#{prefix}hold", @hold)
+            out.bool("#{prefix}reload", @reload).bool("#{prefix}armed", @armed).bool("#{prefix}pb7", @pb7)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.word("#{prefix}counter", @counter)
+            @latch = input.word("#{prefix}latch", @latch)
+            @hold = input.bool("#{prefix}hold", @hold)
+            @reload = input.bool("#{prefix}reload", @reload)
+            @armed = input.bool("#{prefix}armed", @armed)
+            @pb7 = input.bool("#{prefix}pb7", @pb7)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Timer2
+        # Timer 2's fields in a keyed snapshot module, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}latch_low", @latch_low).bool("#{prefix}hold", @hold)
+            out.bool("#{prefix}low_reload", @low_reload).bool("#{prefix}armed", @armed)
+            out.bool("#{prefix}low_underflowed", @low_underflowed).bool("#{prefix}count_pulses", @count_pulses)
+            out.bool("#{prefix}counting_pulses", @counting_pulses)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.word("#{prefix}counter", @counter)
+            @latch_low = input.byte("#{prefix}latch_low", @latch_low)
+            @hold = input.bool("#{prefix}hold", @hold)
+            @low_reload = input.bool("#{prefix}low_reload", @low_reload)
+            @armed = input.bool("#{prefix}armed", @armed)
+            @low_underflowed = input.bool("#{prefix}low_underflowed", @low_underflowed)
+            @count_pulses = input.bool("#{prefix}count_pulses", @count_pulses)
+            @counting_pulses = input.bool("#{prefix}counting_pulses", @counting_pulses)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class ShiftRegister
+        # The shift register's fields in a keyed snapshot module, under
+        # `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}mode", @mode).int("#{prefix}data", @data).int("#{prefix}bits", @bits)
+            out.int("#{prefix}delay", @delay).bool("#{prefix}clock", @clock).bool("#{prefix}cb2", @cb2)
+            out.bool("#{prefix}cb2_input", @cb2_input)
+          end
+
+          def load_fields(input, prefix)
+            @mode = input.masked("#{prefix}mode", @mode, 0x07)
+            @data = input.byte("#{prefix}data", @data)
+            @bits = input.int("#{prefix}bits", @bits)
+            @delay = input.int("#{prefix}delay", @delay)
+            @clock = input.bool("#{prefix}clock", @clock)
+            @cb2 = input.bool("#{prefix}cb2", @cb2)
+            @cb2_input = input.bool("#{prefix}cb2_input", @cb2_input)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class InterruptRegister
+        # The flags and the enable mask, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}flags", @flags).int("#{prefix}enable", @enable)
+          end
+
+          def load_fields(input, prefix)
+            @flags = input.masked("#{prefix}flags", @flags, 0x7f)
+            @enable = input.masked("#{prefix}enable", @enable, 0x7f)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class ControlLines
+        # A pair of control lines' fields, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}control", @control).bool("#{prefix}c1_high", @c1_high).bool("#{prefix}c2_high", @c2_high)
+            out.bool("#{prefix}handshake_low", @handshake_low).int("#{prefix}pulse", @pulse)
+            out.bool("#{prefix}c2_output", @c2_output)
+          end
+
+          def load_fields(input, prefix)
+            @control = input.masked("#{prefix}control", @control, 0x0f)
+            @c1_high = input.bool("#{prefix}c1_high", @c1_high)
+            @c2_high = input.bool("#{prefix}c2_high", @c2_high)
+            @handshake_low = input.bool("#{prefix}handshake_low", @handshake_low)
+            @pulse = input.int("#{prefix}pulse", @pulse)
+            @c2_output = input.bool("#{prefix}c2_output", @c2_output)
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The VIA's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers and PB6, and its parts under t1., t2., sr., ifr., ca. and
+      # cb. Whether the shift register clocks off timer 2 comes from the
+      # ACR on load. The peripheral restores its own state.
+      module KeyedState
+        def save_fields(out)
+          out.int("ora", @ora).int("orb", @orb).int("ddra", @ddra).int("ddrb", @ddrb).int("latch_a", @latch_a)
+          out.int("latch_b", @latch_b).int("acr", @acr).int("pcr", @pcr).bool("pb6_high", @pb6_high)
+          @t1.save_fields(out, "t1.")
+          @t2.save_fields(out, "t2.")
+          @shift_register.save_fields(out, "sr.")
+          @ifr.save_fields(out, "ifr.")
+          @ca.save_fields(out, "ca.")
+          @cb.save_fields(out, "cb.")
+          out
+        end
+
+        def load_fields(input)
+          @ora = input.byte("ora", @ora)
+          @orb = input.byte("orb", @orb)
+          @ddra = input.byte("ddra", @ddra)
+          @ddrb = input.byte("ddrb", @ddrb)
+          @latch_a = input.byte("latch_a", @latch_a)
+          @latch_b = input.byte("latch_b", @latch_b)
+          @acr = input.byte("acr", @acr)
+          @pcr = input.byte("pcr", @pcr)
+          @pb6_high = input.bool("pb6_high", @pb6_high)
+          load_part_fields(input)
+        end
+
+        def restored!
+          @sr_uses_t2 = [1, 4, 5].include?((@acr >> 2) & 0x07)
+        end
+
+        private
+
+        def load_part_fields(input)
+          @t1.load_fields(input, "t1.")
+          @t2.load_fields(input, "t2.")
+          @shift_register.load_fields(input, "sr.")
+          @ifr.load_fields(input, "ifr.")
+          @ca.load_fields(input, "ca.")
+          @cb.load_fields(input, "cb.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/via/shift_register.rb

@@ -81,20 +81,6 @@ module Badline
         # changes it from cycle to cycle.
         def clocking? = @bits.nonzero? && internal_clock?
 
-        def save_state(out)
-          out.int(@mode).int(@data).int(@bits).int(@delay).boolean(@clock).boolean(@cb2).boolean(@cb2_input)
-        end
-
-        def load_state(input)
-          @mode = input.int
-          @data = input.int
-          @bits = input.int
-          @delay = input.int
-          @clock = input.boolean?
-          @cb2 = input.boolean?
-          @cb2_input = input.boolean?
-        end
-
         # Everything the register holds, for comparing it at two points.
         def state = [@mode, @data, @bits, @delay, @clock, @cb2, @cb2_input]
 

data/lib/badline/chips/via/timer1.rb

@@ -93,19 +93,6 @@ module Badline
           @counter = @reload ? 0xffff : @latch - phase + 1
         end
 
-        def save_state(out)
-          out.int(@counter).int(@latch).boolean(@hold).boolean(@reload).boolean(@armed).boolean(@pb7)
-        end
-
-        def load_state(input)
-          @counter = input.int
-          @latch = input.int
-          @hold = input.boolean?
-          @reload = input.boolean?
-          @armed = input.boolean?
-          @pb7 = input.boolean?
-        end
-
         # What the counter and PB7 don't hold, for comparing the timer at two
         # points.
         def state = [@latch, @armed]

data/lib/badline/chips/via/timer2.rb

@@ -85,24 +85,6 @@ module Badline
           @low_underflowed = @counter.allbits?(0xff)
         end
 
-        def save_state(out)
-          out.int(@counter).int(@latch_low)
-          [@hold, @low_reload, @armed, @low_underflowed, @count_pulses, @counting_pulses].each do |flag|
-            out.boolean(flag)
-          end
-        end
-
-        def load_state(input)
-          @counter = input.int
-          @latch_low = input.int
-          @hold = input.boolean?
-          @low_reload = input.boolean?
-          @armed = input.boolean?
-          @low_underflowed = input.boolean?
-          @count_pulses = input.boolean?
-          @counting_pulses = input.boolean?
-        end
-
         # What the counter and the low byte's underflow don't hold, for
         # comparing the timer at two points.
         def state = [@latch_low, @armed, @hold, @low_reload, @count_pulses, @counting_pulses]

data/lib/badline/chips/via.rb

@@ -4,9 +4,9 @@ require "badline/chips/via/control_lines"
 require "badline/chips/via/fast_forward"
 require "badline/chips/via/interrupt_register"
 require "badline/chips/via/shift_register"
-require "badline/chips/via/saved_state"
 require "badline/chips/via/timer1"
 require "badline/chips/via/timer2"
+require "badline/chips/via/keyed_parts"
 
 module Badline
   module Chips
@@ -20,7 +20,6 @@ module Badline
     class VIA
       include Addressable
       include FastForward
-      include SavedState
 
       attr_reader :start, :peripheral, :shift_register, :acr, :pcr
 

data/lib/badline/chips/vic/border_mask.rb

@@ -28,16 +28,6 @@ module Badline
           @groups.fill(FULL)
         end
 
-        def save_state(out)
-          out.ints(@groups).booleans(@mask).blob(@snapshot)
-        end
-
-        def load_state(input)
-          input.ints_into(@groups)
-          input.booleans_into(@mask)
-          input.blob_into(@snapshot)
-        end
-
         def at?(pixel_x)
           case @groups[pixel_x >> 3]
           when FULL then true

data/lib/badline/chips/vic/collisions.rb

@@ -37,17 +37,6 @@ module Badline
           @cleared_data = 0
         end
 
-        def save_state(out)
-          out.blob(@hits).int(@folded).int(@cleared_sprite).int(@cleared_data)
-        end
-
-        def load_state(input)
-          input.blob_into(@hits)
-          @folded = input.int
-          @cleared_sprite = input.int
-          @cleared_data = input.int
-        end
-
         def start_line
           @folded = 0
           @cleared_sprite = carry(@cleared_sprite)

data/lib/badline/chips/vic/color_patches.rb

@@ -18,17 +18,6 @@ module Badline
 
         def clear = @patches.clear
 
-        # Each patch as its four numbers: the boundary pixel, the register,
-        # the old colour and the new.
-        def save_state(out)
-          out.int(@patches.length)
-          @patches.each { |patch| out.ints(patch) }
-        end
-
-        def load_state(input)
-          @patches.replace(Array.new(input.int) { input.ints })
-        end
-
         def log(reg, old, value, boundary_x)
           @patches << [boundary_x, reg, @grey_dots ? GREY_DOT : old & 0x0f, value & 0x0f]
         end

data/lib/badline/chips/vic/display_state.rb

@@ -79,25 +79,6 @@ module Badline
           @matched && column >= FETCH_FIRST && column <= DMA_LAST
         end
 
-        def save_state(out)
-          out.int(@vc_base).int(@vc).int(@vmli).int(@rc).boolean(@display).boolean(@bad_lines_enabled)
-          out.boolean(@matched).optional_int(@ba).int(@line_bits).boolean(@den_line).boolean(@in_window)
-        end
-
-        def load_state(input)
-          @vc_base = input.int
-          @vc = input.int
-          @vmli = input.int
-          @rc = input.int
-          @display = input.boolean?
-          @bad_lines_enabled = input.boolean?
-          @matched = input.boolean?
-          @ba = input.optional_int
-          @line_bits = input.int
-          @den_line = input.boolean?
-          @in_window = input.boolean?
-        end
-
         def new_frame
           @vc_base = 0
           @bad_lines_enabled = false

data/lib/badline/chips/vic/graphics_shifter.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require "badline/chips/vic/graphics_shifter/saved_state"
-
 module Badline
   module Chips
     class VIC
@@ -26,8 +24,6 @@ module Badline
       # invalid mode, it is still black into hi-res text, and so is a
       # background pixel into multicolour bitmap.
       class GraphicsShifter
-        include SavedState
-
         ECM = 0b100
         ECM_BMM = 0b110
         MULTICOLOR_BITMAP = 0b011