badline 0.13.0 → 0.15.0

data/lib/badline/chips/cia/keyed_parts.rb

@@ -0,0 +1,213 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CIA
+      class Timer
+        # A timer's fields in a keyed snapshot module (Snapshot::Keyed),
+        # under `prefix`: the counter, the latch and the pipeline between
+        # them. The fast-path flags are worked out again on load.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}counter", @counter).int("#{prefix}latch", @latch).int("#{prefix}pipe", @pipe)
+            out.int("#{prefix}load_delay", @load_delay).bool("#{prefix}reload", @reload)
+            out.bool("#{prefix}underflowed", @underflowed).int("#{prefix}oneshot_linger", @oneshot_linger)
+            out.bool("#{prefix}toggle", @toggle)
+          end
+
+          def load_fields(input, prefix)
+            @counter = input.word("#{prefix}counter", @counter)
+            @latch = input.word("#{prefix}latch", @latch)
+            @pipe = input.masked("#{prefix}pipe", @pipe, 0b11)
+            @load_delay = input.int("#{prefix}load_delay", @load_delay)
+            @reload = input.bool("#{prefix}reload", @reload)
+            @underflowed = input.bool("#{prefix}underflowed", @underflowed)
+            @oneshot_linger = input.int("#{prefix}oneshot_linger", @oneshot_linger)
+            @toggle = input.bool("#{prefix}toggle", @toggle)
+          end
+
+          def restored! = settle
+        end
+
+        include KeyedState
+      end
+
+      class InterruptRegister
+        # The interrupt register's fields in a keyed snapshot module, under
+        # `prefix`: the mask, the flags, an assert on its way and the reads
+        # whose acknowledge is still landing.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}mask", @mask.value).int("#{prefix}status", @status.value)
+            out.int("#{prefix}pending", @pending)
+            out.optional_int("#{prefix}read", @read).optional_int("#{prefix}read_last_cycle", @read_last_cycle)
+            out.optional_int("#{prefix}read_two_cycles_ago", @read_two_cycles_ago)
+            out.bool("#{prefix}timer_b_bug", @timer_b_bug)
+          end
+
+          def load_fields(input, prefix)
+            @mask.value = input.byte("#{prefix}mask", @mask.value)
+            @status.value = input.byte("#{prefix}status", @status.value)
+            @pending = input.int("#{prefix}pending", @pending)
+            @read = input.optional_int("#{prefix}read")
+            @read_last_cycle = input.optional_int("#{prefix}read_last_cycle")
+            @read_two_cycles_ago = input.optional_int("#{prefix}read_two_cycles_ago")
+            @timer_b_bug = input.bool("#{prefix}timer_b_bug", @timer_b_bug)
+          end
+
+          # Quiet when nothing is due and no read is recent enough to matter.
+          def restored!
+            @quiet = @pending.zero? && @read.nil? && @read_last_cycle.nil? && @read_two_cycles_ago.nil?
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Serial
+        # The serial port's fields in a keyed snapshot module, under
+        # `prefix`: the registers, the bit count, the delay lines, the CNT
+        # and SP levels, and whether the next cycle can be skipped, which
+        # can lag what the delay lines show by a cycle.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}data", @data).int("#{prefix}shift", @shift).int("#{prefix}steps", @steps)
+            out.optional_int("#{prefix}empty_in", @empty_in).optional_int("#{prefix}busy_in", @busy_in)
+            out.bool("#{prefix}busy", @busy).bool("#{prefix}abandoned", @abandoned)
+            out.optional_int("#{prefix}pending", @pending).bool("#{prefix}underflow_high", @underflow_high)
+            out.bool("#{prefix}in_flight", @in_flight).int("#{prefix}flight_up", @flight_up)
+            out.int("#{prefix}flight_down", @flight_down).bool("#{prefix}cnt", @cnt).bool("#{prefix}cnt_in", @cnt_in)
+            out.bool("#{prefix}sp_in", @sp_in).bool("#{prefix}sp_out", @sp_out).bool("#{prefix}idle", @idle)
+          end
+
+          def load_fields(input, prefix)
+            @data = input.byte("#{prefix}data", @data)
+            @shift = input.byte("#{prefix}shift", @shift)
+            @steps = input.int("#{prefix}steps", @steps)
+            @empty_in = input.optional_int("#{prefix}empty_in")
+            @busy_in = input.optional_int("#{prefix}busy_in")
+            @busy = input.bool("#{prefix}busy", @busy)
+            @abandoned = input.bool("#{prefix}abandoned", @abandoned)
+            @pending = input.optional_int("#{prefix}pending")
+            load_line_fields(input, prefix)
+          end
+
+          def restored! = nil
+
+          private
+
+          def load_line_fields(input, prefix)
+            @underflow_high = input.bool("#{prefix}underflow_high", @underflow_high)
+            @in_flight = input.bool("#{prefix}in_flight", @in_flight)
+            @flight_up = input.int("#{prefix}flight_up", @flight_up)
+            @flight_down = input.int("#{prefix}flight_down", @flight_down)
+            @cnt = input.bool("#{prefix}cnt", @cnt)
+            @cnt_in = input.bool("#{prefix}cnt_in", @cnt_in)
+            @sp_in = input.bool("#{prefix}sp_in", @sp_in)
+            @sp_out = input.bool("#{prefix}sp_out", @sp_out)
+            @idle = input.bool("#{prefix}idle", @idle)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class TimeOfDay
+        # The TOD clock's fields in a keyed snapshot module, under `prefix`:
+        # the clock, the alarm and a latched read field by field, the
+        # pulses towards the next tenth, and the mains divider's phase in
+        # cycle·Hz (it reaches the clock rate when a pulse arrives). The
+        # 50/60 Hz divider comes from CRA bit 7 on load.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}mains_phase", @accumulator).int("#{prefix}pulses", @pulses)
+            out.bool("#{prefix}stopped", @stopped).bool("#{prefix}alarm_pending", @alarm_pending)
+            FIELDS.each do |field|
+              out.int("#{prefix}clock.#{field}", @clock[field]).int("#{prefix}alarm.#{field}", @alarm[field])
+            end
+            latch = @latch
+            FIELDS.each { |field| out.int("#{prefix}latch.#{field}", latch[field]) } if latch
+          end
+
+          def load_fields(input, prefix)
+            @accumulator = input.int("#{prefix}mains_phase", @accumulator)
+            @pulses = input.int("#{prefix}pulses", @pulses)
+            @stopped = input.bool("#{prefix}stopped", @stopped)
+            @alarm_pending = input.bool("#{prefix}alarm_pending", @alarm_pending)
+            FIELDS.each do |field|
+              @clock[field] = input.byte("#{prefix}clock.#{field}", @clock[field])
+              @alarm[field] = input.byte("#{prefix}alarm.#{field}", @alarm[field])
+            end
+            load_latch_fields(input, prefix)
+          end
+
+          def restored!(fifty_hz)
+            self.fifty_hz = fifty_hz
+          end
+
+          private
+
+          def load_latch_fields(input, prefix)
+            return @latch = nil if input.optional_int("#{prefix}latch.hours").nil?
+
+            @latch = FIELDS.to_h { |field| [field, input.byte("#{prefix}latch.#{field}", 0)] }
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The CIA's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # ports, the control registers, the PB4 and CNT levels, and its parts
+      # under ta., tb., icr., sdr. and tod.
+      module KeyedState
+        def save_fields(out)
+          out.int("pra", @data_port_a).int("prb", @data_port_b).int("ddra", @data_dir_a).int("ddrb", @data_dir_b)
+          out.int("cra", @control_a.value).int("crb", @control_b.value)
+          out.bool("pb4_high", @port_b4_high).bool("pb4_driven_high", @port_b4_driven_high)
+          out.bool("cnt_high", @cnt_high).bool("cnt_rise", @cnt_rise)
+          @ta.save_fields(out, "ta.")
+          @tb.save_fields(out, "tb.")
+          @icr.save_fields(out, "icr.")
+          @serial.save_fields(out, "sdr.")
+          @tod.save_fields(out, "tod.")
+          out
+        end
+
+        def load_fields(input)
+          @data_port_a = input.byte("pra", @data_port_a)
+          @data_port_b = input.byte("prb", @data_port_b)
+          @data_dir_a = input.byte("ddra", @data_dir_a)
+          @data_dir_b = input.byte("ddrb", @data_dir_b)
+          @control_a.value = input.byte("cra", @control_a.value)
+          @control_b.value = input.byte("crb", @control_b.value)
+          @port_b4_high = input.bool("pb4_high", @port_b4_high)
+          @port_b4_driven_high = input.bool("pb4_driven_high", @port_b4_driven_high)
+          @cnt_high = input.bool("cnt_high", @cnt_high)
+          @cnt_rise = input.bool("cnt_rise", @cnt_rise)
+          load_part_fields(input)
+        end
+
+        def restored!
+          @ta.restored!
+          @tb.restored!
+          @icr.restored!
+          @serial.restored!
+          @tod.restored!(@control_a.clock_frequency?)
+        end
+
+        private
+
+        def load_part_fields(input)
+          @ta.load_fields(input, "ta.")
+          @tb.load_fields(input, "tb.")
+          @icr.load_fields(input, "icr.")
+          @serial.load_fields(input, "sdr.")
+          @tod.load_fields(input, "tod.")
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/chips/cia/serial.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require "badline/chips/cia/serial/saved_state"
-
 module Badline
   module Chips
     class CIA
@@ -18,8 +16,6 @@ module Badline
       # rather than waiting for the sixteenth underflow, and a byte written
       # from that point on goes out on the next one.
       class Serial
-        include SavedState
-
         BITS = 8
 
         # A byte written to the data register reaches the shift register one

data/lib/badline/chips/cia/time_of_day.rb

@@ -32,28 +32,6 @@ module Badline
           @match = enabled ? 4 : 5
         end
 
-        # The clock and the alarm, field by field in FIELDS order, the latch,
-        # and the divider's phase.
-        def save_state(out)
-          out.int(@accumulator).int(@pulses).int(@match).boolean(@stopped).boolean(@alarm_pending)
-          FIELDS.each { |field| out.int(@clock[field]).int(@alarm[field]) }
-          out.boolean(!@latch.nil?)
-          FIELDS.each { |field| out.int(@latch[field]) } if @latch
-        end
-
-        def load_state(input)
-          @accumulator = input.int
-          @pulses = input.int
-          @match = input.int
-          @stopped = input.boolean?
-          @alarm_pending = input.boolean?
-          FIELDS.each do |field|
-            @clock[field] = input.int
-            @alarm[field] = input.int
-          end
-          @latch = input.boolean? ? FIELDS.to_h { |field| [field, input.int] } : nil
-        end
-
         # Whether the clock is stopped, or gets no pulses on its pin, with no
         # alarm to raise, so its cycles move only the divider's phase.
         def quiet? = (@stopped || @mains_hz.zero?) && !@alarm_pending

data/lib/badline/chips/cia/timer.rb

@@ -69,26 +69,6 @@ module Badline
           settle
         end
 
-        # The counter, the latch and the pipeline between them. The control
-        # register is the CIA's to save.
-        def save_state(out)
-          out.int(@counter).int(@latch).int(@pipe).int(@load_delay).boolean(@reload).boolean(@underflowed)
-          out.int(@oneshot_linger).boolean(@toggle).boolean(@settled).boolean(@empty)
-        end
-
-        def load_state(input)
-          @counter = input.int
-          @latch = input.int
-          @pipe = input.int
-          @load_delay = input.int
-          @reload = input.boolean?
-          @underflowed = input.boolean?
-          @oneshot_linger = input.int
-          @toggle = input.boolean?
-          @settled = input.boolean?
-          @empty = input.boolean?
-        end
-
         def write_control(value)
           @toggle = true if value.anybits?(0x01) && !started?
           @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)

data/lib/badline/chips/cia.rb

@@ -1,17 +1,17 @@
 # frozen_string_literal: true
 
+require "badline/chips/cia/time_of_day"
 require "badline/chips/cia/interrupt_register"
 require "badline/chips/cia/serial"
 require "badline/chips/cia/timer"
-require "badline/chips/cia/saved_state"
 require "badline/chips/cia/fast_forward"
+require "badline/chips/cia/keyed_parts"
 
 module Badline
   module Chips
     # CIA (Complex Interface Adapter) chip
     class CIA
       include Addressable
-      include SavedState
       include FastForward
 
       # The original NMOS 6526 of the breadbin C64, and the HMOS 6526A of the

data/lib/badline/chips/cpu/core.rb

@@ -5,7 +5,7 @@ require "badline/chips/cpu/addressing"
 require "badline/chips/cpu/operations"
 require "badline/chips/cpu/stack_operations"
 require "badline/chips/cpu/boundary"
-require "badline/chips/cpu/saved_state"
+require "badline/chips/cpu/keyed_state"
 
 module Badline
   module Chips
@@ -23,7 +23,7 @@ module Badline
         include Operations
         include StackOperations
         include Boundary
-        include SavedState
+        include KeyedState
 
         attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write
         attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y, :nmi, :irq
@@ -67,6 +67,22 @@ module Badline
           end_sequence
         end
 
+        # Drops the instruction or interrupt sequence in flight and the
+        # interrupt lines' pipeline, so the next cycle fetches an opcode at the
+        # program counter, and sets the cycle count. A snapshot from VICE,
+        # taken between instructions, restores through here.
+        def resume(cycles)
+          @irq_sample = @irq_pending = false
+          @nmi_sample = @nmi_pending = false
+          @skip_poll = false
+          @interrupt = nil
+          @brk = false
+          @stalled_at = nil
+          @cycles = cycles
+          end_sequence
+          @pending_write = false
+        end
+
         def p
           status.value
         end

data/lib/badline/chips/cpu/keyed_state.rb

@@ -0,0 +1,177 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # Where a CPU caught inside an instruction is, as a snapshot names it:
+      # an opcode's instruction, an IRQ or NMI sequence, or jammed.
+      POSITIONS = %w[boundary op interrupt jam].freeze
+
+      # The CPU's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers, the interrupt lines' pipeline, the counts and, inside an
+      # instruction, where it is in hardware terms (pos.*), rather than as
+      # the microcode lays it out.
+      module KeyedState
+        def save_fields(out)
+          out.int("pc", @program_counter).int("sp", @stack_pointer).int("a", @a).int("x", @x).int("y", @y)
+          out.int("p", @status.value).bool("nmi", @nmi).bool("so_high", @so_high)
+          out.bool("irq.sample", @irq_sample).bool("irq.pending", @irq_pending).bool("irq.boundary", @boundary_irq)
+          out.bool("nmi.sample", @nmi_sample).bool("nmi.pending", @nmi_pending).bool("nmi.boundary", @boundary_nmi)
+          out.bool("skip_poll", @skip_poll).optional_int("stalled", stalled_ago)
+          out.int("cycles", @cycles).int("instructions", @instructions)
+          save_position(out) unless boundary?
+          out
+        end
+
+        def load_fields(input)
+          @program_counter = input.word("pc", @program_counter)
+          @stack_pointer = input.byte("sp", @stack_pointer)
+          @a = input.byte("a", @a)
+          @x = input.byte("x", @x)
+          @y = input.byte("y", @y)
+          @status.value = input.byte("p", @status.value)
+          load_lines(input)
+          @cycles = input.int("cycles", @cycles)
+          @instructions = input.int("instructions", @instructions)
+          stalled = input.optional_int("stalled")
+          @stalled_at = stalled.nil? ? nil : @cycles - stalled
+          load_position(input)
+        end
+
+        # What the fields leave to be worked out: whether the next step
+        # writes.
+        def restored!
+          @pending_write = @writes[@index]
+        end
+
+        private
+
+        # Cycles since the CPU last stalled, when that was this cycle or the
+        # one before, the only ones an instruction looks back at.
+        def stalled_ago
+          stalled_at = @stalled_at
+          return nil if stalled_at.nil?
+
+          ago = @cycles - stalled_at
+          ago.between?(0, 1) ? ago : nil
+        end
+
+        def load_lines(input)
+          @nmi = input.bool("nmi", @nmi)
+          @so_high = input.bool("so_high", @so_high)
+          @irq_sample = input.bool("irq.sample", @irq_sample)
+          @irq_pending = input.bool("irq.pending", @irq_pending)
+          @boundary_irq = input.bool("irq.boundary", @boundary_irq)
+          @nmi_sample = input.bool("nmi.sample", @nmi_sample)
+          @nmi_pending = input.bool("nmi.pending", @nmi_pending)
+          @boundary_nmi = input.bool("nmi.boundary", @boundary_nmi)
+          @skip_poll = input.bool("skip_poll", @skip_poll)
+        end
+
+        def save_position(out)
+          source = plan_source
+          if source == JAMMED
+            out.text("pos.seq", "jam")
+            return
+          end
+
+          out.text("pos.seq", source == INTERRUPT ? "interrupt" : "op")
+          out.int("pos.op", source) unless source == INTERRUPT
+          out.int("pos.t", position_t(source)).bool("pos.crossed", @boundary_crossed)
+          out.bool("pos.branch_taken", @branch_taken == true).bool("pos.brk", @brk)
+          out.optional_int("pos.vector", @interrupt)
+          out.optional_int("pos.address", @address).optional_int("pos.dummy_address", @dummy_address)
+          out.optional_int("pos.value", @value).optional_int("pos.rmw", @rmw_result)
+          out.optional_int("pos.pointer", @pointer)
+        end
+
+        # The cycles of the instruction or sequence run so far, counting the
+        # opcode fetch as 1 and leaving out stalled cycles.
+        def position_t(source)
+          return @index if source == INTERRUPT
+
+          MICROCODE.fetch(source).t_at(@index, @boundary_crossed)
+        end
+
+        def load_position(input)
+          case input.choice("pos.seq", POSITIONS, "boundary")
+          when "op" then load_instruction(input)
+          when "interrupt" then load_interrupt(input)
+          when "jam" then load_jam
+          else load_boundary
+          end
+        end
+
+        def load_instruction(input)
+          micro = MICROCODE.fetch(input.byte("pos.op", 0xea))
+          use_plan(micro.plan, micro.writes)
+          @operation = micro.operation
+          @optional_dummy = micro.optional_dummy
+          @boundary_crossed = input.bool("pos.crossed", false)
+          @index = micro.index_at(input.int("pos.t", 1), @boundary_crossed).clamp(1, micro.plan.length - 1)
+          load_latches(input)
+        end
+
+        def load_interrupt(input)
+          use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
+          @boundary_crossed = input.bool("pos.crossed", false)
+          @index = input.int("pos.t", 1).clamp(1, INTERRUPT_PLAN.length - 1)
+          load_latches(input)
+        end
+
+        def load_jam
+          use_plan(JAMMED_PLAN, JAMMED_WRITES)
+          @index = 0
+          clear_latches
+        end
+
+        def load_boundary
+          use_plan(FETCH_PLAN, FETCH_WRITES)
+          @index = 0
+          clear_latches
+        end
+
+        def load_latches(input)
+          @branch_taken = input.bool("pos.branch_taken", false)
+          @brk = input.bool("pos.brk", false)
+          @interrupt = input.optional_int("pos.vector")
+          @address = input.optional_int("pos.address")
+          @dummy_address = input.optional_int("pos.dummy_address")
+          @value = input.optional_int("pos.value")
+          @rmw_result = input.optional_int("pos.rmw")
+          @pointer = input.optional_int("pos.pointer")
+        end
+
+        # The working registers no step reads before the next instruction
+        # sets them.
+        def clear_latches
+          @boundary_crossed = false
+          @branch_taken = false
+          @brk = false
+          @interrupt = nil
+          @address = nil
+          @dummy_address = nil
+          @value = nil
+          @rmw_result = nil
+          @pointer = nil
+        end
+
+        # Where the plan running comes from: an opcode's microcode, or FETCH,
+        # INTERRUPT or JAMMED below it.
+        def plan_source
+          return FETCH if @plan.equal?(FETCH_PLAN)
+          return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
+          return JAMMED if @plan.equal?(JAMMED_PLAN)
+
+          MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
+            MICROCODE.index { |micro| micro.plan.equal?(@plan) }
+        end
+
+        def use_plan(plan, writes)
+          @plan = plan
+          @writes = writes
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/microcode.rb

@@ -117,6 +117,22 @@ module Badline
           end.freeze
         end
 
+        # The plan step that follows `cycles` cycles of the instruction, counting
+        # the opcode fetch as 1: one further on once an indexed read has
+        # skipped its dummy read, which it does when the index add didn't
+        # cross a page.
+        def index_at(cycles, crossed) = skips_dummy?(cycles, crossed) ? cycles + 1 : cycles
+
+        # The cycles run before plan step `index`, as index_at counts them.
+        def t_at(index, crossed) = skips_dummy?(index - 1, crossed) ? index - 1 : index
+
+        def skips_dummy?(cycles, crossed)
+          return false unless optional_dummy && !crossed
+
+          dummy = plan.index(:op_idx_dummy)
+          !dummy.nil? && cycles >= dummy
+        end
+
         def self.write_mask(plan)
           plan.map { |step| WRITE_STEPS.include?(step) }.freeze
         end

data/lib/badline/chips/cpu/port.rb

@@ -6,7 +6,8 @@ module Badline
       # The I/O port of the 6510 and the 8502 at $00 (direction) and $01
       # (data). An input pin reads its pull-up, P4 reads the datasette's sense
       # line, and a pin without a pull-up holds the charge last driven onto
-      # it. P5 drives the datasette motor through an inverter: low runs it.
+      # it. P5 drives the datasette motor through an inverter: low runs it,
+      # and P3 drives its write line.
       #
       # The 6510 has pull-ups on P0-P2 and P4 and leaves P3, P6 and P7
       # floating. The 8502 adds a CAPS LOCK pin on P6, high while the key is
@@ -38,6 +39,7 @@ module Badline
           @floating = 0x00
           @change_handler = nil
           @status = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: input_value)
+          @datasette.write_level = @status.tape_out?
         end
 
         # Calls the block after every write to the port, for the bus to remap
@@ -68,19 +70,33 @@ module Badline
         end
 
         # Sets the registers and the charge, as a snapshot restores them, and
-        # drives the motor and calls the change handler as a write does.
+        # drives the datasette and calls the change handler as a write does.
         def restore(ddr, data, floating)
           load(ddr, data, floating)
           update
         end
 
         # Sets the registers and the charge, as a snapshot loads them, without
-        # driving the motor or calling the change handler.
+        # driving the datasette or calling the change handler. The write
+        # line takes P3's level without recording an edge.
         def load(ddr, data, floating)
           @ddr = ddr
           @data = data
           @floating = floating
           refresh
+          @datasette.write_level = @status.tape_out?
+        end
+
+        # The registers and the charge in a keyed snapshot module
+        # (Snapshot::Keyed), under `prefix`. What a read sees is worked out
+        # again on load, and the bus maps its banks afterwards.
+        def save_fields(out, prefix)
+          out.int("#{prefix}ddr", @ddr).int("#{prefix}data", @data).int("#{prefix}floating", @floating)
+        end
+
+        def load_fields(input, prefix)
+          load(input.byte("#{prefix}ddr", @ddr), input.byte("#{prefix}data", @data),
+               input.byte("#{prefix}floating", @floating))
         end
 
         # Holds CAPS LOCK down, or lets it up.
@@ -101,6 +117,7 @@ module Badline
           @floating = (@floating & ~driven) | (@data & driven)
           refresh
           @datasette.motor = !@status.tape_motor?
+          @datasette.write_line = @status.tape_out?
           @change_handler&.call
         end
 

data/lib/badline/chips/cpu.rb

@@ -1,5 +1,10 @@
 # frozen_string_literal: true
 
+require "badline/chips/cpu/port"
+require "badline/chips/cpu/instruction"
+require "badline/chips/cpu/instruction_set"
+require "badline/chips/cpu/interrupts"
+require "badline/chips/cpu/traps"
 require "badline/chips/cpu/core"
 
 module Badline

data/lib/badline/chips/sid/decimator.rb

@@ -23,17 +23,19 @@ module Badline
         # Cycles until the current window closes, counting the next one as 1.
         attr_reader :cycles_to_close
 
-        # How far the current window has got. The clock and the rate are the
+        # How far the current window has got, in a keyed snapshot module
+        # (Snapshot::Keyed) under `prefix`. The clock and the rate are the
         # host's.
-        def save_state(out)
-          out.int(@phase).int(@sum).int(@count).int(@cycles_to_close)
+        def save_fields(out, prefix)
+          out.int("#{prefix}phase", @phase).int("#{prefix}sum", @sum).int("#{prefix}count", @count)
+          out.int("#{prefix}cycles_to_close", @cycles_to_close)
         end
 
-        def load_state(input)
-          @phase = input.int
-          @sum = input.int
-          @count = input.int
-          @cycles_to_close = input.int
+        def load_fields(input, prefix)
+          @phase = input.int("#{prefix}phase", @phase)
+          @sum = input.int("#{prefix}sum", @sum)
+          @count = input.int("#{prefix}count", @count)
+          @cycles_to_close = input.int("#{prefix}cycles_to_close", @cycles_to_close)
         end
 
         # Returns the averaged sample when these cycles close a window, and

data/lib/badline/chips/sid/envelope.rb

@@ -1,7 +1,5 @@
 # frozen_string_literal: true
 
-require "badline/chips/sid/envelope/saved_state"
-
 module Badline
   module Chips
     class SID
@@ -28,11 +26,8 @@ module Badline
         EXPONENTIAL_PERIODS = { 0xff => 1, 0x5d => 2, 0x36 => 4, 0x1a => 8,
                                 0x0e => 16, 0x06 => 30, 0x00 => 1 }.freeze
 
-        # The states a snapshot names by index.
+        # The states, which VICE's SIDEXTENDED numbers by index.
         STATES = %i[attack decay_sustain release].freeze
-
-        include SavedState
-
         attr_reader :state, :counter, :env3
 
         def initialize