axi_tdl 0.2.0 → 0.2.5
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +46 -28
- data/.github/workflows/ruby.yml +1 -1
- data/.gitignore +2 -1
- data/.travis.yml +1 -0
- data/axi_tdl.gemspec +1 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +4 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
- metadata +14 -3
@@ -1,28 +1,9 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2022-07-10 11:21:37 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_top (
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input sys_clock,
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output logic[3:0] odata
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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//==========================================================================
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//-------- instance --------------------------------------------------------
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//==========================================================================
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//-------- expression ------------------------------------------------------
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`timescale 1ns/1ps
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module test_top();
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initial begin
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#(1us);
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$warning("Check TopModule.sim,please!!!");
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$stop;
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end
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2023-08-16 21:22:32 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_top_sim (
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input sys_clock,
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output logic[3:0] odata
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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//==========================================================================
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//-------- instance --------------------------------------------------------
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//==========================================================================
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//-------- expression ------------------------------------------------------
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2022-07-10 11:21:57 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_tttop (
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input global_sys_clk
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock_100M;
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logic rstn_100M;
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axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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simple_clock simple_clock_inst(
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/* input clock */.sys_clk (global_sys_clk ),
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/* output clock */.clock (clock_100M ),
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/* output reset */.rst_n (rstn_100M )
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);
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a_test_md a_test_md_inst(
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/* input clock */.clock (clock_100M ),
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/* input reset */.rst (~rstn_100M ),
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/* axi_stream_inf.master */.origin_inf (x_origin_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign x_origin_inf.axis_tvalid = 1'b0;
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assign x_origin_inf.axis_tdata = '0;
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assign x_origin_inf.axis_tlast = 1'b0;
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`timescale 1ns/1ps
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module test_tttop();
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initial begin
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#(1us);
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$warning("Check TopModule.sim,please!!!");
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$stop;
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end
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endmodule
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@@ -1,9 +1,40 @@
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-
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: 2023-08-16 21:22:16 +0800
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module test_tttop_sim (
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input global_sys_clk
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock_100M;
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logic rstn_100M;
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axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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simple_clock simple_clock_inst(
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/* input clock */.sys_clk (global_sys_clk ),
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/* output clock */.clock (clock_100M ),
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/* output reset */.rst_n (rstn_100M )
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);
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a_test_md a_test_md_inst(
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/* input clock */.clock (clock_100M ),
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/* input reset */.rst (~rstn_100M ),
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/* axi_stream_inf.master */.origin_inf (x_origin_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign x_origin_inf.axis_tvalid = 1'b0;
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assign x_origin_inf.axis_tdata = '0;
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assign x_origin_inf.axis_tlast = 1'b0;
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endmodule
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end
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end
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## Monkey 布丁,
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def force_name_copy(nstr)
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if nstr.to_s.eql?(inst_name.to_s)
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@copy_id ||= 0
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str = "#{nstr.to_s}_copy_#{@copy_id}"
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@copy_id += 1
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str
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else
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nstr.to_s
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end
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end
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def use_which_freq_when_copy(argv_clock,argv_origin)
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if argv_clock == @clock && @clock
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if @clock.respond_to? :freqM
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metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: axi_tdl
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version: !ruby/object:Gem::Version
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version: 0.2.
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version: 0.2.5
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platform: ruby
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authors:
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- Cook.Darwin
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autorequire:
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bindir: exe
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cert_chain: []
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date:
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date: 2023-08-16 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rake
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- lib/axi/AXI4/odata_pool_axi4_A1.sv
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- lib/axi/AXI4/odata_pool_axi4_A2.sv
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- lib/axi/AXI4/odata_pool_axi4_A3.sv
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- lib/axi/AXI4/odata_pool_axi4_A4.sv
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- lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv
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- lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv
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- lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv
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- lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv
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- lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv
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- lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv
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- lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv
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- lib/axi/AXI4/packet_merge/axi4_merge.sv
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- lib/axi/AXI4/packet_merge/axi4_merge_rd.sv
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- lib/axi/AXI4/packet_merge/axi4_merge_wr.sv
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- lib/axi/AXI_stream/gen_origin_axis.sv
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- lib/axi/AXI_stream/gen_origin_axis_A3.sv
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- lib/axi/AXI_stream/gen_simple_axis.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv
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- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv
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- lib/axi/AXI_stream/parse_big_field_table.sv
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- lib/axi/AXI_stream/parse_big_field_table_main.sv
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- lib/axi/AXI_stream/parse_big_field_table_mirror.sv
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- lib/axi/AXI_stream/parse_common_frame_table_A1.sv
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- lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv
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- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv
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- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv
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- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv
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- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv
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- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv
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- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv
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- lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv
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- lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv
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@@ -1340,7 +1351,7 @@ required_ruby_version: !ruby/object:Gem::Requirement
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required_rubygems_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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