axi_tdl 0.2.0 → 0.2.5

data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2022-07-10 11:21:57 +0800
+created: 2023-08-16 21:22:48 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/8_top_module/test_top.sv

@@ -1,28 +1,9 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-created: 2022-07-10 11:21:37 +0800
-madified:
-***********************************************/
-`timescale 1ns/1ps
-
-module test_top (
-    input             sys_clock,
-    output logic[3:0] odata
-);
-
-//==========================================================================
-//-------- define ----------------------------------------------------------
-
-
-//==========================================================================
-//-------- instance --------------------------------------------------------
-
-//==========================================================================
-//-------- expression ------------------------------------------------------
 
+`timescale 1ns/1ps
+module test_top();
+initial begin
+    #(1us);
+    $warning("Check TopModule.sim,please!!!");
+    $stop;
+end
 endmodule

data/lib/tdl/examples/8_top_module/test_top_sim.sv

@@ -1,9 +1,28 @@
-
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2023-08-16 21:22:32 +0800
+madified:
+***********************************************/
 `timescale 1ns/1ps
-module test_top_sim();
-initial begin
-    #(1us);
-    $warning("Check TopModule.sim,please!!!");
-    $stop;
-end
+
+module test_top_sim (
+    input             sys_clock,
+    output logic[3:0] odata
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+
+//==========================================================================
+//-------- instance --------------------------------------------------------
+
+//==========================================================================
+//-------- expression ------------------------------------------------------
+
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -1,40 +1,9 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-created: 2022-07-10 11:21:57 +0800
-madified:
-***********************************************/
-`timescale 1ns/1ps
-
-module test_tttop (
-    input global_sys_clk
-);
-
-//==========================================================================
-//-------- define ----------------------------------------------------------
-logic  clock_100M;
-logic  rstn_100M;
-axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
-//==========================================================================
-//-------- instance --------------------------------------------------------
-simple_clock simple_clock_inst(
-/* input clock  */.sys_clk (global_sys_clk ),
-/* output clock */.clock   (clock_100M     ),
-/* output reset */.rst_n   (rstn_100M      )
-);
-a_test_md a_test_md_inst(
-/* input clock           */.clock      (clock_100M   ),
-/* input reset           */.rst        (~rstn_100M   ),
-/* axi_stream_inf.master */.origin_inf (x_origin_inf )
-);
-//==========================================================================
-//-------- expression ------------------------------------------------------
-assign x_origin_inf.axis_tvalid = 1'b0;
-assign x_origin_inf.axis_tdata = '0;
-assign x_origin_inf.axis_tlast = 1'b0;
 
+`timescale 1ns/1ps
+module test_tttop();
+initial begin
+    #(1us);
+    $warning("Check TopModule.sim,please!!!");
+    $stop;
+end
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop_sim.sv

@@ -1,9 +1,40 @@
-
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2023-08-16 21:22:16 +0800
+madified:
+***********************************************/
 `timescale 1ns/1ps
-module test_tttop_sim();
-initial begin
-    #(1us);
-    $warning("Check TopModule.sim,please!!!");
-    $stop;
-end
+
+module test_tttop_sim (
+    input global_sys_clk
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock_100M;
+logic  rstn_100M;
+axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+simple_clock simple_clock_inst(
+/* input clock  */.sys_clk (global_sys_clk ),
+/* output clock */.clock   (clock_100M     ),
+/* output reset */.rst_n   (rstn_100M      )
+);
+a_test_md a_test_md_inst(
+/* input clock           */.clock      (clock_100M   ),
+/* input reset           */.rst        (~rstn_100M   ),
+/* axi_stream_inf.master */.origin_inf (x_origin_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
+
 endmodule

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -668,6 +668,20 @@ module TdlSpace
             end
         end
 
+        ## Monkey 布丁, 
+        def force_name_copy(nstr)
+            
+            if nstr.to_s.eql?(inst_name.to_s)
+                @copy_id ||= 0
+                str = "#{nstr.to_s}_copy_#{@copy_id}"
+                @copy_id += 1
+                str
+            else
+                nstr.to_s
+            end
+            
+        end
+
         def use_which_freq_when_copy(argv_clock,argv_origin)
             if argv_clock == @clock && @clock
                 if @clock.respond_to? :freqM

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.2.0
+  version: 0.2.5
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2022-07-17 00:00:00.000000000 Z
+date: 2023-08-16 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -131,10 +131,14 @@ files:
 - lib/axi/AXI4/odata_pool_axi4_A1.sv
 - lib/axi/AXI4/odata_pool_axi4_A2.sv
 - lib/axi/AXI4/odata_pool_axi4_A3.sv
+- lib/axi/AXI4/odata_pool_axi4_A4.sv
 - lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv
+- lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv
 - lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv
 - lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv
+- lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv
 - lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv
+- lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv
 - lib/axi/AXI4/packet_merge/axi4_merge.sv
 - lib/axi/AXI4/packet_merge/axi4_merge_rd.sv
 - lib/axi/AXI4/packet_merge/axi4_merge_wr.sv
@@ -306,12 +310,14 @@ files:
 - lib/axi/AXI_stream/gen_origin_axis.sv
 - lib/axi/AXI_stream/gen_origin_axis_A1.sv
 - lib/axi/AXI_stream/gen_origin_axis_A2.sv
+- lib/axi/AXI_stream/gen_origin_axis_A3.sv
 - lib/axi/AXI_stream/gen_simple_axis.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv
+- lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv
 - lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv
@@ -321,6 +327,8 @@ files:
 - lib/axi/AXI_stream/parse_big_field_table.sv
 - lib/axi/AXI_stream/parse_big_field_table_A1.sv
 - lib/axi/AXI_stream/parse_big_field_table_A2.sv
+- lib/axi/AXI_stream/parse_big_field_table_main.sv
+- lib/axi/AXI_stream/parse_big_field_table_mirror.sv
 - lib/axi/AXI_stream/parse_big_field_table_verb.sv
 - lib/axi/AXI_stream/parse_common_frame_table.sv
 - lib/axi/AXI_stream/parse_common_frame_table_A1.sv
@@ -351,6 +359,7 @@ files:
 - lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv
 - lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv
 - lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv
+- lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv
 - lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv
 - lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv
 - lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv
@@ -358,6 +367,8 @@ files:
 - lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv
 - lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv
 - lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv
+- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv
+- lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv
 - lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv
 - lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv
 - lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv
@@ -1340,7 +1351,7 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 2.5.0
+      version: 2.6.0
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="