axi_tdl 0.2.0 → 0.2.5

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 07d14bdc63e601755761b703ae0203852d824e1ffbb0cff1cd61e0c427325401
-  data.tar.gz: 94c7af9a7d499b545956f3f4363eb622aba5d78c67be914958867381764e43d6
+  metadata.gz: cbd04437f9a54f453a70249ea3800e0ad83b7afca7b2eb8aa4e968160a44b714
+  data.tar.gz: 4e0e182673271971834246838aa7f2d2735bf6c16ec8d02bf6cecacc63ef9f9d
 SHA512:
-  metadata.gz: ceee62403d3d7c232713c554600bc774edea66c5aeb059471ea2a1f3ce6f8a5e96826b5204d8ec3e5e825b192648573ac2f4b1c8aee6358e104c714fa2f5a97e
-  data.tar.gz: aa71d8cf174190ee50e8b2347509160b8890b963dbba84e25e2133dc90e7d25608b192dcb6d72ff22e799e714b672c665c24fdad6df7fb8bbc7c8f27e8aa70bf
+  metadata.gz: 756a91a926f7933d0b9f282bc10effc50f7505026b31b15ae4af55e0229bd515687fe30ba35b4d5593ba313655e46643e29089292456079475c7ac6baa9ea562
+  data.tar.gz: 5100e94f2d061d83cf6f0caae29401bfaefefa15bb5f911d6fbf9b84c5aba9bcb891bee496761b76c9e6b1627a57917d7a9e0ac60e4c549699ef475894c7dd3a

data/.github/workflows/gem-push.yml

@@ -1,6 +1,18 @@
+# This workflow uses actions that are not certified by GitHub.
+# They are provided by a third-party and are governed by
+# separate terms of service, privacy policy, and support
+# documentation.
+
+# GitHub recommends pinning actions to a commit SHA.
+# To get a newer version, you will need to update the SHA.
+# You can also reference a tag or branch, but the action may change without warning.
+
 name: Ruby Gem
 
 on:
+  # Manually publish
+  workflow_dispatch:
+  # Alternatively, publish whenever changes are merged to the `main` branch.
   push:
     branches: [ main ]
   pull_request:
@@ -10,35 +22,41 @@ jobs:
   build:
     name: Build + Publish
     runs-on: ubuntu-latest
+    permissions:
+      packages: write
+      contents: read
 
     steps:
-    - uses: actions/checkout@v2
-    - name: Set up Ruby 2.6
-      uses: actions/setup-ruby@v1
-      with:
-        ruby-version: 2.6.x
-
-    - name: Publish to GPR
-      run: |
-        mkdir -p $HOME/.gem
-        touch $HOME/.gem/credentials
-        chmod 0600 $HOME/.gem/credentials
-        printf -- "---\n:github: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
-        gem build *.gemspec
-        gem push --KEY github --host https://rubygems.pkg.github.com/${OWNER} *.gem
-      env:
-        GEM_HOST_API_KEY: "Bearer ${{secrets.GITHUB_TOKEN}}"
-        OWNER: ${{ github.repository_owner }}
-
-    - name: Publish to RubyGems
-      run: |
-        mkdir -p $HOME/.gem
-        touch $HOME/.gem/credentials
-        chmod 0600 $HOME/.gem/credentials
-        printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
-        gem build *.gemspec
-        gem push *.gem
-      env:
+      - uses: actions/checkout@v3
+      - name: Set up Ruby 2.6
+        uses: ruby/setup-ruby@477b21f02be01bcb8030d50f37cfec92bfa615b6
+        with:
+          ruby-version: 2.6
+      - run: bundle install
+
+      - name: Publish to GPR
+        run: |
+          mkdir -p $HOME/.gem
+          touch $HOME/.gem/credentials
+          chmod 0600 $HOME/.gem/credentials
+          printf -- "---\n:github: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
+          gem build *.gemspec
+          gem push --KEY github --host https://rubygems.pkg.github.com/${OWNER} *.gem
+        env:
+          GEM_HOST_API_KEY: "Bearer ${{secrets.GITHUB_TOKEN}}"
+          OWNER: ${{ github.repository_owner }}
+
+      - name: Publish to RubyGems
+        run: |
+          mkdir -p $HOME/.gem
+          touch $HOME/.gem/credentials
+          chmod 0600 $HOME/.gem/credentials
+          printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
+          gem build *.gemspec
+          gem push *.gem
+        env:
+          GEM_HOST_API_KEY: "${{secrets.RUBYGEMS_AUTH_TOKEN}}"
           GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
           RUBYGEMS_API_KEY: ${{secrets.RUBYGEMS_API_KEY}}
-          # RELEASE_COMMAND: rake release
+
+

data/.github/workflows/ruby.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        ruby-version: ['2.6', '2.7', '3.0']
+        ruby-version: ['2.6','2.7', '3.0']
 
     steps:
     - uses: actions/checkout@v2

data/.gitignore

@@ -9,4 +9,5 @@
 .rake_tasks~
 lib/tdl/auto_script/tmp/
 /*.gem
-Gemfile.lock
+Gemfile.lock
+bk*.yml

data/.travis.yml

@@ -4,6 +4,7 @@ before_install:
   
 rvm:
   - 2.6
+  - 2.7
   - 3.0
 
 script: rake test

data/axi_tdl.gemspec

@@ -15,7 +15,7 @@ Gem::Specification.new do |spec|
   spec.license       = "LGPL-2.1"
   spec.files         = Dir['lib/**/*']
   spec.require_paths = ["lib"]
-  spec.required_ruby_version = '>= 2.5.0'
+  spec.required_ruby_version = '>= 2.6.0'
   # Prevent pushing this gem to RubyGems.org. To allow pushes either set the 'allowed_push_host'
   # to allow pushing to a single host or delete this section to allow pushing to any host.
   if spec.respond_to?(:metadata)

data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv

@@ -109,8 +109,8 @@ axi4_partition_OD #(
     // .ADDR_STEP      (slaver_inf.DSIZE/(master_inf.DSIZE/8.0)  )
     // .ADDR_STEP      (4*slaver_inf.DSIZE/16.0  )
 )axi4_partition_inst(
-/*    axi_inf.slaver_inf */ .slaver_inf     (axi_inf_first_wc       ),
-/*    axi_inf.master_inf */ .master_inf     (axi_inf_pout           )
+/*    axi_inf.slaver_inf */ .slaver     (axi_inf_first_wc       ),
+/*    axi_inf.master_inf */ .master     (axi_inf_pout           )
 );
 
 axi4_data_convert_verb #(
@@ -133,9 +133,11 @@ end
 endgenerate
 
 
-axi4_packet_fifo_verb #(             //512
+// axi4_packet_fifo_verb #(             //512
+axi4_packet_fifo_B1 #(             //
     .PIPE       (PIPE   ),
     .DEPTH      (4      ),
+    .MAX_DATA_LEN   (1024*2),
     .SLAVER_MODE    (SLAVER_MODE ),    //
     .MASTER_MODE    (MASTER_MODE )   //
 )axi4_packet_fifo_inst(

data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv

@@ -12,7 +12,8 @@ madified:
 ***********************************************/
 `timescale 1ns/1ps
 module axi4_mix_interconnect_M2S #(
-    parameter NUM = 8
+    parameter NUM = 8,
+    parameter MASTER_IDSIZE = 8
 )(
     axi_inf.slaver slaver [NUM-1:0],
     axi_inf.master master
@@ -38,7 +39,8 @@ axi4_wr_interconnect_M2S_A1 #(     //axi4 dont support write burst out-of-order
 // );
 
 axi4_rd_mix_interconnect_M2S_A2 #(
-    .NUM    (NUM    )
+    .NUM            (NUM    ),
+    .MASTER_IDSIZE  (MASTER_IDSIZE)
 )axi4_rd_mix_interconnect_M2S_inst(
 /*    axi_inf.slaver_rd */  .slaver     (`slaver_vcs_cptRead ),      //[NUM-1:0],
 /*    axi_inf.master_rd */  .master     (`master_vcs_cptRead )

data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv

@@ -14,7 +14,8 @@ madified:
 ***********************************************/
 `timescale 1ns/1ps
 module axi4_rd_mix_interconnect_M2S_A2 #(
-    parameter NUM = 8
+    parameter NUM = 8,
+    parameter MASTER_IDSIZE = 8
 )(
     axi_inf.slaver_rd slaver [NUM-1:0],
     axi_inf.master_rd master
@@ -24,7 +25,8 @@ localparam NSIZE =  $clog2(NUM);
 import SystemPkg::*;
 
 // localparam LAZISE = slaver[0].IDSIZE;
-localparam LAZISE = master.IDSIZE - NSIZE;
+// localparam LAZISE = master.IDSIZE - NSIZE;
+localparam LAZISE = MASTER_IDSIZE - NSIZE;
 
 initial begin
     // assert(slaver[0].IDSIZE+NSIZE == master.IDSIZE)

data/lib/axi/AXI4/long_axis_to_axi4_wr.rb

@@ -2,6 +2,7 @@
 require_hdl "axis_length_split_with_addr.sv"
 require_hdl 'axi_stream_long_fifo_verb.sv'
 require_shdl 'axi4_wr_auxiliary_gen_without_resp','axis_valve_with_pipe'
+require_shdl 'independent_clock_fifo'
 
 TdlBuild.long_axis_to_axi4_wr(__dir__) do
     parameter.BYTE_DEPTH    8192*2

data/lib/axi/AXI4/odata_pool_axi4_A4.sv

@@ -0,0 +1,173 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.1.0 2017/9/18 
+    use axis out
+Version: VERA.2.0 ###### Tue Jan 7 09:47:51 CST 2020
+    data_inf_c replace valid ready
+Version: VERA.4.0 
+    Vision AXI PARAMETER
+creaded: 2017/3/1 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* axi4 = "true" *)
+module odata_pool_axi4_A4 #(
+    parameter   IDSIZE = 2,
+    parameter   ASIZE  = 32,
+    parameter   LSIZE  = 16
+)(
+    axi_stream_inf.master       out_axis,
+    data_inf_c.slaver           addr_size_inf,  //ADDR: 32 SIZE: 32
+    axi_inf.master_rd           axi_master
+);
+
+`include "define_macro.sv"
+
+logic           fifo_empty;
+logic           fifo_full;
+logic [31:0]    fifo_addr;
+logic [31:0]    fifo_size;
+logic           fifo_rd_en;
+
+independent_clock_fifo #(
+    .DEPTH      (4   ),
+    .DSIZE      (64  )
+)independent_clock_fifo_inst_req(
+/*  input                   */    .wr_clk     (addr_size_inf.clock      ),          
+/*  input                   */    .wr_rst_n   (addr_size_inf.rst_n      ),          
+/*  input                   */    .rd_clk     (axi_master.axi_aclk      ),          
+/*  input                   */    .rd_rst_n   (axi_master.axi_aresetn   ),          
+/*  input [DSIZE-1:0]       */    .wdata      (addr_size_inf.data       ),          
+/*  input                   */    .wr_en      (addr_size_inf.valid && addr_size_inf.ready   ),          
+/*  output logic[DSIZE-1:0] */    .rdata      ({fifo_addr,fifo_size}    ),          
+/*  input                   */    .rd_en      ((fifo_rd_en && !fifo_empty)  ),          
+/*  output logic            */    .empty      (fifo_empty               ),          
+/*  output logic            */    .full       (fifo_full                )      
+);
+
+assign  addr_size_inf.ready     = !fifo_full;
+
+initial begin
+    if(out_axis.DSIZE != axi_master.DSIZE)begin
+        $error("DATA POOL AXI4 DATA WIDTH ERROR DSIZE[%d]--axi_master.DSIZE[%d]",out_axis.DSIZE,axi_master.DSIZE);
+        $finish;
+    end
+    assert (axi_master.IDSIZE==IDSIZE) 
+    else   $error("axi_master.IDSIZE==IDSIZE");
+
+    assert (axi_master.ASIZE==ASIZE) 
+    else   $error("axi_master.ASIZE==ASIZE");
+
+    assert (axi_master.LSIZE==LSIZE) 
+    else   $error("axi_master.LSIZE==LSIZE");
+end
+
+axi_stream_inf #(.DSIZE(IDSIZE+ASIZE+LSIZE)) addr_len_inf     (.aclk(axi_master.axi_aclk),.aresetn(axi_master.axi_aresetn),.aclken(1'b1));
+
+logic [IDSIZE-1:0]           id;
+logic [ASIZE-1:0]            addr;
+logic [LSIZE-1:0]            length;
+logic                                   force_align_status;
+
+assign  id      = '0;
+assign  addr    = fifo_addr[ASIZE-1:0];
+assign  length  = fifo_size[LSIZE:0];
+
+assign addr_len_inf.axis_tdata  = {id,addr,length};
+
+`VCS_AXI4_CPT_LT(axi_master,master_rd,master_rd_aux,)
+axi4_rd_auxiliary_gen_A1 axi4_rd_auxiliary_gen_inst(
+/*    axi_stream_inf.slaver     */  .id_add_len_in  (addr_len_inf   ),      //tlast is not necessary
+/*    axi_inf.master_rd_aux     */  .axi_rd_aux     (`axi_master_vcs_cpt            )
+);
+
+assign  addr_len_inf.axis_tvalid    = !fifo_empty && (fifo_size[LSIZE:0]!='0);
+assign  fifo_rd_en                  = addr_len_inf.axis_tready;
+
+//--->> FIFO
+
+logic   axis_fifo_empty;
+logic   axis_fifo_full;
+logic   axis_fifo_rd_en;
+logic [out_axis.DSIZE+1-1:0]    axis_fifo_rd_data;
+
+//--->> forece rd_en <<---------------------------
+
+logic   force_rd_en;
+
+logic   cmded_empty;
+
+independent_clock_fifo #(
+    .DEPTH  (4  ),
+    .DSIZE  (1  )
+)independent_clock_fifo_inst(
+/*  input                    */   .wr_clk           (axi_master.axi_aclk   ),
+/*  input                    */   .wr_rst_n         (axi_master.axi_aresetn ),
+/*  input                    */   .rd_clk           (out_axis.aclk         ),
+/*  input                    */   .rd_rst_n         (out_axis.aresetn      ),
+/*  input [DSIZE-1:0]        */   .wdata            (1'b1),
+/*  input                    */   .wr_en            (axi_master.axi_arready && axi_master.axi_arvalid),
+/*  output logic[DSIZE-1:0]  */   .rdata            (),
+/*  input                    */   .rd_en            (out_axis.axis_tvalid && out_axis.axis_tready && out_axis.axis_tlast),
+/*  output logic             */   .empty            (cmded_empty           ),
+/*  output logic             */   .full             ()
+);
+
+assign force_rd_en  = cmded_empty && !axis_fifo_empty;
+//---<< forece rd_en >>---------------------------
+
+xilinx_fifo_verb #(
+//xilinx_fifo #(
+    .DSIZE      (out_axis.DSIZE+1 )
+)xilinx_fifo_inst(
+/*    input              */ .wr_clk     (axi_master.axi_aclk   ),
+/*    input              */ .wr_rst     (!axi_master.axi_aresetn),
+/*    input              */ .rd_clk     (out_axis.aclk         ),
+/*    input              */ .rd_rst     (!out_axis.aresetn     ),
+/*    input [DSIZE-1:0]  */ .din        ({axi_master.axi_rlast,axi_master.axi_rdata}  ),
+/*    input              */ .wr_en      ((axi_master.axi_rvalid && axi_master.axi_rready) ),
+/*    input              */ .rd_en      (axis_fifo_rd_en  || force_rd_en     ),
+/*    output [DSIZE-1:0] */ .dout       (axis_fifo_rd_data     ),
+/*    output             */ .full       (axis_fifo_full        ),
+/*    output             */ .empty      (axis_fifo_empty       ),
+/*    output [LSIZE-1:0] */ .rdcount    (),
+/*    output [LSIZE-1:0] */ .wrcount    ()
+);
+
+
+assign axi_master.axi_rready   = !axis_fifo_full;
+
+assign out_axis.axis_tdata  = axis_fifo_rd_data[out_axis.DSIZE-1:0];
+assign out_axis.axis_tlast  = axis_fifo_rd_data[out_axis.DSIZE];
+assign out_axis.axis_tvalid = !axis_fifo_empty;
+assign out_axis.axis_tkeep  = '1;
+assign axis_fifo_rd_en      = out_axis.axis_tvalid && out_axis.axis_tready;
+
+
+//--->> force_align_status <<---------------------
+
+// (* dont_touch = "true" *)
+logic [23:0]    axi4_rd_cnt;
+
+always@(posedge axi_master.axi_aclk)
+    if(axi_master.axi_rvalid && axi_master.axi_rready && axi_master.axi_rlast)
+            axi4_rd_cnt <= '0;
+    else if(axi_master.axi_rvalid && axi_master.axi_rready)
+            axi4_rd_cnt <= axi4_rd_cnt + 1'b1;
+    else    axi4_rd_cnt <= axi4_rd_cnt;
+
+always@(posedge axi_master.axi_aclk ,negedge axi_master.axi_aresetn)
+    if(!axi_master.axi_aresetn)
+            force_align_status  <= 1'b0;
+    else if(axi_master.axi_rvalid && axi_master.axi_rready && axi_master.axi_rlast)
+            force_align_status  <= axi_master.axi_rcnt != axi4_rd_cnt;
+    else if(axis_fifo_empty && cmded_empty)
+            force_align_status  <= 1'b0;
+    else    force_align_status  <= force_align_status;
+
+//---<< force_align_status >>---------------------
+endmodule

data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv

@@ -0,0 +1,66 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERB.1.0
+    longer fifo
+creaded: 2017/2/28 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+`include "define_macro.sv"
+module axi4_packet_fifo_B1 #(
+    parameter   PIPE    = "OFF",
+    parameter   DEPTH   = 4,
+    parameter   MAX_DATA_LEN = 1024*16,
+    `parameter_string   MODE    = "BOTH",        //ONLY_WRITE ONLY_READ BOTH
+    `parameter_string SLAVER_MODE  = "BOTH",    //
+    `parameter_string MASTER_MODE  = "BOTH"   //
+)(
+    axi_inf.slaver axi_in,
+    axi_inf.master axi_out
+);
+
+import SystemPkg::*;
+
+initial begin
+    assert(SLAVER_MODE == MASTER_MODE)
+    else begin
+        $error("SLAVER AXIS MODE != MASTER AXIS MODE");
+        $stop;
+    end
+end
+
+
+`VCS_AXI4_CPT(axi_in,slaver,slaver_rd,Read)
+`VCS_AXI4_CPT(axi_in,slaver,slaver_wr,Write)
+`VCS_AXI4_CPT_LT(axi_out,master_rd,master,Read)
+`VCS_AXI4_CPT_LT(axi_out,master_wr,master,Write)
+
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_WRITE")
+axi4_wr_packet_fifo_A1 #(
+    .PIPE       (PIPE       ),
+    .DEPTH      (DEPTH      ),
+    .MAX_DATA_LEN       (MAX_DATA_LEN    )
+)axi4_wr_packet_fifo_inst(
+/*    axi_inf.slaver_wr */  .axi_in      (`axi_in_vcs_cptWrite        ),
+/*    axi_inf.master_wr */  .axi_out     (`axi_out_vcs_cptWrite       )
+);
+endgenerate
+
+generate
+if(SLAVER_MODE=="BOTH" || SLAVER_MODE=="ONLY_READ")
+axi4_rd_packet_fifo_A1 #(
+    .DEPTH              (DEPTH      ),
+    .MAX_DATA_LEN       (MAX_DATA_LEN    )
+)axi4_rd_packet_fifo_inst(
+/*    axi_inf.slaver_rd */  .slaver      (`axi_in_vcs_cptRead        ),
+/*    axi_inf.master_rd */  .master      (`axi_out_vcs_cptRead       )
+);
+endgenerate
+
+endmodule