axi_tdl 0.2.0 → 0.2.5
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +46 -28
- data/.github/workflows/ruby.yml +1 -1
- data/.gitignore +2 -1
- data/.travis.yml +1 -0
- data/axi_tdl.gemspec +1 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +4 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
- metadata +14 -3
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.1.0
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longer fifo
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creaded: 2017/2/28
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_rd_packet_fifo_A1 #(
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parameter PIPE = "OFF",
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parameter DEPTH = 4,
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parameter MAX_DATA_LEN = 1024*16
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)(
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axi_inf.slaver_rd slaver,
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axi_inf.master_rd master
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);
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logic stream_fifo_full;
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//--->> AUXILIARY <<------------------
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logic auxiliary_fifo_empty;
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logic auxiliary_fifo_full;
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logic auxiliary_fifo_rd_en;
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logic auxiliary_fifo_wr_en;
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independent_clock_fifo #( //fifo can stack DEPTH+1 "DATA"
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.DEPTH (DEPTH-1 ),
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.DSIZE (slaver.ASIZE+slaver.LSIZE+slaver.IDSIZE)
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)auxiliary_independent_clock_fifo_inst(
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/* input */ .wr_clk (slaver.axi_aclk ),
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/* input */ .wr_rst_n (slaver.axi_aresetn ),
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/* input */ .rd_clk (master.axi_aclk ),
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/* input */ .rd_rst_n (master.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata ({slaver.axi_araddr,slaver.axi_arlen,slaver.axi_arid}),
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/* input */ .wr_en (auxiliary_fifo_wr_en ),
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/* output logic[DSIZE-1:0] */ .rdata ({master.axi_araddr,master.axi_arlen,master.axi_arid}),
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/* input */ .rd_en (auxiliary_fifo_rd_en ),
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/* output logic */ .empty (auxiliary_fifo_empty ),
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/* output logic */ .full (auxiliary_fifo_full )
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);
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//--->> SLAVER SIDE <<-------------------------------------
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logic sctrl_fifo_empty;
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logic sctrl_fifo_full;
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logic sctrl_fifo_rd_en;
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logic sctrl_fifo_wr_en;
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(* dont_touch="true" *)
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logic [slaver.IDSIZE-1:0] sctrl_fifo_id;
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independent_clock_fifo #(
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.DEPTH (DEPTH-1 ),
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.DSIZE (slaver.IDSIZE)
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)slaver_last_independent_clock_fifo_inst(
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/* input */ .wr_clk (slaver.axi_aclk ),
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/* input */ .wr_rst_n (slaver.axi_aresetn && master.axi_aresetn ),
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/* input */ .rd_clk (slaver.axi_aclk ),
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/* input */ .rd_rst_n (slaver.axi_aresetn && master.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata (slaver.axi_arid ),
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/* input */ .wr_en (sctrl_fifo_wr_en ),
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/* output logic[DSIZE-1:0] */ .rdata (sctrl_fifo_id ),
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/* input */ .rd_en (sctrl_fifo_rd_en ),
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/* output logic */ .empty (sctrl_fifo_empty ),
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/* output logic */ .full (sctrl_fifo_full )
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);
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assign sctrl_fifo_wr_en = slaver.axi_arvalid && slaver.axi_arready;
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assign sctrl_fifo_rd_en = (slaver.axi_rvalid && slaver.axi_rready && slaver.axi_rlast);
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//---<< SLAVER SIDE >>-------------------------------------
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//--->> MASTER SIDE <<---------------------------------
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logic mctrl_fifo_empty;
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logic mctrl_fifo_full;
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logic mctrl_fifo_rd_en;
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logic mctrl_fifo_wr_en;
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(* dont_touch="true" *)
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logic [master.IDSIZE-1:0] mctrl_fifo_id;
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independent_clock_fifo #(
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.DEPTH (DEPTH-1 ),
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.DSIZE (master.IDSIZE)
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// .DSIZE (1)
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)master_last_independent_clock_fifo_inst(
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/* input */ .wr_clk (master.axi_aclk ),
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/* input */ .wr_rst_n (master.axi_aresetn && slaver.axi_aresetn ),
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/* input */ .rd_clk (master.axi_aclk ),
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/* input */ .rd_rst_n (master.axi_aresetn && slaver.axi_aresetn ),
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/* input [DSIZE-1:0] */ .wdata (master.axi_arid ),
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/* input */ .wr_en (mctrl_fifo_wr_en ),
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/* output logic[DSIZE-1:0] */ .rdata (mctrl_fifo_id ),
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/* input */ .rd_en (mctrl_fifo_rd_en ),
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/* output logic */ .empty (mctrl_fifo_empty ),
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/* output logic */ .full (mctrl_fifo_full )
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);
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assign mctrl_fifo_wr_en = master.axi_arvalid && master.axi_arready;
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assign mctrl_fifo_rd_en = (master.axi_rvalid && master.axi_rready && master.axi_rlast);
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//---<< MASTER SIDE >>---------------------------------
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//--->> VLD RDY PAIR slaver
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assign slaver.axi_arready = !sctrl_fifo_full;
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assign auxiliary_fifo_wr_en = slaver.axi_arvalid && !sctrl_fifo_full;
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//=====================
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//--->> VLD RDY PAIR master
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assign auxiliary_fifo_rd_en = master.axi_arready && !mctrl_fifo_full;
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assign master.axi_arvalid = !auxiliary_fifo_empty && !mctrl_fifo_full;
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//=====================
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//---<< AUXILIARY >>------------------
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//--->> DEPTH CTRL <<-----------------
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//---<< DEPTH CTRL >>-----------------
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//--->> DATA <<-----------------------
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axi_stream_inf #(
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.DSIZE(slaver.DSIZE)
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)axis_out(
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.aclk (slaver.axi_aclk ),
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.aresetn (slaver.axi_aresetn ),
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.aclken (1'b1 )
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);
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axi_stream_inf #(
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.DSIZE(slaver.DSIZE)
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)post_axis_in(
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.aclk (master.axi_aclk ),
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.aresetn (master.axi_aresetn ),
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.aclken (1'b1 )
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);
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axi_stream_inf #(
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.DSIZE(master.DSIZE)
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)axis_in(
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.aclk (master.axi_aclk ),
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.aresetn (master.axi_aresetn ),
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.aclken (1'b1 )
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);
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`ifdef VCS_ENV
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localparam CSIZE = $bits(slaver.axi_rid);
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`else
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localparam CSIZE = slaver.IDSIZE;
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`endif
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axi_stream_packet_fifo_B1F #(
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.DEPTH (DEPTH), //2-4
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.CSIZE (CSIZE ),
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.DSIZE (slaver.DSIZE ),
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.MAX_DATA_LEN(MAX_DATA_LEN)
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)axi_stream_packet_fifo_inst(
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/* input [CSIZE-1:0] */ .in_cdata (master.axi_rid ),
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/* output[CSIZE-1:0] */ .out_cdata (slaver.axi_rid ),
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/* axi_stream_inf.slaver */.slaver_inf (post_axis_in ),
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/* axi_stream_inf.slaver */.master_inf (axis_out )
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);
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generate
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if(PIPE == "ON")
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axis_connect_pipe in_axis_connect_pipe_inst(
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/* axi_stream_inf.slaver */ .axis_in (axis_in ),
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/* axi_stream_inf.master */ .axis_out (post_axis_in )
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);
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else
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axis_direct axis_direct_inst(
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/* axi_stream_inf.slaver */ .slaver (axis_in ),
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/* axi_stream_inf.master */ .master (post_axis_in )
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);
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endgenerate
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//--->> AXIS FIFO SPACE CHK <<--------------
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//---<< AXIS FIFO SPACE CHK >>--------------
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assign axis_in.axis_tvalid = master.axi_rvalid;
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assign axis_in.axis_tdata = master.axi_rdata;
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assign axis_in.axis_tlast = master.axi_rlast;
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assign axis_in.axis_tkeep = '1;
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assign axis_in.axis_tuser = '0;
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assign master.axi_rready = axis_in.axis_tready;
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assign slaver.axi_rvalid = axis_out.axis_tvalid;
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assign slaver.axi_rdata = axis_out.axis_tdata;
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assign slaver.axi_rlast = axis_out.axis_tlast;
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assign axis_out.axis_tready= slaver.axi_rready;
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assign stream_fifo_full = !axis_in.axis_tready;
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//---<< DATA >>-----------------------
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//--->> ID TRACK <<-------------------
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// (* dont_touch="true" *)
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// logic id_err;
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// (* dont_touch="true" *)
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// logic [slaver.IDSIZE-1:0] slaver_post_id;
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// always@(posedge slaver.axi_aclk,negedge slaver.axi_aresetn)begin:ID_ERR_BLOCK
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// if(~slaver.axi_aresetn) begin
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// id_err <= 1'b0;
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// slaver_post_id <= '0;
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// end else begin
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// slaver_post_id <= (slaver.axi_rvalid && slaver.axi_rready)? slaver.axi_rid : slaver_post_id;
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// if(slaver.axi_rvalid && slaver.axi_rready)begin
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// if(slaver_post_id=='1)begin
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// if(slaver.axi_rid != '0 && (slaver_post_id != slaver.axi_rid))
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// id_err <= 1'b1;
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// else id_err <= id_err;
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// end else begin
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// id_err <= (slaver_post_id+1 != slaver.axi_rid) && (slaver_post_id != slaver.axi_rid);
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// end
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// end else slaver_post_id <= slaver_post_id;
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// end
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// end
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//
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// initial begin
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// wait(id_err);
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// #(100us);
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// $stop;
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// end
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//
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// (* dont_touch="true" *)
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// logic master_id_err;
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// (* dont_touch="true" *)
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// logic [slaver.IDSIZE-1:0] master_post_id;
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// always@(posedge master.axi_aclk,negedge master.axi_aresetn)begin:MASTER_ID_ERR_BLOCK
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// if(~master.axi_aresetn) begin
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// master_id_err <= 1'b0;
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// master_id_err <= '0;
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// end else begin
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// master_post_id <= (master.axi_rvalid && master.axi_rready)? master.axi_rid : master_post_id;
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// if(master.axi_rvalid && master.axi_rready)begin
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// if(master_post_id=='1)begin
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// if(master.axi_rid != '0 && (master_post_id != master.axi_rid))
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// master_id_err <= 1'b1;
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// else master_id_err <= master_id_err;
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// end else begin
|
|
234
|
+
// master_id_err <= (master_post_id+1 != master.axi_rid) && (master_post_id != master.axi_rid);
|
|
235
|
+
// end
|
|
236
|
+
// end else master_id_err <= master_id_err;
|
|
237
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+
// end
|
|
238
|
+
// end
|
|
239
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+
//
|
|
240
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+
// initial begin
|
|
241
|
+
// wait(master_id_err);
|
|
242
|
+
// #(100us);
|
|
243
|
+
// $stop;
|
|
244
|
+
// end
|
|
245
|
+
//---<< ID TRACK >>-------------------
|
|
246
|
+
`include "define_macro.sv"
|
|
247
|
+
`VCS_AXI4_CPT(master,master,mirror_rd,)
|
|
248
|
+
import SystemPkg::*;
|
|
249
|
+
generate
|
|
250
|
+
if(SIM=="ON" || SIM=="TRUE")begin
|
|
251
|
+
axi4_rd_burst_track #(
|
|
252
|
+
.MAX_LEN (16 ),
|
|
253
|
+
.MAX_CYCLE (1000 )
|
|
254
|
+
)axi4_rd_burst_track_inst(
|
|
255
|
+
/* axi_inf.mirror_rd */ .axi4_mirror (`master_vcs_cpt )
|
|
256
|
+
);
|
|
257
|
+
end
|
|
258
|
+
endgenerate
|
|
259
|
+
|
|
260
|
+
endmodule
|
|
@@ -0,0 +1,192 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.1.0
|
|
8
|
+
longer fifo
|
|
9
|
+
creaded: 2017/2/28
|
|
10
|
+
madified:
|
|
11
|
+
***********************************************/
|
|
12
|
+
`timescale 1ns/1ps
|
|
13
|
+
module axi4_wr_packet_fifo_A1 #(
|
|
14
|
+
parameter PIPE = "OFF",
|
|
15
|
+
parameter DEPTH = 4,
|
|
16
|
+
parameter MAX_DATA_LEN = 1024*16
|
|
17
|
+
)(
|
|
18
|
+
axi_inf.slaver_wr axi_in,
|
|
19
|
+
axi_inf.master_wr axi_out
|
|
20
|
+
);
|
|
21
|
+
|
|
22
|
+
//--->> AUXILIARY <<------------------
|
|
23
|
+
logic auxiliary_fifo_empty;
|
|
24
|
+
logic auxiliary_fifo_full;
|
|
25
|
+
logic auxiliary_fifo_wr_en;
|
|
26
|
+
logic auxiliary_fifo_rd_en;
|
|
27
|
+
logic [axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE-1:0] auxiliary_fifo_rd_data;
|
|
28
|
+
|
|
29
|
+
independent_clock_fifo #(
|
|
30
|
+
.DEPTH (DEPTH ),
|
|
31
|
+
.DSIZE (axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)
|
|
32
|
+
)auxiliary_independent_clock_fifo_inst(
|
|
33
|
+
/* input */ .wr_clk (axi_in.axi_aclk ),
|
|
34
|
+
/* input */ .wr_rst_n (axi_in.axi_aresetn ),
|
|
35
|
+
/* input */ .rd_clk (axi_out.axi_aclk ),
|
|
36
|
+
/* input */ .rd_rst_n (axi_out.axi_aresetn ),
|
|
37
|
+
/* input [DSIZE-1:0] */ .wdata ({axi_in.axi_awid,axi_in.axi_awaddr,axi_in.axi_awlen}),
|
|
38
|
+
/* input */ .wr_en (axi_in.axi_awvalid ),
|
|
39
|
+
/* output logic[DSIZE-1:0] */ .rdata (auxiliary_fifo_rd_data ),
|
|
40
|
+
/* input */ .rd_en ((auxiliary_fifo_rd_en && !auxiliary_fifo_empty) ),
|
|
41
|
+
/* output logic */ .empty (auxiliary_fifo_empty ),
|
|
42
|
+
/* output logic */ .full (auxiliary_fifo_full )
|
|
43
|
+
);
|
|
44
|
+
|
|
45
|
+
assign axi_in.axi_awready = !auxiliary_fifo_full;
|
|
46
|
+
// assign axi_out.axi_awvalid = !auxiliary_fifo_empty && axi_out.axi_wvalid;
|
|
47
|
+
// assign auxiliary_fifo_rd_en = axi_out.axi_awready && axi_out.axi_awvalid;
|
|
48
|
+
|
|
49
|
+
logic stream_fifo_empty;
|
|
50
|
+
|
|
51
|
+
axi_stream_inf #(.DSIZE(axi_in.ASIZE+axi_in.LSIZE+axi_in.IDSIZE)) id_add_len_in(.aclk(axi_out.axi_aclk),.aresetn(axi_out.axi_aresetn),.aclken(1'b1));
|
|
52
|
+
|
|
53
|
+
assign id_add_len_in.axis_tdata = auxiliary_fifo_rd_data;
|
|
54
|
+
assign id_add_len_in.axis_tvalid = !auxiliary_fifo_empty && !stream_fifo_empty;
|
|
55
|
+
assign id_add_len_in.axis_tlast = 1'b1;
|
|
56
|
+
assign auxiliary_fifo_rd_en = id_add_len_in.axis_tready && !stream_fifo_empty;
|
|
57
|
+
|
|
58
|
+
logic axi_stream_en;
|
|
59
|
+
`VCS_AXI4_CPT_LT(axi_out,master_wr_aux_no_resp,master_wr,Aux_Write)
|
|
60
|
+
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
|
61
|
+
/* axi_stream_inf.slaver */ .id_add_len_in (id_add_len_in ), //tlast is not necessary
|
|
62
|
+
// /* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (axi_out ),
|
|
63
|
+
/* axi_inf.master_wr_aux_no_resp */ .axi_wr_aux (`axi_out_vcs_cptAux_Write ),
|
|
64
|
+
/* output logic */ .stream_en (axi_stream_en )
|
|
65
|
+
);
|
|
66
|
+
//---<< AUXILIARY >>------------------
|
|
67
|
+
//--->> BRESP<<------------------
|
|
68
|
+
logic resp_fifo_empty;
|
|
69
|
+
logic resp_fifo_full;
|
|
70
|
+
|
|
71
|
+
independent_clock_fifo #(
|
|
72
|
+
.DEPTH (DEPTH ),
|
|
73
|
+
.DSIZE (2+axi_in.IDSIZE)
|
|
74
|
+
)bresp_independent_clock_fifo_inst(
|
|
75
|
+
/* input */ .wr_clk (axi_out.axi_aclk ),
|
|
76
|
+
/* input */ .wr_rst_n (axi_out.axi_aresetn ),
|
|
77
|
+
/* input */ .rd_clk (axi_in.axi_aclk ),
|
|
78
|
+
/* input */ .rd_rst_n (axi_in.axi_aresetn ),
|
|
79
|
+
/* input [DSIZE-1:0] */ .wdata ({axi_out.axi_bresp,axi_out.axi_bid} ),
|
|
80
|
+
/* input */ .wr_en (axi_out.axi_bvalid ),
|
|
81
|
+
/* output logic[DSIZE-1:0] */ .rdata ({axi_in.axi_bresp,axi_in.axi_bid} ),
|
|
82
|
+
/* input */ .rd_en (axi_in.axi_bready ),
|
|
83
|
+
/* output logic */ .empty (resp_fifo_empty ),
|
|
84
|
+
/* output logic */ .full (resp_fifo_full )
|
|
85
|
+
);
|
|
86
|
+
|
|
87
|
+
assign axi_out.axi_bready = !resp_fifo_full;
|
|
88
|
+
assign axi_in.axi_bvalid = !resp_fifo_empty;
|
|
89
|
+
//---<< BRESP >>------------------
|
|
90
|
+
//--->> DATA <<-----------------------
|
|
91
|
+
axi_stream_inf #(
|
|
92
|
+
.DSIZE(axi_in.DSIZE)
|
|
93
|
+
)axis_in(
|
|
94
|
+
.aclk (axi_in.axi_aclk ),
|
|
95
|
+
.aresetn (axi_in.axi_aresetn ),
|
|
96
|
+
.aclken (1'b1 )
|
|
97
|
+
);
|
|
98
|
+
|
|
99
|
+
axi_stream_inf #(
|
|
100
|
+
.DSIZE(axi_out.DSIZE)
|
|
101
|
+
)axis_valve_slaver(
|
|
102
|
+
.aclk (axi_out.axi_aclk ),
|
|
103
|
+
.aresetn (axi_out.axi_aresetn ),
|
|
104
|
+
.aclken (1'b1 )
|
|
105
|
+
);
|
|
106
|
+
|
|
107
|
+
axi_stream_inf #(
|
|
108
|
+
.DSIZE(axi_out.DSIZE)
|
|
109
|
+
)axis_out(
|
|
110
|
+
.aclk (axi_out.axi_aclk ),
|
|
111
|
+
.aresetn (axi_out.axi_aresetn ),
|
|
112
|
+
.aclken (1'b1 )
|
|
113
|
+
);
|
|
114
|
+
|
|
115
|
+
data_inf_c #(axi_out.DSIZE+1) axis_out_master_inf (axi_out.axi_aclk,axi_out.axi_aresetn);
|
|
116
|
+
data_inf_c #(axi_out.DSIZE+1) axis_out_slaver_inf (axi_out.axi_aclk,axi_out.axi_aresetn);
|
|
117
|
+
|
|
118
|
+
axi_stream_inf #(
|
|
119
|
+
.DSIZE(axi_out.DSIZE)
|
|
120
|
+
)pre_axis_out(
|
|
121
|
+
.aclk (axi_out.axi_aclk ),
|
|
122
|
+
.aresetn (axi_out.axi_aresetn ),
|
|
123
|
+
.aclken (1'b1 )
|
|
124
|
+
);
|
|
125
|
+
|
|
126
|
+
// axi_stream_packet_fifo #(
|
|
127
|
+
// .DEPTH (DEPTH) //2-4
|
|
128
|
+
// )axi_stream_packet_fifo_inst(
|
|
129
|
+
// /* axi_stream_inf.slaver */ .axis_in (axis_in ),
|
|
130
|
+
// /* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
|
|
131
|
+
// );
|
|
132
|
+
|
|
133
|
+
axi_stream_packet_long_fifo #(
|
|
134
|
+
.DEPTH (DEPTH), //2-4
|
|
135
|
+
.BYTE_DEPTH (MAX_DATA_LEN)
|
|
136
|
+
)axi_stream_packet_fifo_inst(
|
|
137
|
+
/* axi_stream_inf.slaver */ .axis_in (axis_in ),
|
|
138
|
+
/* axi_stream_inf.master */ .axis_out (axis_valve_slaver )
|
|
139
|
+
);
|
|
140
|
+
|
|
141
|
+
assign stream_fifo_empty = !axis_valve_slaver.axis_tvalid;
|
|
142
|
+
|
|
143
|
+
generate
|
|
144
|
+
if(PIPE == "ON")begin
|
|
145
|
+
axis_valve_with_pipe axis_valve_inst(
|
|
146
|
+
// axis_valve axis_valve_inst(
|
|
147
|
+
/* input */ .button (axi_stream_en ), //[1] OPEN ; [0] CLOSE
|
|
148
|
+
/* axi_stream_inf.slaver */ .axis_in (axis_valve_slaver ),
|
|
149
|
+
/* axi_stream_inf.master */ .axis_out (pre_axis_out )
|
|
150
|
+
);
|
|
151
|
+
|
|
152
|
+
assign axis_out_slaver_inf.valid = pre_axis_out.axis_tvalid;
|
|
153
|
+
assign axis_out_slaver_inf.data = {pre_axis_out.axis_tdata,pre_axis_out.axis_tlast};
|
|
154
|
+
assign pre_axis_out.axis_tready = axis_out_slaver_inf.ready;
|
|
155
|
+
|
|
156
|
+
data_c_pipe_force_vld data_c_pipe_force_vld_inst(
|
|
157
|
+
/* data_inf_c.slaver */ .slaver (axis_out_slaver_inf ),
|
|
158
|
+
/* data_inf_c.master */ .master (axis_out_master_inf )
|
|
159
|
+
);
|
|
160
|
+
|
|
161
|
+
assign axis_out.axis_tvalid = axis_out_master_inf.valid;
|
|
162
|
+
assign {axis_out.axis_tdata,axis_out.axis_tlast} = axis_out_master_inf.data;
|
|
163
|
+
assign axis_out_master_inf.ready = axis_out.axis_tready;
|
|
164
|
+
|
|
165
|
+
end else
|
|
166
|
+
axis_valve axis_valve_inst(
|
|
167
|
+
/* input */ .button (axi_stream_en ), //[1] OPEN ; [0] CLOSE
|
|
168
|
+
/* axi_stream_inf.slaver */ .axis_in (axis_valve_slaver ),
|
|
169
|
+
/* axi_stream_inf.master */ .axis_out (axis_out )
|
|
170
|
+
);
|
|
171
|
+
endgenerate
|
|
172
|
+
|
|
173
|
+
assign axis_in.axis_tvalid = axi_in.axi_wvalid;
|
|
174
|
+
assign axis_in.axis_tdata = axi_in.axi_wdata;
|
|
175
|
+
assign axis_in.axis_tlast = axi_in.axi_wlast;
|
|
176
|
+
assign axis_in.axis_tkeep = '1;
|
|
177
|
+
assign axis_in.axis_tuser = '0;
|
|
178
|
+
assign axi_in.axi_wready = axis_in.axis_tready;
|
|
179
|
+
|
|
180
|
+
assign axi_out.axi_wvalid = axis_out.axis_tvalid;
|
|
181
|
+
assign axi_out.axi_wdata = axis_out.axis_tdata;
|
|
182
|
+
assign axi_out.axi_wlast = axis_out.axis_tlast;
|
|
183
|
+
assign axis_out.axis_tready= axi_out.axi_wready;
|
|
184
|
+
//---<< DATA >>-----------------------
|
|
185
|
+
|
|
186
|
+
// axi4_wr_burst_track #(
|
|
187
|
+
// .MAX_LEN (16 ),
|
|
188
|
+
// .MAX_CYCLE (1000 )
|
|
189
|
+
// )axi4_wr_burst_track_inst(
|
|
190
|
+
// /* axi_inf.mirror_wr */ .axi4_mirror (axi_in )
|
|
191
|
+
// );
|
|
192
|
+
endmodule
|
|
@@ -44,8 +44,10 @@ TdlBuild.axi4_partition_rd_verb(__dir__) do
|
|
|
44
44
|
h.input.wr_en partition_pulse_inf.vld_rdy
|
|
45
45
|
h.output['DSIZE'].rdata ''.to_nq
|
|
46
46
|
h.input.rd_en short_inf.axi_rvalid & short_inf.axi_rready & short_inf.axi_rlast
|
|
47
|
-
h.output.logic.empty debugLogic.fifo_empty
|
|
48
|
-
h.output.logic.full debugLogic.fifo_full
|
|
47
|
+
# h.output.logic.empty debugLogic.fifo_empty
|
|
48
|
+
# h.output.logic.full debugLogic.fifo_full
|
|
49
|
+
h.output.logic.empty logic.fifo_empty
|
|
50
|
+
h.output.logic.full logic.fifo_full
|
|
49
51
|
end
|
|
50
52
|
|
|
51
53
|
Assign do
|
|
@@ -4,7 +4,7 @@ ___________ Cook Darwin __________
|
|
|
4
4
|
_______________________________________
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
|
-
Version:
|
|
7
|
+
Version:
|
|
8
8
|
creaded: XXXX.XX.XX
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
@@ -55,22 +55,22 @@ axis_direct axis_direct_end_inf_inst0 (
|
|
|
55
55
|
);
|
|
56
56
|
//-------- CLOCKs Total 3 ----------------------
|
|
57
57
|
//--->> CheckClock <<----------------
|
|
58
|
-
logic
|
|
59
|
-
integer
|
|
60
|
-
ClockSameDomain
|
|
58
|
+
logic cc_done_8,cc_same_8;
|
|
59
|
+
integer cc_afreq_8,cc_bfreq_8;
|
|
60
|
+
ClockSameDomain CheckPClock_inst_8(
|
|
61
61
|
/* input */ .aclk (origin_inf.aclk ),
|
|
62
62
|
/* input */ .bclk (first_inf.aclk ),
|
|
63
|
-
/* output logic */ .done (
|
|
64
|
-
/* output logic */ .same (
|
|
65
|
-
/* output integer */ .aFreqK (
|
|
66
|
-
/* output integer */ .bFreqK (
|
|
63
|
+
/* output logic */ .done (cc_done_8),
|
|
64
|
+
/* output logic */ .same (cc_same_8),
|
|
65
|
+
/* output integer */ .aFreqK (cc_afreq_8),
|
|
66
|
+
/* output integer */ .bFreqK (cc_bfreq_8)
|
|
67
67
|
);
|
|
68
68
|
|
|
69
69
|
initial begin
|
|
70
|
-
wait(
|
|
71
|
-
assert(
|
|
70
|
+
wait(cc_done_8);
|
|
71
|
+
assert(cc_same_8)
|
|
72
72
|
else begin
|
|
73
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
|
|
73
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
|
|
74
74
|
repeat(10)begin
|
|
75
75
|
@(posedge origin_inf.aclk);
|
|
76
76
|
end
|
|
@@ -80,22 +80,22 @@ end
|
|
|
80
80
|
//---<< CheckClock >>----------------
|
|
81
81
|
|
|
82
82
|
//--->> CheckClock <<----------------
|
|
83
|
-
logic
|
|
84
|
-
integer
|
|
85
|
-
ClockSameDomain
|
|
83
|
+
logic cc_done_9,cc_same_9;
|
|
84
|
+
integer cc_afreq_9,cc_bfreq_9;
|
|
85
|
+
ClockSameDomain CheckPClock_inst_9(
|
|
86
86
|
/* input */ .aclk (origin_inf.aclk ),
|
|
87
87
|
/* input */ .bclk (end_inf.aclk ),
|
|
88
|
-
/* output logic */ .done (
|
|
89
|
-
/* output logic */ .same (
|
|
90
|
-
/* output integer */ .aFreqK (
|
|
91
|
-
/* output integer */ .bFreqK (
|
|
88
|
+
/* output logic */ .done (cc_done_9),
|
|
89
|
+
/* output logic */ .same (cc_same_9),
|
|
90
|
+
/* output integer */ .aFreqK (cc_afreq_9),
|
|
91
|
+
/* output integer */ .bFreqK (cc_bfreq_9)
|
|
92
92
|
);
|
|
93
93
|
|
|
94
94
|
initial begin
|
|
95
|
-
wait(
|
|
96
|
-
assert(
|
|
95
|
+
wait(cc_done_9);
|
|
96
|
+
assert(cc_same_9)
|
|
97
97
|
else begin
|
|
98
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
|
|
98
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
|
99
99
|
repeat(10)begin
|
|
100
100
|
@(posedge origin_inf.aclk);
|
|
101
101
|
end
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from axi_streams_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from axi_streams_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
creaded: 2016/12/9
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.1.0 2018-4-16 12:13:05
|
|
7
8
|
use data_c_scaler
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
creaded: 2017/3/23
|
|
@@ -34,9 +34,10 @@ logic [DSIZE*16*8-1:0] value_tmp;
|
|
|
34
34
|
|
|
35
35
|
// assign value_tmp = {value,{(16*8-FIELD_LEN){1'b0}}};
|
|
36
36
|
generate
|
|
37
|
-
if(FIELD_LEN < 128)
|
|
37
|
+
if(FIELD_LEN < 128)begin
|
|
38
38
|
assign value_tmp[DSIZE*16*8-1-:DSIZE*FIELD_LEN] = value;
|
|
39
|
-
|
|
39
|
+
assign value_tmp[DSIZE*16*8-1-DSIZE*FIELD_LEN:0] = '0;
|
|
40
|
+
end else
|
|
40
41
|
assign value_tmp = value;
|
|
41
42
|
endgenerate
|
|
42
43
|
|