axi_tdl 0.2.0 → 0.2.5

data/lib/axi/AXI_stream/gen_origin_axis_A3.sv

@@ -0,0 +1,163 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.1.0
+    addr start num
+Version: VERA.2.0
+    length can be 1
+Version: VERA.3.0 
+    can be reset
+creaded: 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module gen_origin_axis_A3 #(
+    `parameter_string MODE = "RANGE"
+)(
+    input                 reset,
+    input                 enable,
+    output logic          ready,
+    input [31:0]          length,       // '1' meet 1 length
+    input [31:0]          start,
+    axi_stream_inf.master axis_out
+);
+
+import DataInterfacePkg::*;
+
+wire    clock,rst_n;
+
+assign  clock   = axis_out.aclk;
+assign  rst_n   = axis_out.aresetn;
+
+assign  axis_out.axis_tuser = 1'b0;
+assign  axis_out.axis_tkeep = '1;
+
+typedef enum {IDLE,SEND_DATA,FRAME_DONE}    STATUS;
+
+STATUS  cstate,nstate;
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n || reset)  
+                cstate  <= IDLE;
+    else        cstate  <= nstate;
+
+// logic   data_ok;
+
+always@(*)
+    case(cstate)
+    IDLE:
+        if(enable && ready)
+                nstate  = SEND_DATA;
+        else    nstate  = IDLE;
+    SEND_DATA:
+        if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)
+                nstate  = IDLE;
+        else    nstate  = SEND_DATA;
+    FRAME_DONE:
+        // if(!enable)
+                nstate  = IDLE;
+        // else    nstate  = FRAME_DONE;
+    default:    nstate  = IDLE;
+    endcase
+
+// always@(posedge clock/*,negedge rst_n*/)
+//     if(~rst_n)  axis_out.axis_tdata     <= start;
+//     else begin
+//         if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
+//             if(axis_out.axis_tdata < (start+length-1))begin
+//                 if(MODE == "RANGE")
+//                         axis_out.axis_tdata     <= axis_out.axis_tdata + 1'b1;
+//                 else    axis_out.axis_tdata     <= start;
+//             end
+//             else    axis_out.axis_tdata     <= start;
+//         else    axis_out.axis_tdata     <= axis_out.axis_tdata;
+//     end
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n || reset)  axis_out.axis_tdata     <= start;
+    else
+        case(nstate)
+        IDLE:       axis_out.axis_tdata     <= start;
+        SEND_DATA:begin
+            if(enable && ready)
+                    axis_out.axis_tdata     <= start;
+            else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)begin 
+                    // axis_out.axis_tdata     <= axis_out.axis_tdata + 1'b1;
+                     if(MODE == "RANGE")
+                            axis_out.axis_tdata     <= axis_out.axis_tdata + 1'b1;
+                    else    axis_out.axis_tdata     <= start;
+            end else    
+                    axis_out.axis_tdata     <= axis_out.axis_tdata;
+        end
+        default:;
+        endcase
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n || reset)  axis_out.axis_tvalid     <= 1'b0;
+    else
+        case(nstate)
+        SEND_DATA:  axis_out.axis_tvalid    <= 1'b1;
+        default:    axis_out.axis_tvalid    <= 1'b0;
+        endcase
+
+
+// reg [31:0]      cnt ;
+// always@(posedge clock/*,negedge rst_n*/)
+//     if(~rst_n)  cnt     <= '0;
+//     else begin
+//         if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
+//             if(cnt < (length-1))
+//                     cnt     <= cnt + 1'b1;
+//             else    cnt     <= '0;
+//         else        cnt     <= cnt;
+//     end
+
+//
+logic [31:0]    lock_length;
+always@(posedge clock/*,negedge rst_n*/)begin 
+    if(~rst_n || reset)  lock_length <= '0;
+    else begin 
+        if(enable && ready)
+                lock_length <= length;
+        else    lock_length <= lock_length;
+    end 
+end 
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n || reset)  axis_out.axis_tlast    <= 1'b0;
+    else begin
+        // if(axis_out.aclken)
+        //     if(length > 1)
+        //             axis_out.axis_tlast <= pipe_last_func(axis_out.axis_tvalid,axis_out.axis_tready,axis_out.axis_tlast,(cnt==length-2));
+        //     else    axis_out.axis_tlast <= 1'b1;
+        // else    axis_out.axis_tlast <= 1'b0;
+        if(axis_out.aclken)begin 
+            if(enable && ready)begin 
+                axis_out.axis_tlast <= length < 2;
+            end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)begin
+                axis_out.axis_tlast <= 1'b0;
+            end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tcnt==lock_length-2 && axis_out.aclken )begin 
+                axis_out.axis_tlast <= 1'b1;
+            end else begin 
+                axis_out.axis_tlast <= axis_out.axis_tlast;
+            end 
+        end else begin 
+            axis_out.axis_tlast <= axis_out.axis_tlast;
+        end
+    end
+
+// assign  data_ok = axis_out.axis_tlast && axis_out.axis_tready && axis_out.axis_tvalid;
+
+always@(posedge clock/*,negedge rst_n*/)
+    if(~rst_n || reset)  ready     <= 1'b0;
+    else
+        case(nstate)
+        IDLE:       ready    <= 1'b1;
+        default:    ready    <= 1'b0;
+        endcase
+
+
+endmodule

data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv

@@ -0,0 +1,129 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERB.0.0 :
+    add custom signalssync to last
+Version: VERB.1.0 :2017/3/15 
+    add empty size
+Version: VERB.1.1 :2017/11/3 
+    user xilinx_fifo_verb
+Version: VERB.1.F 
+    longer fifo
+creaded:
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module axi_stream_packet_fifo_B1F #(
+    parameter DEPTH   = 2,   //2-4
+    parameter CSIZE   = 1,
+    parameter DSIZE   = 24,
+    parameter MAX_DATA_LEN = 1024*16
+)(
+    input [CSIZE-1:0]        in_cdata,
+    output[CSIZE-1:0]        out_cdata,
+    axi_stream_inf.slaver    slaver_inf,
+    axi_stream_inf.master    master_inf
+);
+
+
+parameter LSIZE = $clog2(1024+1);
+
+logic   data_fifo_full;
+logic   data_fifo_empty;
+
+
+long_fifo_verb #(
+    .DSIZE          (DSIZE         ),
+    .LENGTH         (MAX_DATA_LEN  )
+)long_fifo_verb_inst(
+/*  input              */ .wr_clk       (slaver_inf.aclk        ),
+/*  input              */ .wr_rst       (!slaver_inf.aresetn    ),
+/*  input              */ .rd_clk       (master_inf.aclk       ),
+/*  input              */ .rd_rst       (!master_inf.aresetn   ),
+/*  input [DSIZE-1:0]  */ .din          (slaver_inf.axis_tdata  ),
+/*  input              */ .wr_en        ((slaver_inf.axis_tvalid && slaver_inf.axis_tready)      ),
+/*  input              */ .rd_en        ((master_inf.axis_tvalid && master_inf.axis_tready)    ),
+/*  output [DSIZE-1:0] */ .dout         (master_inf.axis_tdata ),
+/*  output             */ .full         (data_fifo_full      ),
+/*  output             */ .empty        (data_fifo_empty     )
+);
+
+//---<< NATIVE FIFO IP >>------------------------------
+
+//--->> PACKET <<--------------------------------------
+logic   packet_fifo_full;
+logic   packet_fifo_empty;
+logic [15:0]      w_bytes_total;
+logic [15:0]      r_bytes_total;
+logic             w_total_eq_1;
+logic             r_total_eq_1;
+
+// assign w_total_eq_1 = w_bytes_total=='0;
+assign w_total_eq_1 = slaver_inf.axis_tcnt =='0;
+
+localparam IDEPTH   = (DEPTH<4)? 4 : DEPTH;
+
+independent_clock_fifo #(
+    .DEPTH      (IDEPTH     ),
+    .DSIZE      (16+1+CSIZE      )
+)common_independent_clock_fifo_inst(
+/*    input                     */  .wr_clk     (slaver_inf.aclk        ),
+/*    input                     */  .wr_rst_n   (slaver_inf.aresetn     ),
+/*    input                     */  .rd_clk     (master_inf.aclk       ),
+/*    input                     */  .rd_rst_n   (master_inf.aresetn    ),
+/*    input [DSIZE-1:0]         */  .wdata      ({w_total_eq_1,w_bytes_total,in_cdata}      ),
+/*    input                     */  .wr_en      ((slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready)      ),
+/*    output logic[DSIZE-1:0]   */  .rdata      ({r_total_eq_1,r_bytes_total,out_cdata}      ),
+/*    input                     */  .rd_en      ((master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready)    ),
+/*    output logic              */  .empty      (packet_fifo_empty   ),
+/*    output logic              */  .full       (packet_fifo_full    )
+);
+
+assign slaver_inf.axis_tready  = !packet_fifo_full && !data_fifo_full;
+assign master_inf.axis_tvalid = !packet_fifo_empty && !data_fifo_empty;
+//---<< PACKET >>--------------------------------------
+//--->> bytes counter <<-------------------------------
+logic reset_w_bytes;
+assign #1 reset_w_bytes = slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready;
+
+always@(posedge slaver_inf.aclk,negedge slaver_inf.aresetn)
+    if(~slaver_inf.aresetn)    w_bytes_total   <= '0;
+    else begin
+        if(reset_w_bytes)
+                w_bytes_total   <= '0;
+        else if(slaver_inf.axis_tvalid && slaver_inf.axis_tready)
+                w_bytes_total   <= w_bytes_total + 1'b1;
+        else    w_bytes_total   <= w_bytes_total;
+    end
+
+logic [15:0]    out_cnt;
+
+always@(posedge master_inf.aclk,negedge master_inf.aresetn)
+    if(~master_inf.aresetn)   out_cnt <= '0;
+    else begin
+        if(master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready)
+                out_cnt   <= '0;
+        else if(master_inf.axis_tvalid && master_inf.axis_tready)
+                out_cnt   <= out_cnt + 1'b1;
+        else    out_cnt   <= out_cnt;
+    end
+//---<< bytes counter >>-------------------------------
+//--->> READ LAST <<-----------------------------------
+logic   native_last;
+
+always@(posedge master_inf.aclk,negedge master_inf.aresetn)
+    if(~master_inf.aresetn) native_last   <= 1'b0;
+    else begin
+        if(master_inf.axis_tvalid && native_last && master_inf.axis_tready)
+                native_last <= 1'b0;
+        else if(out_cnt == (r_bytes_total-1) && master_inf.axis_tvalid  && master_inf.axis_tready)
+                native_last <= 1'b1;
+        else    native_last <= native_last;
+    end
+
+assign master_inf.axis_tlast  = native_last || r_total_eq_1;
+//---<< READ LAST >>-----------------------------------
+endmodule

data/lib/axi/AXI_stream/parse_big_field_table_main.sv

@@ -0,0 +1,101 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript: 解析大块的值域用于  common_frame_table
+author : Cook.Darwin
+Version: VERA.2.0 2017/9/11 
+    resever value
+Version: VERA.2.0 2017/12/11 
+    use parse_common_frame_table_A2
+Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
+    rebuild
+creaded: 2016/12/22 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module parse_big_field_table_main #(
+    parameter   DSIZE         = 8,
+    parameter   FIELD_LEN     = 16*8,     //MAX 16*8
+    parameter   START_INDEX   = 0
+)(
+    output logic[START_INDEX:DSIZE*FIELD_LEN-1]       value,
+    output logic                            out_valid,
+    axi_stream_inf.slaver                   cm_tb_s,
+    axi_stream_inf.master                   cm_tb_m
+);
+
+localparam  VSIZE = $clog2(FIELD_LEN);
+
+import SystemPkg::*;
+
+initial begin 
+    assert(DSIZE == cm_tb_s.DSIZE)
+    else begin 
+        $error("DSIZE<%d> != stream.DSIZE<%d>",DSIZE, cm_tb_s.DSIZE);
+    end 
+end
+
+wire        clock,rst_n,clken;
+
+axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
+
+assign      clock   = cm_tb_s.aclk;
+assign      rst_n   = cm_tb_s.aresetn;
+assign      clken   = cm_tb_s.aclken;
+
+
+assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
+assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
+assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
+assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
+assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
+assign parse_stream.axis_tready= cm_tb_m.axis_tready;
+assign cm_tb_s.axis_tready     = cm_tb_m.axis_tready;
+
+
+logic   region_valid;
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  region_valid   <= 1'b1;
+    else begin 
+        if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
+                region_valid    <= 1'b1;
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
+                region_valid    <= 1'b0;
+        else    region_valid    <= region_valid;
+    end
+end
+
+
+logic[DSIZE-1:0]    value_array [0:FIELD_LEN-1];
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  
+        foreach(value_array[i])
+            value_array[i]   <= '0;
+    else begin 
+        if(region_valid)begin
+            value_array[parse_stream.axis_tcnt[VSIZE-1:0]]    <= parse_stream.axis_tdata;
+        end
+    end
+end
+
+assign value    = {>>{value_array}};
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  out_valid   <= 1'b0;
+    else begin
+        if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
+            if(out_valid)
+                    out_valid    <= 1'b0;
+            else    out_valid    <= 1'b1;
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
+                out_valid    <= 1'b1;
+        else if(region_valid)
+                out_valid   <= 1'b0;
+        else    out_valid    <= out_valid;
+    end
+end
+
+endmodule

data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv

@@ -0,0 +1,94 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript: 解析大块的值域用于  common_frame_table
+author : Cook.Darwin
+Version: VERA.2.0 2017/9/11 
+    resever value
+Version: VERA.2.0 2017/12/11 
+    use parse_common_frame_table_A2
+Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
+    rebuild
+creaded: 2016/12/22 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module parse_big_field_table_mirror #(
+    parameter   DSIZE         = 8,
+    parameter   FIELD_LEN     = 16*8,     //MAX 16*8
+    parameter   START_INDEX   = 0
+)(
+    output logic[START_INDEX:DSIZE*FIELD_LEN-1]       value,
+    output logic                            out_valid,
+    axi_stream_inf.mirror                   cm_mirror
+);
+
+localparam  VSIZE = $clog2(FIELD_LEN);
+
+import SystemPkg::*;
+
+
+wire        clock,rst_n,clken;
+
+axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
+
+
+
+assign      clock   = cm_mirror.aclk;
+assign      rst_n   = cm_mirror.aresetn;
+assign      clken   = cm_mirror.aclken;
+
+assign parse_stream.axis_tkeep = cm_mirror.axis_tkeep ;
+assign parse_stream.axis_tuser = cm_mirror.axis_tuser ;
+assign parse_stream.axis_tlast = cm_mirror.axis_tlast ;
+assign parse_stream.axis_tdata = cm_mirror.axis_tdata ;
+assign parse_stream.axis_tvalid= cm_mirror.axis_tvalid;
+assign parse_stream.axis_tready= cm_mirror.axis_tready;
+
+
+logic   region_valid;
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  region_valid   <= 1'b1;
+    else begin 
+        if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
+                region_valid    <= 1'b1;
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
+                region_valid    <= 1'b0;
+        else    region_valid    <= region_valid;
+    end
+end
+
+
+logic[DSIZE-1:0]    value_array [0:FIELD_LEN-1];
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  
+        foreach(value_array[i])
+            value_array[i]   <= '0;
+    else begin 
+        if(region_valid)begin
+            value_array[parse_stream.axis_tcnt[VSIZE-1:0]]    <= parse_stream.axis_tdata;
+        end
+    end
+end
+
+assign value    = {>>{value_array}};
+
+always_ff@(posedge clock,negedge rst_n)begin 
+    if(~rst_n)  out_valid   <= 1'b0;
+    else begin
+        if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
+            if(out_valid)
+                    out_valid    <= 1'b0;
+            else    out_valid    <= 1'b1;
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
+                out_valid    <= 1'b1;
+        else if(region_valid)
+                out_valid   <= 1'b0;
+        else    out_valid    <= out_valid;
+    end
+end
+
+endmodule

data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv

@@ -0,0 +1,75 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.1 2017/9/28 
+    user axi4 addr_step
+Version: VERC.0.0 2018/11/23 
+    rebuild
+Version: VERC.1.0 ###### Fri Apr 24 10:14:28 CST 2020
+    use ddr_native_fifo_verb
+Version: VERC.2.0 
+    使用 ddr_native_fifo_B1 具有跨时钟功能
+creaded: 2016/10/12
+madified:
+***********************************************/
+`timescale 1ns / 1ps
+(* axi4 = "true" *)
+module axi4_to_native_for_ddr_ip_C2 #(
+    parameter ADDR_WIDTH            = 27,
+    parameter DATA_WIDTH            = 256
+)(
+    axi_inf.slaver                  ddr3_axi4_inf,
+    input                           ui_clock,
+    input                           ui_rstn,
+    output logic[ADDR_WIDTH-1:0]    app_addr,
+    output logic[2:0]               app_cmd,
+    output logic                    app_en,
+    output logic[DATA_WIDTH-1:0]    app_wdf_data,
+    output logic                    app_wdf_end,
+    output logic[DATA_WIDTH/8-1:0]  app_wdf_mask,
+    output logic                    app_wdf_wren,
+    input  [DATA_WIDTH-1:0]         app_rd_data,
+    input                           app_rd_data_end,
+    input                           app_rd_data_valid,
+    input                           app_rdy,
+    input                           app_wdf_rdy,
+    input logic                     init_calib_complete
+);
+
+axi_stream_inf #(DATA_WIDTH + ADDR_WIDTH + 3)   axis_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
+axi_stream_inf #(DATA_WIDTH)                    axis_rd_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
+
+ddr_axi4_to_axis ddr_axi4_to_axis_inst(
+/*  axi4.slaver            */     .axi4_inf     (ddr3_axi4_inf    ),
+/*  axi_stream_inf.master  */     .axis_inf     (axis_inf   ),
+/*  axi_stream_inf.slaver  */     .axis_rd_inf  (axis_rd_inf)   //DSIZE
+);
+
+ddr_native_fifo_B1 #(
+    .ADDR_WIDTH     (ADDR_WIDTH   ),
+    .DATA_WIDTH     (DATA_WIDTH   )
+)ddr_native_fifo_B1_inst(
+/*    axi_stream_inf.slaver         */ .axis_inf             (axis_inf              ),
+/*    axi_stream_inf.master         */ .axis_rd_inf          (axis_rd_inf           ),
+/*    //---DDR IP                   */
+/*    input                         */ .ui_clock             (ui_clock              ),
+/*    input                         */ .ui_rstn              (ui_rstn               ),
+/*    output logic[ADDR_WIDTH-1:0]  */ .app_addr             (app_addr              ),
+/*    output logic[2:0]             */ .app_cmd              (app_cmd               ),
+/*    output logic                  */ .app_en               (app_en                ),
+/*    output logic[DATA_WIDTH-1:0]  */ .app_wdf_data         (app_wdf_data          ),
+/*    output logic                  */ .app_wdf_end          (app_wdf_end           ),
+/*    output logic[DATA_WIDTH/8-1:0]*/ .app_wdf_mask         (app_wdf_mask          ),
+/*    output logic                  */ .app_wdf_wren         (app_wdf_wren          ),
+/*    input  [DATA_WIDTH-1:0]       */ .app_rd_data          (app_rd_data           ),
+/*    input                         */ .app_rd_data_end      (app_rd_data_end       ),
+/*    input                         */ .app_rd_data_valid    (app_rd_data_valid     ),
+/*    input                         */ .app_rdy              (app_rdy               ),
+/*    input                         */ .app_wdf_rdy          (app_wdf_rdy           ),
+/*    input logic                   */ .init_calib_complete  (init_calib_complete   )
+);
+
+endmodule