axi_tdl 0.2.0 → 0.2.5

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (49) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +46 -28
  3. data/.github/workflows/ruby.yml +1 -1
  4. data/.gitignore +2 -1
  5. data/.travis.yml +1 -0
  6. data/axi_tdl.gemspec +1 -1
  7. data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
  8. data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
  9. data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
  10. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
  11. data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
  12. data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
  13. data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
  14. data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +4 -2
  16. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
  17. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
  18. data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
  19. data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
  20. data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
  21. data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
  22. data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
  23. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
  24. data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
  25. data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
  26. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
  27. data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
  28. data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
  29. data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
  30. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
  31. data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
  32. data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
  33. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  34. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  35. data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
  36. data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
  37. data/lib/axi/data_interface/data_streams_combin.sv +2 -1
  38. data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
  39. data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
  40. data/lib/axi_tdl/version.rb +1 -1
  41. data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
  42. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
  43. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  44. data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
  45. data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
  46. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  47. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
  48. data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
  49. metadata +14 -3
@@ -0,0 +1,163 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.1.0
8
+ addr start num
9
+ Version: VERA.2.0
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+ length can be 1
11
+ Version: VERA.3.0
12
+ can be reset
13
+ creaded:
14
+ madified:
15
+ ***********************************************/
16
+ `timescale 1ns/1ps
17
+ module gen_origin_axis_A3 #(
18
+ `parameter_string MODE = "RANGE"
19
+ )(
20
+ input reset,
21
+ input enable,
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+ output logic ready,
23
+ input [31:0] length, // '1' meet 1 length
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+ input [31:0] start,
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+ axi_stream_inf.master axis_out
26
+ );
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+
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+ import DataInterfacePkg::*;
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+
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+ wire clock,rst_n;
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+
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+ assign clock = axis_out.aclk;
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+ assign rst_n = axis_out.aresetn;
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+
35
+ assign axis_out.axis_tuser = 1'b0;
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+ assign axis_out.axis_tkeep = '1;
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+
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+ typedef enum {IDLE,SEND_DATA,FRAME_DONE} STATUS;
39
+
40
+ STATUS cstate,nstate;
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+
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+ always@(posedge clock/*,negedge rst_n*/)
43
+ if(~rst_n || reset)
44
+ cstate <= IDLE;
45
+ else cstate <= nstate;
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+
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+ // logic data_ok;
48
+
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+ always@(*)
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+ case(cstate)
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+ IDLE:
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+ if(enable && ready)
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+ nstate = SEND_DATA;
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+ else nstate = IDLE;
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+ SEND_DATA:
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+ if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)
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+ nstate = IDLE;
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+ else nstate = SEND_DATA;
59
+ FRAME_DONE:
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+ // if(!enable)
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+ nstate = IDLE;
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+ // else nstate = FRAME_DONE;
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+ default: nstate = IDLE;
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+ endcase
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+
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+ // always@(posedge clock/*,negedge rst_n*/)
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+ // if(~rst_n) axis_out.axis_tdata <= start;
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+ // else begin
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+ // if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
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+ // if(axis_out.axis_tdata < (start+length-1))begin
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+ // if(MODE == "RANGE")
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+ // axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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+ // else axis_out.axis_tdata <= start;
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+ // end
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+ // else axis_out.axis_tdata <= start;
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+ // else axis_out.axis_tdata <= axis_out.axis_tdata;
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+ // end
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+
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+ always@(posedge clock/*,negedge rst_n*/)
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+ if(~rst_n || reset) axis_out.axis_tdata <= start;
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+ else
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+ case(nstate)
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+ IDLE: axis_out.axis_tdata <= start;
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+ SEND_DATA:begin
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+ if(enable && ready)
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+ axis_out.axis_tdata <= start;
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+ else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)begin
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+ // axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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+ if(MODE == "RANGE")
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+ axis_out.axis_tdata <= axis_out.axis_tdata + 1'b1;
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+ else axis_out.axis_tdata <= start;
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+ end else
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+ axis_out.axis_tdata <= axis_out.axis_tdata;
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+ end
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+ default:;
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+ endcase
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+
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+ always@(posedge clock/*,negedge rst_n*/)
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+ if(~rst_n || reset) axis_out.axis_tvalid <= 1'b0;
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+ else
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+ case(nstate)
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+ SEND_DATA: axis_out.axis_tvalid <= 1'b1;
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+ default: axis_out.axis_tvalid <= 1'b0;
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+ endcase
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+
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+
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+ // reg [31:0] cnt ;
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+ // always@(posedge clock/*,negedge rst_n*/)
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+ // if(~rst_n) cnt <= '0;
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+ // else begin
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+ // if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.aclken)
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+ // if(cnt < (length-1))
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+ // cnt <= cnt + 1'b1;
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+ // else cnt <= '0;
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+ // else cnt <= cnt;
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+ // end
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+
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+ //
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+ logic [31:0] lock_length;
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+ always@(posedge clock/*,negedge rst_n*/)begin
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+ if(~rst_n || reset) lock_length <= '0;
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+ else begin
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+ if(enable && ready)
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+ lock_length <= length;
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+ else lock_length <= lock_length;
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+ end
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+ end
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+
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+ always@(posedge clock/*,negedge rst_n*/)
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+ if(~rst_n || reset) axis_out.axis_tlast <= 1'b0;
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+ else begin
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+ // if(axis_out.aclken)
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+ // if(length > 1)
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+ // axis_out.axis_tlast <= pipe_last_func(axis_out.axis_tvalid,axis_out.axis_tready,axis_out.axis_tlast,(cnt==length-2));
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+ // else axis_out.axis_tlast <= 1'b1;
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+ // else axis_out.axis_tlast <= 1'b0;
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+ if(axis_out.aclken)begin
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+ if(enable && ready)begin
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+ axis_out.axis_tlast <= length < 2;
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+ end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tlast && axis_out.aclken)begin
141
+ axis_out.axis_tlast <= 1'b0;
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+ end else if(axis_out.axis_tvalid && axis_out.axis_tready && axis_out.axis_tcnt==lock_length-2 && axis_out.aclken )begin
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+ axis_out.axis_tlast <= 1'b1;
144
+ end else begin
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+ axis_out.axis_tlast <= axis_out.axis_tlast;
146
+ end
147
+ end else begin
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+ axis_out.axis_tlast <= axis_out.axis_tlast;
149
+ end
150
+ end
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+
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+ // assign data_ok = axis_out.axis_tlast && axis_out.axis_tready && axis_out.axis_tvalid;
153
+
154
+ always@(posedge clock/*,negedge rst_n*/)
155
+ if(~rst_n || reset) ready <= 1'b0;
156
+ else
157
+ case(nstate)
158
+ IDLE: ready <= 1'b1;
159
+ default: ready <= 1'b0;
160
+ endcase
161
+
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+
163
+ endmodule
@@ -0,0 +1,129 @@
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+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERB.0.0 :
8
+ add custom signalssync to last
9
+ Version: VERB.1.0 :2017/3/15
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+ add empty size
11
+ Version: VERB.1.1 :2017/11/3
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+ user xilinx_fifo_verb
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+ Version: VERB.1.F
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+ longer fifo
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+ creaded:
16
+ madified:
17
+ ***********************************************/
18
+ `timescale 1ns/1ps
19
+ module axi_stream_packet_fifo_B1F #(
20
+ parameter DEPTH = 2, //2-4
21
+ parameter CSIZE = 1,
22
+ parameter DSIZE = 24,
23
+ parameter MAX_DATA_LEN = 1024*16
24
+ )(
25
+ input [CSIZE-1:0] in_cdata,
26
+ output[CSIZE-1:0] out_cdata,
27
+ axi_stream_inf.slaver slaver_inf,
28
+ axi_stream_inf.master master_inf
29
+ );
30
+
31
+
32
+ parameter LSIZE = $clog2(1024+1);
33
+
34
+ logic data_fifo_full;
35
+ logic data_fifo_empty;
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+
37
+
38
+ long_fifo_verb #(
39
+ .DSIZE (DSIZE ),
40
+ .LENGTH (MAX_DATA_LEN )
41
+ )long_fifo_verb_inst(
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+ /* input */ .wr_clk (slaver_inf.aclk ),
43
+ /* input */ .wr_rst (!slaver_inf.aresetn ),
44
+ /* input */ .rd_clk (master_inf.aclk ),
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+ /* input */ .rd_rst (!master_inf.aresetn ),
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+ /* input [DSIZE-1:0] */ .din (slaver_inf.axis_tdata ),
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+ /* input */ .wr_en ((slaver_inf.axis_tvalid && slaver_inf.axis_tready) ),
48
+ /* input */ .rd_en ((master_inf.axis_tvalid && master_inf.axis_tready) ),
49
+ /* output [DSIZE-1:0] */ .dout (master_inf.axis_tdata ),
50
+ /* output */ .full (data_fifo_full ),
51
+ /* output */ .empty (data_fifo_empty )
52
+ );
53
+
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+ //---<< NATIVE FIFO IP >>------------------------------
55
+
56
+ //--->> PACKET <<--------------------------------------
57
+ logic packet_fifo_full;
58
+ logic packet_fifo_empty;
59
+ logic [15:0] w_bytes_total;
60
+ logic [15:0] r_bytes_total;
61
+ logic w_total_eq_1;
62
+ logic r_total_eq_1;
63
+
64
+ // assign w_total_eq_1 = w_bytes_total=='0;
65
+ assign w_total_eq_1 = slaver_inf.axis_tcnt =='0;
66
+
67
+ localparam IDEPTH = (DEPTH<4)? 4 : DEPTH;
68
+
69
+ independent_clock_fifo #(
70
+ .DEPTH (IDEPTH ),
71
+ .DSIZE (16+1+CSIZE )
72
+ )common_independent_clock_fifo_inst(
73
+ /* input */ .wr_clk (slaver_inf.aclk ),
74
+ /* input */ .wr_rst_n (slaver_inf.aresetn ),
75
+ /* input */ .rd_clk (master_inf.aclk ),
76
+ /* input */ .rd_rst_n (master_inf.aresetn ),
77
+ /* input [DSIZE-1:0] */ .wdata ({w_total_eq_1,w_bytes_total,in_cdata} ),
78
+ /* input */ .wr_en ((slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready) ),
79
+ /* output logic[DSIZE-1:0] */ .rdata ({r_total_eq_1,r_bytes_total,out_cdata} ),
80
+ /* input */ .rd_en ((master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready) ),
81
+ /* output logic */ .empty (packet_fifo_empty ),
82
+ /* output logic */ .full (packet_fifo_full )
83
+ );
84
+
85
+ assign slaver_inf.axis_tready = !packet_fifo_full && !data_fifo_full;
86
+ assign master_inf.axis_tvalid = !packet_fifo_empty && !data_fifo_empty;
87
+ //---<< PACKET >>--------------------------------------
88
+ //--->> bytes counter <<-------------------------------
89
+ logic reset_w_bytes;
90
+ assign #1 reset_w_bytes = slaver_inf.axis_tvalid && slaver_inf.axis_tlast && slaver_inf.axis_tready;
91
+
92
+ always@(posedge slaver_inf.aclk,negedge slaver_inf.aresetn)
93
+ if(~slaver_inf.aresetn) w_bytes_total <= '0;
94
+ else begin
95
+ if(reset_w_bytes)
96
+ w_bytes_total <= '0;
97
+ else if(slaver_inf.axis_tvalid && slaver_inf.axis_tready)
98
+ w_bytes_total <= w_bytes_total + 1'b1;
99
+ else w_bytes_total <= w_bytes_total;
100
+ end
101
+
102
+ logic [15:0] out_cnt;
103
+
104
+ always@(posedge master_inf.aclk,negedge master_inf.aresetn)
105
+ if(~master_inf.aresetn) out_cnt <= '0;
106
+ else begin
107
+ if(master_inf.axis_tvalid && master_inf.axis_tlast && master_inf.axis_tready)
108
+ out_cnt <= '0;
109
+ else if(master_inf.axis_tvalid && master_inf.axis_tready)
110
+ out_cnt <= out_cnt + 1'b1;
111
+ else out_cnt <= out_cnt;
112
+ end
113
+ //---<< bytes counter >>-------------------------------
114
+ //--->> READ LAST <<-----------------------------------
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+ logic native_last;
116
+
117
+ always@(posedge master_inf.aclk,negedge master_inf.aresetn)
118
+ if(~master_inf.aresetn) native_last <= 1'b0;
119
+ else begin
120
+ if(master_inf.axis_tvalid && native_last && master_inf.axis_tready)
121
+ native_last <= 1'b0;
122
+ else if(out_cnt == (r_bytes_total-1) && master_inf.axis_tvalid && master_inf.axis_tready)
123
+ native_last <= 1'b1;
124
+ else native_last <= native_last;
125
+ end
126
+
127
+ assign master_inf.axis_tlast = native_last || r_total_eq_1;
128
+ //---<< READ LAST >>-----------------------------------
129
+ endmodule
@@ -0,0 +1,101 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 解析大块的值域用于 common_frame_table
6
+ author : Cook.Darwin
7
+ Version: VERA.2.0 2017/9/11
8
+ resever value
9
+ Version: VERA.2.0 2017/12/11
10
+ use parse_common_frame_table_A2
11
+ Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
12
+ rebuild
13
+ creaded: 2016/12/22
14
+ madified:
15
+ ***********************************************/
16
+ `timescale 1ns/1ps
17
+ module parse_big_field_table_main #(
18
+ parameter DSIZE = 8,
19
+ parameter FIELD_LEN = 16*8, //MAX 16*8
20
+ parameter START_INDEX = 0
21
+ )(
22
+ output logic[START_INDEX:DSIZE*FIELD_LEN-1] value,
23
+ output logic out_valid,
24
+ axi_stream_inf.slaver cm_tb_s,
25
+ axi_stream_inf.master cm_tb_m
26
+ );
27
+
28
+ localparam VSIZE = $clog2(FIELD_LEN);
29
+
30
+ import SystemPkg::*;
31
+
32
+ initial begin
33
+ assert(DSIZE == cm_tb_s.DSIZE)
34
+ else begin
35
+ $error("DSIZE<%d> != stream.DSIZE<%d>",DSIZE, cm_tb_s.DSIZE);
36
+ end
37
+ end
38
+
39
+ wire clock,rst_n,clken;
40
+
41
+ axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
42
+
43
+ assign clock = cm_tb_s.aclk;
44
+ assign rst_n = cm_tb_s.aresetn;
45
+ assign clken = cm_tb_s.aclken;
46
+
47
+
48
+ assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
49
+ assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
50
+ assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
51
+ assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
52
+ assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
53
+ assign parse_stream.axis_tready= cm_tb_m.axis_tready;
54
+ assign cm_tb_s.axis_tready = cm_tb_m.axis_tready;
55
+
56
+
57
+ logic region_valid;
58
+
59
+ always_ff@(posedge clock,negedge rst_n)begin
60
+ if(~rst_n) region_valid <= 1'b1;
61
+ else begin
62
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
63
+ region_valid <= 1'b1;
64
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
65
+ region_valid <= 1'b0;
66
+ else region_valid <= region_valid;
67
+ end
68
+ end
69
+
70
+
71
+ logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
72
+
73
+ always_ff@(posedge clock,negedge rst_n)begin
74
+ if(~rst_n)
75
+ foreach(value_array[i])
76
+ value_array[i] <= '0;
77
+ else begin
78
+ if(region_valid)begin
79
+ value_array[parse_stream.axis_tcnt[VSIZE-1:0]] <= parse_stream.axis_tdata;
80
+ end
81
+ end
82
+ end
83
+
84
+ assign value = {>>{value_array}};
85
+
86
+ always_ff@(posedge clock,negedge rst_n)begin
87
+ if(~rst_n) out_valid <= 1'b0;
88
+ else begin
89
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
90
+ if(out_valid)
91
+ out_valid <= 1'b0;
92
+ else out_valid <= 1'b1;
93
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
94
+ out_valid <= 1'b1;
95
+ else if(region_valid)
96
+ out_valid <= 1'b0;
97
+ else out_valid <= out_valid;
98
+ end
99
+ end
100
+
101
+ endmodule
@@ -0,0 +1,94 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript: 解析大块的值域用于 common_frame_table
6
+ author : Cook.Darwin
7
+ Version: VERA.2.0 2017/9/11
8
+ resever value
9
+ Version: VERA.2.0 2017/12/11
10
+ use parse_common_frame_table_A2
11
+ Version: VERB.0.0 ###### Tue Oct 20 09:42:34 CST 2020
12
+ rebuild
13
+ creaded: 2016/12/22
14
+ madified:
15
+ ***********************************************/
16
+ `timescale 1ns/1ps
17
+ module parse_big_field_table_mirror #(
18
+ parameter DSIZE = 8,
19
+ parameter FIELD_LEN = 16*8, //MAX 16*8
20
+ parameter START_INDEX = 0
21
+ )(
22
+ output logic[START_INDEX:DSIZE*FIELD_LEN-1] value,
23
+ output logic out_valid,
24
+ axi_stream_inf.mirror cm_mirror
25
+ );
26
+
27
+ localparam VSIZE = $clog2(FIELD_LEN);
28
+
29
+ import SystemPkg::*;
30
+
31
+
32
+ wire clock,rst_n,clken;
33
+
34
+ axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
35
+
36
+
37
+
38
+ assign clock = cm_mirror.aclk;
39
+ assign rst_n = cm_mirror.aresetn;
40
+ assign clken = cm_mirror.aclken;
41
+
42
+ assign parse_stream.axis_tkeep = cm_mirror.axis_tkeep ;
43
+ assign parse_stream.axis_tuser = cm_mirror.axis_tuser ;
44
+ assign parse_stream.axis_tlast = cm_mirror.axis_tlast ;
45
+ assign parse_stream.axis_tdata = cm_mirror.axis_tdata ;
46
+ assign parse_stream.axis_tvalid= cm_mirror.axis_tvalid;
47
+ assign parse_stream.axis_tready= cm_mirror.axis_tready;
48
+
49
+
50
+ logic region_valid;
51
+
52
+ always_ff@(posedge clock,negedge rst_n)begin
53
+ if(~rst_n) region_valid <= 1'b1;
54
+ else begin
55
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
56
+ region_valid <= 1'b1;
57
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
58
+ region_valid <= 1'b0;
59
+ else region_valid <= region_valid;
60
+ end
61
+ end
62
+
63
+
64
+ logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
65
+
66
+ always_ff@(posedge clock,negedge rst_n)begin
67
+ if(~rst_n)
68
+ foreach(value_array[i])
69
+ value_array[i] <= '0;
70
+ else begin
71
+ if(region_valid)begin
72
+ value_array[parse_stream.axis_tcnt[VSIZE-1:0]] <= parse_stream.axis_tdata;
73
+ end
74
+ end
75
+ end
76
+
77
+ assign value = {>>{value_array}};
78
+
79
+ always_ff@(posedge clock,negedge rst_n)begin
80
+ if(~rst_n) out_valid <= 1'b0;
81
+ else begin
82
+ if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
83
+ if(out_valid)
84
+ out_valid <= 1'b0;
85
+ else out_valid <= 1'b1;
86
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
87
+ out_valid <= 1'b1;
88
+ else if(region_valid)
89
+ out_valid <= 1'b0;
90
+ else out_valid <= out_valid;
91
+ end
92
+ end
93
+
94
+ endmodule
@@ -0,0 +1,75 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.1 2017/9/28
8
+ user axi4 addr_step
9
+ Version: VERC.0.0 2018/11/23
10
+ rebuild
11
+ Version: VERC.1.0 ###### Fri Apr 24 10:14:28 CST 2020
12
+ use ddr_native_fifo_verb
13
+ Version: VERC.2.0
14
+ 使用 ddr_native_fifo_B1 具有跨时钟功能
15
+ creaded: 2016/10/12
16
+ madified:
17
+ ***********************************************/
18
+ `timescale 1ns / 1ps
19
+ (* axi4 = "true" *)
20
+ module axi4_to_native_for_ddr_ip_C2 #(
21
+ parameter ADDR_WIDTH = 27,
22
+ parameter DATA_WIDTH = 256
23
+ )(
24
+ axi_inf.slaver ddr3_axi4_inf,
25
+ input ui_clock,
26
+ input ui_rstn,
27
+ output logic[ADDR_WIDTH-1:0] app_addr,
28
+ output logic[2:0] app_cmd,
29
+ output logic app_en,
30
+ output logic[DATA_WIDTH-1:0] app_wdf_data,
31
+ output logic app_wdf_end,
32
+ output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
33
+ output logic app_wdf_wren,
34
+ input [DATA_WIDTH-1:0] app_rd_data,
35
+ input app_rd_data_end,
36
+ input app_rd_data_valid,
37
+ input app_rdy,
38
+ input app_wdf_rdy,
39
+ input logic init_calib_complete
40
+ );
41
+
42
+ axi_stream_inf #(DATA_WIDTH + ADDR_WIDTH + 3) axis_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
43
+ axi_stream_inf #(DATA_WIDTH) axis_rd_inf (ddr3_axi4_inf.axi_aclk,ddr3_axi4_inf.axi_aresetn,1'b1);
44
+
45
+ ddr_axi4_to_axis ddr_axi4_to_axis_inst(
46
+ /* axi4.slaver */ .axi4_inf (ddr3_axi4_inf ),
47
+ /* axi_stream_inf.master */ .axis_inf (axis_inf ),
48
+ /* axi_stream_inf.slaver */ .axis_rd_inf (axis_rd_inf) //DSIZE
49
+ );
50
+
51
+ ddr_native_fifo_B1 #(
52
+ .ADDR_WIDTH (ADDR_WIDTH ),
53
+ .DATA_WIDTH (DATA_WIDTH )
54
+ )ddr_native_fifo_B1_inst(
55
+ /* axi_stream_inf.slaver */ .axis_inf (axis_inf ),
56
+ /* axi_stream_inf.master */ .axis_rd_inf (axis_rd_inf ),
57
+ /* //---DDR IP */
58
+ /* input */ .ui_clock (ui_clock ),
59
+ /* input */ .ui_rstn (ui_rstn ),
60
+ /* output logic[ADDR_WIDTH-1:0] */ .app_addr (app_addr ),
61
+ /* output logic[2:0] */ .app_cmd (app_cmd ),
62
+ /* output logic */ .app_en (app_en ),
63
+ /* output logic[DATA_WIDTH-1:0] */ .app_wdf_data (app_wdf_data ),
64
+ /* output logic */ .app_wdf_end (app_wdf_end ),
65
+ /* output logic[DATA_WIDTH/8-1:0]*/ .app_wdf_mask (app_wdf_mask ),
66
+ /* output logic */ .app_wdf_wren (app_wdf_wren ),
67
+ /* input [DATA_WIDTH-1:0] */ .app_rd_data (app_rd_data ),
68
+ /* input */ .app_rd_data_end (app_rd_data_end ),
69
+ /* input */ .app_rd_data_valid (app_rd_data_valid ),
70
+ /* input */ .app_rdy (app_rdy ),
71
+ /* input */ .app_wdf_rdy (app_wdf_rdy ),
72
+ /* input logic */ .init_calib_complete (init_calib_complete )
73
+ );
74
+
75
+ endmodule