axi_tdl 0.2.0 → 0.2.5
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +46 -28
- data/.github/workflows/ruby.yml +1 -1
- data/.gitignore +2 -1
- data/.travis.yml +1 -0
- data/axi_tdl.gemspec +1 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +5 -3
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +4 -2
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +4 -2
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +173 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +66 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +260 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +192 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +4 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +21 -21
- data/lib/axi/AXI_stream/axi_streams_combin.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +2 -1
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +2 -1
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +2 -1
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +2 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +3 -2
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +163 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +129 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +101 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +94 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +75 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +206 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +297 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +2 -2
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +2 -1
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin.sv +2 -1
- data/lib/axi/data_interface/data_streams_combin_A1.sv +2 -1
- data/lib/axi/data_interface/data_streams_scaler.sv +2 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +5 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +7 -26
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +26 -7
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/rebuild_ele/ele_base.rb +14 -0
- metadata +14 -3
|
@@ -0,0 +1,206 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.1.0
|
|
8
|
+
regenerate axis_rd_inf.axis_tlast
|
|
9
|
+
creaded: 2018/11/26
|
|
10
|
+
madified:
|
|
11
|
+
***********************************************/
|
|
12
|
+
`timescale 1ns / 1ps
|
|
13
|
+
module ddr_native_fifo_A2 #(
|
|
14
|
+
parameter ADDR_WIDTH = 27,
|
|
15
|
+
parameter DATA_WIDTH = 256
|
|
16
|
+
)(
|
|
17
|
+
axi_stream_inf.slaver axis_inf,
|
|
18
|
+
axi_stream_inf.master axis_rd_inf,
|
|
19
|
+
//---DDR IP
|
|
20
|
+
input ui_clock,
|
|
21
|
+
input ui_rstn,
|
|
22
|
+
output logic[ADDR_WIDTH-1:0] app_addr,
|
|
23
|
+
output logic[2:0] app_cmd,
|
|
24
|
+
output logic app_en,
|
|
25
|
+
output logic[DATA_WIDTH-1:0] app_wdf_data,
|
|
26
|
+
output logic app_wdf_end,
|
|
27
|
+
output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
|
|
28
|
+
output logic app_wdf_wren,
|
|
29
|
+
input [DATA_WIDTH-1:0] app_rd_data,
|
|
30
|
+
input app_rd_data_end,
|
|
31
|
+
input app_rd_data_valid,
|
|
32
|
+
input app_rdy,
|
|
33
|
+
input app_wdf_rdy,
|
|
34
|
+
input logic init_calib_complete
|
|
35
|
+
);
|
|
36
|
+
|
|
37
|
+
assign app_wdf_mask = '0;
|
|
38
|
+
assign app_wdf_end = 1'b1;
|
|
39
|
+
|
|
40
|
+
|
|
41
|
+
initial begin
|
|
42
|
+
assert(axis_inf.DSIZE == (ADDR_WIDTH + DATA_WIDTH + 3))
|
|
43
|
+
else begin
|
|
44
|
+
$error("axis_inf.DSIZE#%0d != (3 + ADDR_WIDTH#%0d + DATA_WIDTH#%0d)",axis_inf.DSIZE,ADDR_WIDTH,DATA_WIDTH);
|
|
45
|
+
$stop;
|
|
46
|
+
end
|
|
47
|
+
end
|
|
48
|
+
|
|
49
|
+
logic clock,rst_n;
|
|
50
|
+
assign clock = axis_inf.aclk;
|
|
51
|
+
assign rst_n = axis_inf.aresetn;
|
|
52
|
+
|
|
53
|
+
logic aux_fifo_empty;
|
|
54
|
+
logic aux_fifo_full;
|
|
55
|
+
logic aux_fifo_wr_en;
|
|
56
|
+
logic aux_fifo_rd_en;
|
|
57
|
+
logic [ADDR_WIDTH + 3 -1:0] aux_fifo_wdata,aux_fifo_rdata;
|
|
58
|
+
|
|
59
|
+
independent_clock_fifo #(
|
|
60
|
+
.DEPTH ( 8 ),
|
|
61
|
+
.DSIZE (ADDR_WIDTH + 3 )
|
|
62
|
+
)common_fifo_addr_inst(
|
|
63
|
+
// /* input */ .clock (clock ),
|
|
64
|
+
// /* input */ .rst_n (rst_n ),
|
|
65
|
+
/* input */ .wr_clk (clock ),
|
|
66
|
+
/* input */ .wr_rst_n (rst_n ),
|
|
67
|
+
/* input */ .rd_clk (ui_clock ),
|
|
68
|
+
/* input */ .rd_rst_n (ui_rstn ),
|
|
69
|
+
/* input [DSIZE-1:0] */ .wdata (aux_fifo_wdata ),
|
|
70
|
+
/* input */ .wr_en (aux_fifo_wr_en ),
|
|
71
|
+
/* output logic[DSIZE-1:0] */ .rdata (aux_fifo_rdata ),
|
|
72
|
+
/* input */ .rd_en (aux_fifo_rd_en ),
|
|
73
|
+
/* output logic[CSIZE-1:0] */ .count (),
|
|
74
|
+
/* output logic */ .empty (aux_fifo_empty ),
|
|
75
|
+
/* output logic */ .full (aux_fifo_full )
|
|
76
|
+
);
|
|
77
|
+
|
|
78
|
+
assign aux_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH +: (ADDR_WIDTH+3)];
|
|
79
|
+
assign aux_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready;
|
|
80
|
+
|
|
81
|
+
//-->> DATA
|
|
82
|
+
logic w_fifo_empty;
|
|
83
|
+
logic w_fifo_full;
|
|
84
|
+
logic w_fifo_wr_en;
|
|
85
|
+
logic w_fifo_rd_en;
|
|
86
|
+
logic [DATA_WIDTH-1:0] w_fifo_wdata,w_fifo_rdata;
|
|
87
|
+
|
|
88
|
+
independent_clock_fifo #(
|
|
89
|
+
.DEPTH ( 8 ),
|
|
90
|
+
.DSIZE (DATA_WIDTH )
|
|
91
|
+
)common_fifo_data_inst(
|
|
92
|
+
// /* input */ .clock (clock ),
|
|
93
|
+
// /* input */ .rst_n (rst_n ),
|
|
94
|
+
/* input */ .wr_clk (clock ),
|
|
95
|
+
/* input */ .wr_rst_n (rst_n ),
|
|
96
|
+
/* input */ .rd_clk (ui_clock ),
|
|
97
|
+
/* input */ .rd_rst_n (ui_rstn ),
|
|
98
|
+
/* input [DSIZE-1:0] */ .wdata (w_fifo_wdata ),
|
|
99
|
+
/* input */ .wr_en (w_fifo_wr_en ),
|
|
100
|
+
/* output logic[DSIZE-1:0] */ .rdata (w_fifo_rdata ),
|
|
101
|
+
/* input */ .rd_en (w_fifo_rd_en ),
|
|
102
|
+
/* output logic[CSIZE-1:0] */ .count (),
|
|
103
|
+
/* output logic */ .empty (w_fifo_empty ),
|
|
104
|
+
/* output logic */ .full (w_fifo_full )
|
|
105
|
+
);
|
|
106
|
+
|
|
107
|
+
assign axis_inf.axis_tready = !aux_fifo_full && !w_fifo_full;
|
|
108
|
+
|
|
109
|
+
assign w_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH-1:0];
|
|
110
|
+
assign w_fifo_wr_en = aux_fifo_wr_en && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b000;
|
|
111
|
+
assign app_wdf_data = w_fifo_rdata;
|
|
112
|
+
assign app_wdf_wren = !w_fifo_empty;
|
|
113
|
+
assign w_fifo_rd_en = (app_wdf_wren && app_wdf_rdy);
|
|
114
|
+
|
|
115
|
+
//-- APP
|
|
116
|
+
assign app_en = !aux_fifo_empty;
|
|
117
|
+
assign aux_fifo_rd_en = app_rdy && app_en;
|
|
118
|
+
assign app_cmd = aux_fifo_rdata[ADDR_WIDTH +: 3];
|
|
119
|
+
assign app_addr = aux_fifo_rdata[ADDR_WIDTH-1:0];
|
|
120
|
+
|
|
121
|
+
//-->> STACK
|
|
122
|
+
logic rd_fifo_empty;
|
|
123
|
+
logic rd_fifo_full;
|
|
124
|
+
logic rd_fifo_wr_en;
|
|
125
|
+
logic rd_fifo_rd_en;
|
|
126
|
+
logic [8+2:0] rd_fifo_wdata,rd_fifo_rdata;
|
|
127
|
+
|
|
128
|
+
common_fifo #(
|
|
129
|
+
.DEPTH ( 8 ),
|
|
130
|
+
.DSIZE ( 9+2 )
|
|
131
|
+
)common_fifo_rd_last_inst(
|
|
132
|
+
/* input */ .clock (clock ),
|
|
133
|
+
/* input */ .rst_n (rst_n ),
|
|
134
|
+
/* input [DSIZE-1:0] */ .wdata (rd_fifo_wdata ),
|
|
135
|
+
/* input */ .wr_en (rd_fifo_wr_en ),
|
|
136
|
+
/* output logic[DSIZE-1:0] */ .rdata (rd_fifo_rdata ),
|
|
137
|
+
/* input */ .rd_en (rd_fifo_rd_en ),
|
|
138
|
+
/* output logic[CSIZE-1:0] */ .count (),
|
|
139
|
+
/* output logic */ .empty (rd_fifo_empty ),
|
|
140
|
+
/* output logic */ .full (rd_fifo_full )
|
|
141
|
+
);
|
|
142
|
+
|
|
143
|
+
assign rd_fifo_wdata = {axis_inf.axis_tcnt[8:0]};
|
|
144
|
+
assign rd_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tlast && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
|
|
145
|
+
assign rd_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tlast;
|
|
146
|
+
|
|
147
|
+
// read valid conter
|
|
148
|
+
logic[8+2:0] rd_vld_cnt;
|
|
149
|
+
always@(posedge clock,negedge rst_n)
|
|
150
|
+
if(~rst_n) rd_vld_cnt <= '0;
|
|
151
|
+
else begin
|
|
152
|
+
if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tlast)
|
|
153
|
+
rd_vld_cnt <= '0;
|
|
154
|
+
else if(axis_rd_inf.axis_tvalid)
|
|
155
|
+
rd_vld_cnt <= rd_vld_cnt + 1'b1;
|
|
156
|
+
else rd_vld_cnt <= rd_vld_cnt;
|
|
157
|
+
end
|
|
158
|
+
|
|
159
|
+
always@(posedge clock,negedge rst_n)
|
|
160
|
+
if(~rst_n) axis_rd_inf.axis_tlast <= 1'b0;
|
|
161
|
+
else begin
|
|
162
|
+
if(!rd_fifo_empty && rd_fifo_rdata == '0)
|
|
163
|
+
// if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast && axis_rd_inf.axis_tcnt == '0)
|
|
164
|
+
axis_rd_inf.axis_tlast <= 1'b1;
|
|
165
|
+
else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast)
|
|
166
|
+
axis_rd_inf.axis_tlast <= 1'b0;
|
|
167
|
+
else if(axis_rd_inf.axis_tvalid && rd_vld_cnt >= (rd_fifo_rdata-9'd1) && !rd_fifo_empty)
|
|
168
|
+
axis_rd_inf.axis_tlast <= 1'b1;
|
|
169
|
+
else axis_rd_inf.axis_tlast <= axis_rd_inf.axis_tlast;
|
|
170
|
+
end
|
|
171
|
+
|
|
172
|
+
//-- APP
|
|
173
|
+
// assign axis_rd_inf.axis_tdata = app_rd_data;
|
|
174
|
+
// assign axis_rd_inf.axis_tvalid = app_rd_data_valid;
|
|
175
|
+
assign axis_rd_inf.axis_tkeep = '1;
|
|
176
|
+
assign axis_rd_inf.axis_tuser = '0;
|
|
177
|
+
|
|
178
|
+
wide_fifo #( //min 512 depth
|
|
179
|
+
.DSIZE (DATA_WIDTH )
|
|
180
|
+
)wide_fifo_inst(
|
|
181
|
+
/* input */ .wr_clk (ui_clock ),
|
|
182
|
+
/* input */ .wr_rst (~ui_rstn ),
|
|
183
|
+
/* input */ .rd_clk (clock ),
|
|
184
|
+
/* input */ .rd_rst (~rst_n ),
|
|
185
|
+
/* input [DSIZE-1:0] */ .din (app_rd_data ),
|
|
186
|
+
/* input */ .wr_en (app_rd_data_valid ),
|
|
187
|
+
/* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
|
|
188
|
+
/* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
|
|
189
|
+
/* output */ .full (wide_fifo_full ),
|
|
190
|
+
/* output */ .empty (wide_fifo_empty )
|
|
191
|
+
);
|
|
192
|
+
|
|
193
|
+
assign axis_rd_inf.axis_tvalid = ~wide_fifo_empty;
|
|
194
|
+
|
|
195
|
+
// data overflow
|
|
196
|
+
(* dont_touch = "true" *)logic rd_data_overflow;
|
|
197
|
+
|
|
198
|
+
always@(posedge clock,negedge rst_n)
|
|
199
|
+
if(~rst_n) rd_data_overflow <= 1'b0;
|
|
200
|
+
else begin
|
|
201
|
+
if(axis_rd_inf.axis_tvalid && ~axis_rd_inf.axis_tready)
|
|
202
|
+
rd_data_overflow <= 1'b1;
|
|
203
|
+
else rd_data_overflow <= rd_data_overflow;
|
|
204
|
+
end
|
|
205
|
+
|
|
206
|
+
endmodule
|
|
@@ -0,0 +1,297 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERB.0.0 : ###### Fri Apr 24 10:02:44 CST 2020
|
|
8
|
+
add fifo buffer for read
|
|
9
|
+
creaded: 2018/11/26
|
|
10
|
+
madified: ###### Fri Apr 24 10:02:31 CST 2020
|
|
11
|
+
***********************************************/
|
|
12
|
+
`timescale 1ns / 1ps
|
|
13
|
+
module ddr_native_fifo_B1 #(
|
|
14
|
+
parameter ADDR_WIDTH = 27,
|
|
15
|
+
parameter DATA_WIDTH = 256
|
|
16
|
+
)(
|
|
17
|
+
axi_stream_inf.slaver axis_inf,
|
|
18
|
+
axi_stream_inf.master axis_rd_inf, // 和 axis_inf一个时钟域
|
|
19
|
+
//---DDR IP
|
|
20
|
+
input ui_clock,
|
|
21
|
+
input ui_rstn,
|
|
22
|
+
output logic[ADDR_WIDTH-1:0] app_addr,
|
|
23
|
+
output logic[2:0] app_cmd,
|
|
24
|
+
output logic app_en,
|
|
25
|
+
output logic[DATA_WIDTH-1:0] app_wdf_data,
|
|
26
|
+
output logic app_wdf_end,
|
|
27
|
+
output logic[DATA_WIDTH/8-1:0] app_wdf_mask,
|
|
28
|
+
output logic app_wdf_wren,
|
|
29
|
+
input [DATA_WIDTH-1:0] app_rd_data,
|
|
30
|
+
input app_rd_data_end,
|
|
31
|
+
input app_rd_data_valid,
|
|
32
|
+
input app_rdy,
|
|
33
|
+
input app_wdf_rdy,
|
|
34
|
+
input logic init_calib_complete
|
|
35
|
+
);
|
|
36
|
+
|
|
37
|
+
assign app_wdf_mask = '0;
|
|
38
|
+
assign app_wdf_end = 1'b1;
|
|
39
|
+
|
|
40
|
+
|
|
41
|
+
initial begin
|
|
42
|
+
assert(axis_inf.DSIZE == (ADDR_WIDTH + DATA_WIDTH + 3))
|
|
43
|
+
else begin
|
|
44
|
+
$error("axis_inf.DSIZE#%0d != (3 + ADDR_WIDTH#%0d + DATA_WIDTH#%0d)",axis_inf.DSIZE,ADDR_WIDTH,DATA_WIDTH);
|
|
45
|
+
$stop;
|
|
46
|
+
end
|
|
47
|
+
end
|
|
48
|
+
|
|
49
|
+
logic clock,rst_n;
|
|
50
|
+
assign clock = axis_inf.aclk;
|
|
51
|
+
assign rst_n = axis_inf.aresetn;
|
|
52
|
+
|
|
53
|
+
logic aux_fifo_empty;
|
|
54
|
+
logic aux_fifo_full;
|
|
55
|
+
logic aux_fifo_wr_en;
|
|
56
|
+
logic aux_fifo_rd_en;
|
|
57
|
+
logic [ADDR_WIDTH + 3 -1:0] aux_fifo_wdata,aux_fifo_rdata;
|
|
58
|
+
|
|
59
|
+
independent_clock_fifo #(
|
|
60
|
+
.DEPTH ( 8 ),
|
|
61
|
+
.DSIZE (ADDR_WIDTH + 3 )
|
|
62
|
+
)independent_clock_fifo_addr_inst(
|
|
63
|
+
// /* input */ .clock (clock ),
|
|
64
|
+
// /* input */ .rst_n (rst_n ),
|
|
65
|
+
/* input */ .wr_clk (clock ),
|
|
66
|
+
/* input */ .wr_rst_n (rst_n ),
|
|
67
|
+
/* input */ .rd_clk (ui_clock ),
|
|
68
|
+
/* input */ .rd_rst_n (ui_rstn ),
|
|
69
|
+
/* input [DSIZE-1:0] */ .wdata (aux_fifo_wdata ),
|
|
70
|
+
/* input */ .wr_en (aux_fifo_wr_en ),
|
|
71
|
+
/* output logic[DSIZE-1:0] */ .rdata (aux_fifo_rdata ),
|
|
72
|
+
/* input */ .rd_en (aux_fifo_rd_en ),
|
|
73
|
+
/* output logic */ .empty (aux_fifo_empty ),
|
|
74
|
+
/* output logic */ .full (aux_fifo_full )
|
|
75
|
+
);
|
|
76
|
+
|
|
77
|
+
assign aux_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH +: (ADDR_WIDTH+3)];
|
|
78
|
+
assign aux_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready;
|
|
79
|
+
|
|
80
|
+
//-->> DATA
|
|
81
|
+
logic w_fifo_empty;
|
|
82
|
+
logic w_fifo_full;
|
|
83
|
+
logic w_fifo_wr_en;
|
|
84
|
+
logic w_fifo_rd_en;
|
|
85
|
+
logic [DATA_WIDTH-1:0] w_fifo_wdata,w_fifo_rdata;
|
|
86
|
+
|
|
87
|
+
logic rd_atom_fifo_full;
|
|
88
|
+
|
|
89
|
+
independent_clock_fifo #(
|
|
90
|
+
.DEPTH ( 8 ),
|
|
91
|
+
.DSIZE (DATA_WIDTH )
|
|
92
|
+
)independent_clock_fifo_data_inst(
|
|
93
|
+
// /* input */ .clock (clock ),
|
|
94
|
+
// /* input */ .rst_n (rst_n ),
|
|
95
|
+
/* input */ .wr_clk (clock ),
|
|
96
|
+
/* input */ .wr_rst_n (rst_n ),
|
|
97
|
+
/* input */ .rd_clk (ui_clock ),
|
|
98
|
+
/* input */ .rd_rst_n (ui_rstn ),
|
|
99
|
+
/* input [DSIZE-1:0] */ .wdata (w_fifo_wdata ),
|
|
100
|
+
/* input */ .wr_en (w_fifo_wr_en ),
|
|
101
|
+
/* output logic[DSIZE-1:0] */ .rdata (w_fifo_rdata ),
|
|
102
|
+
/* input */ .rd_en (w_fifo_rd_en ),
|
|
103
|
+
/* output logic */ .empty (w_fifo_empty ),
|
|
104
|
+
/* output logic */ .full (w_fifo_full )
|
|
105
|
+
);
|
|
106
|
+
|
|
107
|
+
assign axis_inf.axis_tready = !aux_fifo_full && !w_fifo_full && !rd_atom_fifo_full;
|
|
108
|
+
|
|
109
|
+
assign w_fifo_wdata = axis_inf.axis_tdata[DATA_WIDTH-1:0];
|
|
110
|
+
assign w_fifo_wr_en = aux_fifo_wr_en && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b000;
|
|
111
|
+
assign app_wdf_data = w_fifo_rdata;
|
|
112
|
+
assign app_wdf_wren = !w_fifo_empty;
|
|
113
|
+
assign w_fifo_rd_en = (app_wdf_wren && app_wdf_rdy);
|
|
114
|
+
|
|
115
|
+
//-- APP
|
|
116
|
+
assign app_en = !aux_fifo_empty;
|
|
117
|
+
assign aux_fifo_rd_en = app_rdy && app_en;
|
|
118
|
+
assign app_cmd = aux_fifo_rdata[ADDR_WIDTH +: 3];
|
|
119
|
+
assign app_addr = aux_fifo_rdata[ADDR_WIDTH-1:0];
|
|
120
|
+
|
|
121
|
+
//-->> STACK
|
|
122
|
+
logic rd_fifo_empty;
|
|
123
|
+
// (* dont_touch="true" *)(* mark_debug="true" *)
|
|
124
|
+
logic rd_fifo_full_error; // when rd_fifo_full high meet that error raising
|
|
125
|
+
logic rd_fifo_wr_en;
|
|
126
|
+
logic rd_fifo_rd_en;
|
|
127
|
+
logic [15:0] rd_fifo_wdata,rd_fifo_rdata;
|
|
128
|
+
// (* dont_touch="true" *)(* mark_debug="true" *)
|
|
129
|
+
logic [16:0] rd_fifo_count;
|
|
130
|
+
|
|
131
|
+
common_fifo #(
|
|
132
|
+
.DEPTH ( 8 ),
|
|
133
|
+
.DSIZE ( 16 )
|
|
134
|
+
)common_fifo_rd_last_inst(
|
|
135
|
+
/* input */ .clock (clock ),
|
|
136
|
+
/* input */ .rst_n (rst_n ),
|
|
137
|
+
// /* input */ .wr_clk (clock ),
|
|
138
|
+
// /* input */ .wr_rst_n (rst_n ),
|
|
139
|
+
// /* input */ .rd_clk (ui_clock ),
|
|
140
|
+
// /* input */ .rd_rst_n (ui_rstn ),
|
|
141
|
+
/* input [DSIZE-1:0] */ .wdata (rd_fifo_wdata ),
|
|
142
|
+
/* input */ .wr_en (rd_fifo_wr_en ),
|
|
143
|
+
/* output logic[DSIZE-1:0] */ .rdata (rd_fifo_rdata ),
|
|
144
|
+
/* input */ .rd_en (rd_fifo_rd_en ),
|
|
145
|
+
/* output logic[CSIZE-1:0] */ .count (rd_fifo_count ),
|
|
146
|
+
/* output logic */ .empty (rd_fifo_empty ),
|
|
147
|
+
/* output logic */ .full (rd_fifo_full_error )
|
|
148
|
+
);
|
|
149
|
+
|
|
150
|
+
assign rd_fifo_wdata = {axis_inf.axis_tcnt[15:0]};
|
|
151
|
+
assign rd_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tlast && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
|
|
152
|
+
assign rd_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast;
|
|
153
|
+
|
|
154
|
+
always@(posedge clock,negedge rst_n)
|
|
155
|
+
if(~rst_n) axis_rd_inf.axis_tlast <= 1'b0;
|
|
156
|
+
else begin
|
|
157
|
+
if(!rd_fifo_empty && rd_fifo_rdata == '0)
|
|
158
|
+
// if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast && axis_rd_inf.axis_tcnt == '0)
|
|
159
|
+
axis_rd_inf.axis_tlast <= 1'b1;
|
|
160
|
+
else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tcnt == (rd_fifo_rdata-9'd1) && !rd_fifo_empty)
|
|
161
|
+
axis_rd_inf.axis_tlast <= 1'b1;
|
|
162
|
+
else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && axis_rd_inf.axis_tlast)
|
|
163
|
+
axis_rd_inf.axis_tlast <= 1'b0;
|
|
164
|
+
else axis_rd_inf.axis_tlast <= axis_rd_inf.axis_tlast;
|
|
165
|
+
end
|
|
166
|
+
|
|
167
|
+
//-- APP
|
|
168
|
+
//-- >> READ BUFFER
|
|
169
|
+
// assign axis_rd_inf.axis_tdata = app_rd_data;
|
|
170
|
+
// assign axis_rd_inf.axis_tvalid = app_rd_data_valid;
|
|
171
|
+
// assign axis_rd_inf.axis_tkeep = '1;
|
|
172
|
+
// assign axis_rd_inf.axis_tuser = '0;
|
|
173
|
+
|
|
174
|
+
// contrl cmd exec
|
|
175
|
+
// logic rd_atom_fifo_wdata
|
|
176
|
+
logic rd_atom_fifo_wr_en;
|
|
177
|
+
// logic rd_atom_fifo_rdata
|
|
178
|
+
logic rd_atom_fifo_rd_en;
|
|
179
|
+
// logic rd_atom_fifo_count
|
|
180
|
+
logic rd_atom_fifo_empty;
|
|
181
|
+
// logic rd_atom_fifo_full
|
|
182
|
+
|
|
183
|
+
common_fifo #(
|
|
184
|
+
.DEPTH ( 256 ),
|
|
185
|
+
.DSIZE ( 1 )
|
|
186
|
+
)common_fifo_rd_cmd_inst(
|
|
187
|
+
/* input */ .clock (clock ),
|
|
188
|
+
/* input */ .rst_n (rst_n ),
|
|
189
|
+
/* input [DSIZE-1:0] */ .wdata (1'b0 ),
|
|
190
|
+
/* input */ .wr_en (rd_atom_fifo_wr_en ),
|
|
191
|
+
/* output logic[DSIZE-1:0] */ .rdata ( ),
|
|
192
|
+
/* input */ .rd_en (rd_atom_fifo_rd_en ),
|
|
193
|
+
/* output logic[CSIZE-1:0] */ .count ( ),
|
|
194
|
+
/* output logic */ .empty (rd_atom_fifo_empty ),
|
|
195
|
+
/* output logic */ .full (rd_atom_fifo_full )
|
|
196
|
+
);
|
|
197
|
+
|
|
198
|
+
assign rd_atom_fifo_wr_en = axis_inf.axis_tvalid && axis_inf.axis_tready && axis_inf.axis_tdata[(DATA_WIDTH + ADDR_WIDTH) +: 3] == 3'b001;
|
|
199
|
+
assign rd_atom_fifo_rd_en = axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready;
|
|
200
|
+
|
|
201
|
+
// (* dont_touch="true" *)(* mark_debug="true" *)
|
|
202
|
+
logic wide_fifo_full;
|
|
203
|
+
logic wide_fifo_empty;
|
|
204
|
+
|
|
205
|
+
// wide_fifo #( //min 512 depth
|
|
206
|
+
// .DSIZE (DATA_WIDTH )
|
|
207
|
+
// )wide_fifo_inst(
|
|
208
|
+
// /* input */ .wr_clk (ui_clock ),
|
|
209
|
+
// /* input */ .wr_rst (~ui_rstn ),
|
|
210
|
+
// /* input */ .rd_clk (clock ),
|
|
211
|
+
// /* input */ .rd_rst (~rst_n ),
|
|
212
|
+
// /* input [DSIZE-1:0] */ .din (app_rd_data ),
|
|
213
|
+
// /* input */ .wr_en (app_rd_data_valid ),
|
|
214
|
+
// /* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
|
|
215
|
+
// /* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
|
|
216
|
+
// /* output */ .full (wide_fifo_full ),
|
|
217
|
+
// /* output */ .empty (wide_fifo_empty )
|
|
218
|
+
// );
|
|
219
|
+
|
|
220
|
+
long_fifo_verb #(
|
|
221
|
+
.DSIZE (DATA_WIDTH),
|
|
222
|
+
.LENGTH (1024*2)
|
|
223
|
+
)long_fifo_verb_inst(
|
|
224
|
+
/* input */ .wr_clk (ui_clock ),
|
|
225
|
+
/* input */ .wr_rst (~ui_rstn ),
|
|
226
|
+
/* input */ .rd_clk (clock ),
|
|
227
|
+
/* input */ .rd_rst (~rst_n ),
|
|
228
|
+
/* input [DSIZE-1:0] */ .din (app_rd_data ),
|
|
229
|
+
/* input */ .wr_en (app_rd_data_valid ),
|
|
230
|
+
/* input */ .rd_en (axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready ),
|
|
231
|
+
/* output [DSIZE-1:0] */ .dout (axis_rd_inf.axis_tdata ),
|
|
232
|
+
/* output */ .full (wide_fifo_full ),
|
|
233
|
+
/* output */ .empty (wide_fifo_empty )
|
|
234
|
+
);
|
|
235
|
+
|
|
236
|
+
assign axis_rd_inf.axis_tvalid = ~wide_fifo_empty;
|
|
237
|
+
|
|
238
|
+
// TRACK
|
|
239
|
+
`ifdef TRACK_DDR3_STREAM
|
|
240
|
+
(* dont_touch="true" *)(* mark_debug="true" *)
|
|
241
|
+
logic[10:0] track_native_rd_cnt;
|
|
242
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
243
|
+
if(~rst_n) track_native_rd_cnt <= '0;
|
|
244
|
+
else begin
|
|
245
|
+
if(app_en && app_cmd==3'b001 && app_rdy && app_rd_data_valid)
|
|
246
|
+
track_native_rd_cnt <= track_native_rd_cnt;
|
|
247
|
+
else if(app_en && app_cmd==3'b001 && app_rdy)
|
|
248
|
+
track_native_rd_cnt <= track_native_rd_cnt + 1'b1;
|
|
249
|
+
else if(app_rd_data_valid)
|
|
250
|
+
track_native_rd_cnt <= track_native_rd_cnt - 1'b1;
|
|
251
|
+
else track_native_rd_cnt <= track_native_rd_cnt;
|
|
252
|
+
end
|
|
253
|
+
end
|
|
254
|
+
|
|
255
|
+
(* dont_touch="true" *)(* mark_debug="true" *)
|
|
256
|
+
logic[10:0] track_axis_rd_cnt;
|
|
257
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
258
|
+
if(~rst_n) track_axis_rd_cnt <= '0;
|
|
259
|
+
else begin
|
|
260
|
+
if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready && app_rd_data_valid)
|
|
261
|
+
track_axis_rd_cnt <= track_axis_rd_cnt;
|
|
262
|
+
else if(axis_rd_inf.axis_tvalid && axis_rd_inf.axis_tready)
|
|
263
|
+
track_axis_rd_cnt <= track_axis_rd_cnt - 1'b1;
|
|
264
|
+
else if(app_rd_data_valid)
|
|
265
|
+
track_axis_rd_cnt <= track_axis_rd_cnt + 1'b1;
|
|
266
|
+
else track_axis_rd_cnt <= track_axis_rd_cnt;
|
|
267
|
+
end
|
|
268
|
+
end
|
|
269
|
+
`endif
|
|
270
|
+
|
|
271
|
+
// `define TRACK_DDR3_APP
|
|
272
|
+
`ifdef TRACK_DDR3_APP
|
|
273
|
+
(* dont_touch="true" *)(* mark_debug="true" *)
|
|
274
|
+
logic [9:0] app_en_wr_cnt;
|
|
275
|
+
(* dont_touch="true" *)(* mark_debug="true" *)
|
|
276
|
+
logic [9:0] app_wdf_wren_cnt;
|
|
277
|
+
|
|
278
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
279
|
+
if(~rst_n) app_en_wr_cnt <= '0;
|
|
280
|
+
else begin
|
|
281
|
+
if(app_en && app_cmd==3'b000 && app_rdy)
|
|
282
|
+
app_en_wr_cnt <= app_en_wr_cnt + 1'b1 ;
|
|
283
|
+
else app_en_wr_cnt <= app_en_wr_cnt;
|
|
284
|
+
end
|
|
285
|
+
end
|
|
286
|
+
|
|
287
|
+
always_ff@(posedge clock,negedge rst_n)begin
|
|
288
|
+
if(~rst_n) app_wdf_wren_cnt <= '0;
|
|
289
|
+
else begin
|
|
290
|
+
if(app_wdf_rdy && app_wdf_wren)
|
|
291
|
+
app_wdf_wren_cnt <= app_wdf_wren_cnt + 1'b1;
|
|
292
|
+
else app_wdf_wren_cnt <= app_wdf_wren_cnt;
|
|
293
|
+
end
|
|
294
|
+
end
|
|
295
|
+
`endif
|
|
296
|
+
|
|
297
|
+
endmodule
|
|
@@ -115,8 +115,8 @@ task automatic write_cmd ();
|
|
|
115
115
|
endtask:write_cmd
|
|
116
116
|
|
|
117
117
|
task automatic write_data ();
|
|
118
|
-
|
|
119
|
-
|
|
118
|
+
bit [ADDR_WIDTH-1:0] addr;
|
|
119
|
+
bit [DATA_WIDTH-1:0] data;
|
|
120
120
|
fork
|
|
121
121
|
forever begin
|
|
122
122
|
forever begin
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
creaded:
|
|
8
|
+
creaded:
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
|
|
|
48
48
|
endgenerate
|
|
49
49
|
//-------- CLOCKs Total 2 ----------------------
|
|
50
50
|
//--->> CheckClock <<----------------
|
|
51
|
-
logic
|
|
52
|
-
integer
|
|
53
|
-
ClockSameDomain
|
|
51
|
+
logic cc_done_28,cc_same_28;
|
|
52
|
+
integer cc_afreq_28,cc_bfreq_28;
|
|
53
|
+
ClockSameDomain CheckPClock_inst_28(
|
|
54
54
|
/* input */ .aclk (in_inf.clock ),
|
|
55
55
|
/* input */ .bclk (out_inf.clock ),
|
|
56
|
-
/* output logic */ .done (
|
|
57
|
-
/* output logic */ .same (
|
|
58
|
-
/* output integer */ .aFreqK (
|
|
59
|
-
/* output integer */ .bFreqK (
|
|
56
|
+
/* output logic */ .done (cc_done_28),
|
|
57
|
+
/* output logic */ .same (cc_same_28),
|
|
58
|
+
/* output integer */ .aFreqK (cc_afreq_28),
|
|
59
|
+
/* output integer */ .bFreqK (cc_bfreq_28)
|
|
60
60
|
);
|
|
61
61
|
|
|
62
62
|
initial begin
|
|
63
|
-
wait(
|
|
64
|
-
assert(
|
|
63
|
+
wait(cc_done_28);
|
|
64
|
+
assert(cc_same_28)
|
|
65
65
|
else begin
|
|
66
|
-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
|
|
66
|
+
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_28, 1000000.0/cc_bfreq_28);
|
|
67
67
|
repeat(10)begin
|
|
68
68
|
@(posedge in_inf.clock);
|
|
69
69
|
end
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
creaded: 2018-4-13 12:39:59
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.1.0 2018-4-16 12:04:47
|
|
7
8
|
add trigger
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from data_streams_scaler VA.0.1
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.0
|
|
7
8
|
build from data_streams_scaler VA.0.1
|
|
@@ -1,7 +1,8 @@
|
|
|
1
1
|
/**********************************************
|
|
2
2
|
_______________________________________
|
|
3
3
|
___________ Cook Darwin __________
|
|
4
|
-
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
5
6
|
author : Cook.Darwin
|
|
6
7
|
Version: VERA.0.1
|
|
7
8
|
Version: VERA.0.2 2018-4-12 15:42:15
|
data/lib/axi_tdl/version.rb
CHANGED
|
@@ -228,7 +228,7 @@ class Axi4
|
|
|
228
228
|
curr_quanti_len = e.dsize.real_data * (2**e.lsize.real_data)
|
|
229
229
|
if(curr_quanti_len > root_quanti_len )
|
|
230
230
|
# if(true )
|
|
231
|
-
new_master = self.copy(mode:e.mode,idsize:e.idsize+4)
|
|
231
|
+
new_master = self.copy(mode:e.mode,idsize:e.idsize+4,name: "#{self.name}_long_slim_to_wide_#{globle_random_name_flag('axi_intc')}" )
|
|
232
232
|
new_master.mode = e.mode
|
|
233
233
|
|
|
234
234
|
require_hdl 'axi4_long_to_axi4_wide_B1.sv'
|
|
@@ -236,6 +236,8 @@ class Axi4
|
|
|
236
236
|
TopModule.contain_hdl 'axi4_packet_fifo_verb.sv'
|
|
237
237
|
TopModule.contain_hdl 'axi4_data_convert_verb.sv'
|
|
238
238
|
TopModule.contain_hdl 'data_c_pipe_force_vld.sv'
|
|
239
|
+
TopModule.contain_hdl 'axi4_packet_fifo_B1.sv','axi4_rd_packet_fifo_A1.sv','axi4_wr_packet_fifo_A1.sv','axi_stream_packet_fifo_B1F.sv'
|
|
240
|
+
|
|
239
241
|
|
|
240
242
|
belong_to_module.Instance(:axi4_long_to_axi4_wide_B1,"axi4_long_to_axi4_wide_B1_#{index}_inst") do |h|
|
|
241
243
|
h[:PARTITION] = "ON"
|
|
@@ -254,6 +256,8 @@ class Axi4
|
|
|
254
256
|
TopModule.contain_hdl 'axi4_packet_fifo_verb.sv'
|
|
255
257
|
TopModule.contain_hdl 'axi4_data_convert_verb.sv'
|
|
256
258
|
TopModule.contain_hdl 'data_c_pipe_force_vld.sv'
|
|
259
|
+
TopModule.contain_hdl 'axi4_packet_fifo_B1.sv','axi4_rd_packet_fifo_A1.sv','axi4_wr_packet_fifo_A1.sv','axi_stream_packet_fifo_B1F.sv'
|
|
260
|
+
|
|
257
261
|
# puts "#{e.dsize} == #{self.dsize} #{e.dsize != self.dsize} #{e.dsize.class}"
|
|
258
262
|
new_master = self.copy(name: "#{e.name}_renew_dir",mode:e.mode,idsize:e.idsize)
|
|
259
263
|
# new_master.axi4_data_convert(up_stream: e)
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2023-08-16 21:22:47 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module test_module_var #(
|
|
|
19
19
|
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
|
-
localparam ASIZE = 20
|
|
22
|
+
localparam ASIZE = 20;
|
|
23
23
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
24
|
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
25
|
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|