axi_tdl 0.1.8 → 0.1.19

data/lib/tdl/rebuild_ele/axi_stream.rb

@@ -62,7 +62,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
     def inherited(name: nil ,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
         a = nil 
         unless name 
-            name = "#{inst_name}_inherited#{globle_random_name_flag()}"
+            name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
         end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
             append_name = name_copy(name)
@@ -88,7 +88,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
 
     ## =======================
     def self.leave_empty(curr_type: :master,dsize:8,clock:"",reset:"",belong_to_module:nil)
-        nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{globle_random_name_flag()}"
+        nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{belong_to_module._auto_name_incr_index_()}"
         # puts belong_to_module.module_name
         if curr_type.to_sym == :slaver
             # self.axis_master_empty(master:nc)
@@ -109,7 +109,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
 
     def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
         unless name 
-            name = "#{inst_name}_branch#{globle_random_name_flag()}"
+            name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
         end
         a =  inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
         self << a

data/lib/tdl/rebuild_ele/data_inf_c.rb

@@ -41,7 +41,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
     def inherited(name: nil,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
         a = nil 
         unless name 
-            name = "#{inst_name}_inherited#{globle_random_name_flag()}"
+            name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
         end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
             append_name = name_copy(name)
@@ -71,7 +71,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
 
     def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
         unless name 
-            name = "#{inst_name}_branch#{globle_random_name_flag()}"
+            name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
         end
         a =  inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
         self << a

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -411,7 +411,11 @@ class SdlModule
         ref_modules.each do |e| 
             _indexs << index 
             _names << e.module_name
-            _paths << File.expand_path(e.real_sv_path)
+            begin 
+                _paths << File.expand_path(e.real_sv_path)
+            rescue 
+                _paths << " ___ dont have a path !!!!! ____"
+            end
             index += 1
             if e.module_name.size > max_size
                 max_size = e.module_name.size 
@@ -539,3 +543,15 @@ class SdlModule
         end
     end
 end
+
+## 定义自动变量递增
+class SdlModule
+
+    def _auto_name_incr_index_(flag='R')
+        @__auto_name_incr_index__ ||= 0
+        index = @__auto_name_incr_index__
+        @__auto_name_incr_index__ += 1
+        return "#{flag}#{"%04d" % index}" 
+    end
+
+end

data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb

@@ -81,7 +81,7 @@ module VCSCompatable
     # end
 
     def self.common_instance(sdlmodule,inst_name,inst_modport,cn_modport)
-        vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{globle_random_name_flag()}")
+        vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{sdlmodule._auto_name_incr_index_()}")
         if vcs_cpt_inf.is_a? Axi4 
             # vcs_cpt_inf.origin_freqM   = cn_modport.FreqM
             vcs_cpt_inf.addr_step = cn_modport.ADDR_STEP 
@@ -90,7 +90,7 @@ module VCSCompatable
     
         if inst_modport.modport_type.to_s =~ /master/ || inst_modport.modport_type.to_s == "out_mirror"
             # puts "+++++++ Match Master ModPort ++++++ #{sdlmodule.module_name}"
-            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
+            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
                 h[:ORIGIN]  = "#{inst_modport.modport_type}"
                 h[:TO]      = "#{cn_modport.modport_type}" 
                 h[:origin]  = vcs_cpt_inf
@@ -98,7 +98,7 @@ module VCSCompatable
             end
         elsif inst_modport.modport_type.to_s =~ /slaver/ || inst_modport.modport_type.to_s =~ /mirror/
             # puts "+++++++ Match Slaver ModPort ++++++"
-            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
+            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
                 h[:TO]      = "#{inst_modport.modport_type}"
                 h[:ORIGIN]  = "#{cn_modport.modport_type}" 
                 h[:to]      = vcs_cpt_inf

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -20,7 +20,9 @@ class SdlModule
         @__track_signals_hash__[flag] ||= Hash.new
 
         if @__track_signals_hash__[flag].has_key?(base_ele)
-            raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
+            # raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
+            puts "WAINNING: `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!"
+            return 
         end
 
         @__track_signals_hash__[flag][base_ele] = block

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.1.8
+  version: 0.1.19
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-05-30 00:00:00.000000000 Z
+date: 2021-09-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -91,9 +91,12 @@ files:
 - lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv
 - lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv
 - lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv
+- lib/axi/AXI4/axi4_ram_cache.rb
+- lib/axi/AXI4/axi4_ram_cache.sv
 - lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv
 - lib/axi/AXI4/axi4_rd_auxiliary_gen.sv
 - lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv
+- lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv
 - lib/axi/AXI4/axi4_rd_burst_track.sv
 - lib/axi/AXI4/axi4_wr_aux_bind_data.sv
 - lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv
@@ -120,6 +123,8 @@ files:
 - lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv
 - lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv
 - lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak
+- lib/axi/AXI4/long_axis_to_axi4_wr.rb
+- lib/axi/AXI4/long_axis_to_axi4_wr.sv
 - lib/axi/AXI4/odata_pool_axi4.sv
 - lib/axi/AXI4/odata_pool_axi4_A1.sv
 - lib/axi/AXI4/odata_pool_axi4_A2.sv