axi_tdl 0.1.8 → 0.1.19

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Files changed (47) hide show
  1. checksums.yaml +4 -4
  2. data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
  3. data/lib/axi/AXI4/axi4_dpram_cache.rb +2 -2
  4. data/lib/axi/AXI4/axi4_dpram_cache.sv +3 -3
  5. data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
  6. data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
  7. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
  8. data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
  9. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
  10. data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
  11. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
  12. data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +5 -5
  15. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
  16. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
  17. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -23
  18. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
  19. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  20. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  21. data/lib/axi_tdl/version.rb +1 -1
  22. data/lib/tdl/Logic/logic_edge.rb +14 -6
  23. data/lib/tdl/Logic/logic_latency.rb +7 -7
  24. data/lib/tdl/auto_script/import_hdl.rb +1 -0
  25. data/lib/tdl/auto_script/import_sdl.rb +43 -1
  26. data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
  27. data/lib/tdl/class_hdl/hdl_data.rb +1 -1
  28. data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
  29. data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
  30. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
  31. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
  32. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
  33. data/lib/tdl/examples/11_test_unit/tu0.sv +3 -6
  34. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  35. data/lib/tdl/examples/9_itegration/dve.tcl +6 -153
  36. data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
  37. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
  38. data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
  39. data/lib/tdl/exlib/axis_verify.rb +2 -2
  40. data/lib/tdl/exlib/logic_verify.rb +1 -1
  41. data/lib/tdl/rebuild_ele/axi4.rb +6 -2
  42. data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
  43. data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
  44. data/lib/tdl/sdlmodule/sdlmodule.rb +17 -1
  45. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
  46. data/lib/tdl/sdlmodule/test_unit_module.rb +3 -1
  47. metadata +7 -2
@@ -62,7 +62,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
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  def inherited(name: nil ,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
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  a = nil
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  unless name
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- name = "#{inst_name}_inherited#{globle_random_name_flag()}"
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+ name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
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  end
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  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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  append_name = name_copy(name)
@@ -88,7 +88,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
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  ## =======================
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  def self.leave_empty(curr_type: :master,dsize:8,clock:"",reset:"",belong_to_module:nil)
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- nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{globle_random_name_flag()}"
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+ nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{belong_to_module._auto_name_incr_index_()}"
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  # puts belong_to_module.module_name
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  if curr_type.to_sym == :slaver
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  # self.axis_master_empty(master:nc)
@@ -109,7 +109,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
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  def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
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  unless name
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- name = "#{inst_name}_branch#{globle_random_name_flag()}"
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+ name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
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  end
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  a = inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
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  self << a
@@ -41,7 +41,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
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  def inherited(name: nil,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
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  a = nil
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  unless name
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- name = "#{inst_name}_inherited#{globle_random_name_flag()}"
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+ name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
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  end
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  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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  append_name = name_copy(name)
@@ -71,7 +71,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
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  def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
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  unless name
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- name = "#{inst_name}_branch#{globle_random_name_flag()}"
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+ name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
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  end
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  a = inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
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  self << a
@@ -411,7 +411,11 @@ class SdlModule
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  ref_modules.each do |e|
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  _indexs << index
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  _names << e.module_name
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- _paths << File.expand_path(e.real_sv_path)
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+ begin
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+ _paths << File.expand_path(e.real_sv_path)
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+ rescue
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+ _paths << " ___ dont have a path !!!!! ____"
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+ end
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  index += 1
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  if e.module_name.size > max_size
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  max_size = e.module_name.size
@@ -539,3 +543,15 @@ class SdlModule
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  end
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  end
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  end
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+
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+ ## 定义自动变量递增
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+ class SdlModule
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+
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+ def _auto_name_incr_index_(flag='R')
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+ @__auto_name_incr_index__ ||= 0
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+ index = @__auto_name_incr_index__
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+ @__auto_name_incr_index__ += 1
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+ return "#{flag}#{"%04d" % index}"
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+ end
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+
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+ end
@@ -81,7 +81,7 @@ module VCSCompatable
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  # end
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  def self.common_instance(sdlmodule,inst_name,inst_modport,cn_modport)
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- vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{globle_random_name_flag()}")
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+ vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{sdlmodule._auto_name_incr_index_()}")
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  if vcs_cpt_inf.is_a? Axi4
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  # vcs_cpt_inf.origin_freqM = cn_modport.FreqM
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  vcs_cpt_inf.addr_step = cn_modport.ADDR_STEP
@@ -90,7 +90,7 @@ module VCSCompatable
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  if inst_modport.modport_type.to_s =~ /master/ || inst_modport.modport_type.to_s == "out_mirror"
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  # puts "+++++++ Match Master ModPort ++++++ #{sdlmodule.module_name}"
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- sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
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+ sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
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  h[:ORIGIN] = "#{inst_modport.modport_type}"
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  h[:TO] = "#{cn_modport.modport_type}"
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  h[:origin] = vcs_cpt_inf
@@ -98,7 +98,7 @@ module VCSCompatable
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  end
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  elsif inst_modport.modport_type.to_s =~ /slaver/ || inst_modport.modport_type.to_s =~ /mirror/
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  # puts "+++++++ Match Slaver ModPort ++++++"
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- sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
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+ sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
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  h[:TO] = "#{inst_modport.modport_type}"
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  h[:ORIGIN] = "#{cn_modport.modport_type}"
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  h[:to] = vcs_cpt_inf
@@ -20,7 +20,9 @@ class SdlModule
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  @__track_signals_hash__[flag] ||= Hash.new
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22
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  if @__track_signals_hash__[flag].has_key?(base_ele)
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- raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
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+ # raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
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+ puts "WAINNING: `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!"
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+ return
24
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  end
25
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  @__track_signals_hash__[flag][base_ele] = block
metadata CHANGED
@@ -1,14 +1,14 @@
1
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  --- !ruby/object:Gem::Specification
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  name: axi_tdl
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  version: !ruby/object:Gem::Version
4
- version: 0.1.8
4
+ version: 0.1.19
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  platform: ruby
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  authors:
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  - Cook.Darwin
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  autorequire:
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  bindir: exe
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  cert_chain: []
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- date: 2021-05-30 00:00:00.000000000 Z
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+ date: 2021-09-24 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rake
@@ -91,9 +91,12 @@ files:
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  - lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv
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  - lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv
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  - lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv
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+ - lib/axi/AXI4/axi4_ram_cache.rb
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+ - lib/axi/AXI4/axi4_ram_cache.sv
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  - lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv
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  - lib/axi/AXI4/axi4_rd_auxiliary_gen.sv
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  - lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv
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+ - lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv
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  - lib/axi/AXI4/axi4_rd_burst_track.sv
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  - lib/axi/AXI4/axi4_wr_aux_bind_data.sv
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  - lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv
@@ -120,6 +123,8 @@ files:
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  - lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv
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  - lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv
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  - lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak
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+ - lib/axi/AXI4/long_axis_to_axi4_wr.rb
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+ - lib/axi/AXI4/long_axis_to_axi4_wr.sv
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  - lib/axi/AXI4/odata_pool_axi4.sv
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  - lib/axi/AXI4/odata_pool_axi4_A1.sv
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  - lib/axi/AXI4/odata_pool_axi4_A2.sv