axi_tdl 0.1.8 → 0.1.19

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: d94bd22852a5b0a5f1bb2cc2326a6c67c0ba29875eba154fe001b63021aeb3d2
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+  data.tar.gz: 5740e4dff8c816d6607bf11d37808d1c32082e495ed7a97ddb6c0915104ee1f47465d0c95bd65529e6d3e422112d621a451e73b5fd183d8f6d558970d14a4618

data/lib/axi/AXI4/axi4_direct_verc.sv

@@ -70,6 +70,9 @@ initial begin
     "ONLY_READ_to_ONLY_READ":
         assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
         else $error("SLAVER AXIS MODE != ONLY_READ");
+    "ONLY_WRITE_TO_ONLY_WRITE":
+        assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
+        else $error("SLAVER AXIS MODE != ONLY_WRITE");
     default:
         assert(slaver_inf.MODE == "_____")
         else $error("SLAVER AXIS MODE ERROR")  ;
@@ -88,6 +91,9 @@ initial begin
     "ONLY_READ_to_ONLY_READ":
         assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
         else $error("MASTER AXIS MODE != ONLY_READ");
+    "ONLY_WRITE_TO_ONLY_WRITE":
+        assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
+        else $error("MASTER AXIS MODE != ONLY_WRITE");
     default:
         assert(master_inf.MODE == "_____")
         else $error("MASTER AXIS MODE ERROR");

data/lib/axi/AXI4/axi4_dpram_cache.rb

@@ -14,8 +14,8 @@ TdlBuild.axi4_dpram_cache(__dir__) do
     cm_ram_inf(dsize: a_inf.dsize,rsize: a_inf.asize,msize: a_inf.DSIZE/8)           - 'xram_inf'
 
     initial do 
-        assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE != b_inf.ASIZE")
-        assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE != b_inf.ASIZE")
+        assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.ASIZE, b_inf.ASIZE)
+        assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.DSIZE, b_inf.DSIZE)
     end
 
     full_axi4_to_axis.full_axi4_to_axis_ainst do |h|

data/lib/axi/AXI4/axi4_dpram_cache.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-16 17:01:03 +0800
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -70,11 +70,11 @@ common_ram_wrapper #(
 //-------- expression ------------------------------------------------------
 initial begin
     assert(a_inf.ASIZE==b_inf.ASIZE)else begin
-        $error("a_inf.ASIZE != b_inf.ASIZE");
+        $error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.ASIZE,b_inf.ASIZE);
         $stop;
     end
     assert(a_inf.DSIZE==b_inf.DSIZE)else begin
-        $error("a_inf.ASIZE != b_inf.ASIZE");
+        $error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.DSIZE,b_inf.DSIZE);
         $stop;
     end
 end

data/lib/axi/AXI4/axi4_ram_cache.rb

@@ -0,0 +1,23 @@
+require_shdl 'axi4_dpram_cache'
+
+TdlBuild.axi4_ram_cache(__dir__) do 
+    parameter.INIT_FILE     ''
+    port.axi4.slaver    - 'a_inf'
+
+    axi4_dpram_cache.axi4_dpram_cache_inst do |h|
+        h.parameter.INIT_FILE     param.INIT_FILE
+        h.port.axi4.slaver.a_inf    a_inf
+        h.port.axi4.slaver.b_inf    a_inf.copy(name: 'b_inf')
+    end
+
+    Assign do 
+        b_inf.axi_awvalid   <= 1.b0 
+        b_inf.axi_arvalid   <= 1.b0 
+
+        b_inf.axi_wvalid    <= 1.b0 
+        b_inf.axi_rready    <= 1.b1 
+
+        b_inf.axi_bready    <= 1.b1 
+    end
+
+end

data/lib/axi/AXI4/axi4_ram_cache.sv

@@ -0,0 +1,39 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axi4_ram_cache #(
+    parameter  INIT_FILE = ""
+)(
+    axi_inf.slaver   a_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+axi_inf #(.DSIZE(a_inf.DSIZE),.IDSIZE(a_inf.IDSIZE),.ASIZE(a_inf.ASIZE),.LSIZE(a_inf.LSIZE),.MODE(a_inf.MODE),.ADDR_STEP(a_inf.ADDR_STEP),.FreqM(a_inf.FreqM)) b_inf (.axi_aclk(a_inf.axi_aclk),.axi_aresetn(a_inf.axi_aresetn)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axi4_dpram_cache #(
+    .INIT_FILE (INIT_FILE )
+)axi4_dpram_cache_inst(
+/* axi_inf.slaver */.a_inf (a_inf ),
+/* axi_inf.slaver */.b_inf (b_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign b_inf.axi_awvalid = 1'b0;
+assign b_inf.axi_arvalid = 1'b0;
+assign b_inf.axi_wvalid = 1'b0;
+assign b_inf.axi_rready = 1'b1;
+assign b_inf.axi_bready = 1'b1;
+
+endmodule

data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv

@@ -0,0 +1,112 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+    it burst next after current be responed
+author : Cook.Darwin
+Version: VERA.1.0
+    dont wait last
+Version: VERA.2.0 
+    ex wait
+creaded: 2017/3/1 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module axi4_rd_auxiliary_gen_A2 (
+    input                       ex_wait_nofull,
+    axi_stream_inf.slaver       id_add_len_in,      //tlast is not necessary
+    axi_inf.master_rd_aux       axi_rd_aux
+);
+
+logic       clock,rst_n;
+assign  clock   = axi_rd_aux.axi_aclk;
+assign  rst_n   = axi_rd_aux.axi_aresetn;
+
+typedef enum {IDLE,SET_AR,WAIT_EMPTY} STATUS;
+
+STATUS nstate,cstate;
+
+always@(posedge clock,negedge rst_n)
+    if(~rst_n)  cstate  = IDLE;
+    else        cstate  = nstate;
+
+logic   cmd_fifo_empty;
+logic   cmd_fifo_full;
+
+always_comb
+    case(cstate)
+    IDLE:
+        if(id_add_len_in.axis_tvalid && id_add_len_in.axis_tready)
+                nstate  = SET_AR;
+        else    nstate  = IDLE;
+    SET_AR:
+        if(axi_rd_aux.axi_arvalid && axi_rd_aux.axi_arready)
+                nstate  = WAIT_EMPTY;
+        else    nstate  = SET_AR;
+    WAIT_EMPTY:
+        if(!cmd_fifo_full && ex_wait_nofull)
+                nstate  = IDLE;
+        else    nstate  = WAIT_EMPTY;
+    default:    nstate  = IDLE;
+    endcase
+
+logic [axi_rd_aux.ASIZE-1:0]    addr;
+logic [axi_rd_aux.IDSIZE-1:0]   id;
+logic [axi_rd_aux.LSIZE-1:0]    length;
+
+always@(posedge clock,negedge   rst_n)
+    if(~rst_n)  {id,addr,length}    <= '0;
+    else begin
+        if(id_add_len_in.axis_tvalid && id_add_len_in.axis_tready)
+                {id,addr,length}    <= id_add_len_in.axis_tdata;
+        else    {id,addr,length}    <= {id,addr,length};
+    end
+
+assign axi_rd_aux.axi_araddr    = addr;
+assign axi_rd_aux.axi_arlen     = length;
+assign axi_rd_aux.axi_arid      = id;
+
+always@(posedge clock,negedge   rst_n)
+    if(~rst_n)  axi_rd_aux.axi_arvalid  <= 1'b0;
+    else
+        case(nstate)
+        SET_AR: axi_rd_aux.axi_arvalid  <= 1'b1;
+        default:axi_rd_aux.axi_arvalid  <= 1'b0;
+        endcase
+
+
+always@(posedge clock,negedge   rst_n)
+    if(~rst_n)  id_add_len_in.axis_tready   <= 1'b0;
+    else
+        case(nstate)
+        IDLE:   id_add_len_in.axis_tready   <= 1'b1;
+        default:id_add_len_in.axis_tready   <= 1'b0;
+        endcase
+
+//--->> CMD FIFO <<--------------
+common_fifo #(
+    .DEPTH      (4  ),
+    .DSIZE      (axi_rd_aux.IDSIZE  )
+)common_fifo_inst(
+/*  input                   */  .clock      (clock                  ),
+/*  input                   */  .rst_n      (rst_n                  ),
+/*  input [DSIZE-1:0]       */  .wdata      (axi_rd_aux.axi_arid    ),
+/*  input                   */  .wr_en      ((axi_rd_aux.axi_arvalid && axi_rd_aux.axi_arready)),
+/*  output logic[DSIZE-1:0] */  .rdata      (),
+/*  input                   */  .rd_en      ((axi_rd_aux.axi_rvalid && axi_rd_aux.axi_rready && axi_rd_aux.axi_rlast)),
+/*  output logic[CSIZE-1:0] */  .count      (),
+/*  output logic            */  .empty      (cmd_fifo_empty         ),
+/*  output logic            */  .full       (cmd_fifo_full          )
+);
+//---<< CMD FIFO >>--------------
+
+//-->> TRACK <<-----------------
+// (* dont_touch="true" *)
+// logic [axi_rd_aux.LSIZE-1:0] rcnt;
+
+// always@(posedge clock,negedge   rst_n)
+//     if(~rst_n)  rcnt    <= '0;
+//     else        rcnt    <= axi_rd_aux.axi_rcnt;
+//--<< TRACK >>-----------------
+endmodule

data/lib/axi/AXI4/axis_to_axi4_wr.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded:
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1624 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -94,13 +94,13 @@ independent_clock_fifo #(
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
 /* output                        */.stream_en     (stream_en           ),
 /* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1624 )
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R0000 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R675_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1624 ),
+)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R0000 ),
 /* output */.to     (axi_wr              )
 );
 axis_valve_with_pipe #(

data/lib/axi/AXI4/long_axis_to_axi4_wr.rb

@@ -0,0 +1,113 @@
+# require_relative "../prj_lib"
+require_hdl "axis_length_split_with_addr.sv"
+require_hdl 'axi_stream_long_fifo_verb.sv'
+require_shdl 'axi4_wr_auxiliary_gen_without_resp','axis_valve_with_pipe'
+
+TdlBuild.long_axis_to_axi4_wr(__dir__) do
+    parameter.BYTE_DEPTH    8192*2
+
+    input[32]               - :addr
+    input[32]               - :max_length
+    port.axis.slaver        - 'axis_in'
+    port.axi4.master_wr     - 'axi_wr'
+
+    Initial do 
+        assert(axis_in.DSIZE == axi_wr.DSIZE, "STREAM DSIZE<%d> should eql AXI4 DSIZE<%d>",axis_in.DSIZE, axi_wr.DSIZE)
+    end
+
+    Def().logic(name: "addr_cur",dsize:32)
+
+    axis_length_split_with_addr.axis_length_split_with_addr_inst do |h|
+        h.param.ADDR_STEP       axi_wr.ADDR_STEP       
+        h.origin_addr           addr
+        h.length                max_length
+        h.band_addr             addr_cur
+        h.axis_in               axis_in
+        h.axis_out              axis_in.copy(name: 'split_out')
+    end
+
+    axi_stream_long_fifo_verb.axi_stream_long_fifo_verb_inst do |h|
+        h.param.DEPTH           4
+        h.param.BYTE_DEPTH      param.BYTE_DEPTH
+        h.port.axis.slaver.axis_in      split_out
+        h.port.axis.master.axis_out     split_out.copy(name:'fifo_axis',clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:axis_in.DSIZE)
+    end
+
+    Def().logic(name: :id,dsize:axi_wr.idsize)
+    Def().logic(name: :addr_s,dsize:axi_wr.asize)
+    Def().logic(name: :len_s,dsize:axi_wr.lsize)
+
+    Instance(:independent_clock_fifo,"independent_clock_fifo_inst") do |h|
+        h[:DEPTH]       = 4
+        h[:DSIZE]       = NqString.new("#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
+        h[:wr_clk]      = axis_in.aclk
+        h[:wr_rst_n]    = axis_in.aresetn
+        h[:rd_clk]      = axi_wr.axi_aclk
+        h[:rd_rst_n]    = axi_wr.axi_aresetn
+        h[:wdata]       = "{#{id.s},#{addr_s.s},#{len_s.s}}".to_nq
+        h[:wr_en]       = split_out.vld_rdy_last
+        h[:rdata]       = Def().logic(name:"fifo_rdata",dsize:h[:DSIZE])
+        h[:rd_en]       = Def().logic(name:"fifo_rd_en")
+        h[:empty]       = Def().logic(name:"fifo_empty")
+        h[:full]        = Def().logic(name:"fifo_full")
+    end
+
+    # AxiStream.axi4_wr_auxiliary_gen_without_resp(
+    #     stream_en:          Def().logic(name:"stream_en"),
+    #     id_add_len_in:      Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}"),
+    #     axi_wr_aux:         axi_wr,
+    #     belong_to_module:   self
+    # )
+
+    Instance(:axi4_wr_auxiliary_gen_without_resp,"axi4_wr_auxiliary_gen_without_resp_inst") do |h|
+        h[:stream_en]       = Def().logic(name: "stream_en")
+        # h[:id_add_len_in]   = Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
+        h[:id_add_len_in]   = axi_stream_inf(clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}".to_nq).id_add_len_in
+        h[:axi_wr_aux]      = axi_wr
+    end
+
+    Always(posedge:axis_in.aclk,negedge:axis_in.aresetn) do
+        IF ~axis_in.aresetn do
+            id <= 0
+         end
+        ELSIF split_out.vld_rdy_last do
+            id <= id + 1
+        end
+        ELSE do
+            id <= id
+        end
+    end
+
+    Assign do
+        addr_s  <= addr_cur
+        len_s   <= split_out.axis_tcnt
+        id_add_len_in.axis_tvalid           <= ~independent_clock_fifo_inst[:empty]
+        id_add_len_in.axis_tdata            <= independent_clock_fifo_inst[:rdata]
+        id_add_len_in.axis_tlast            <= 1.b1
+        independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
+    end
+
+    # pipe_axis = AxiStream.axis_valve_with_pipe(
+    #     mode:       "OUT",
+    #     button:     stream_en,
+    #     up_stream:  fifo_axis,
+    #     belong_to_module:self)
+
+    axis_valve_with_pipe.axis_valve_with_pipe_inst do |h|
+        h.parameter.MODE            "OUT"
+        h.input.button              stream_en         # //[1] OPEN ; [0] CLOSE
+        h.axis_in                   fifo_axis
+        h.axis_out                  fifo_axis.copy(name: 'pipe_axis')
+    end
+
+    Assign do
+        axi_wr.axi_wdata      <= pipe_axis.axis_tdata
+        axi_wr.axi_wstrb      <= ~pipe_axis.axis_tkeep
+        axi_wr.axi_wvalid     <= pipe_axis.axis_tvalid
+        axi_wr.axi_wlast      <= pipe_axis.axis_tlast
+        pipe_axis.axis_tready <= axi_wr.axi_wready
+        axi_wr.axi_bready     <= 1.b1
+    end
+
+    
+end

data/lib/axi/AXI4/long_axis_to_axi4_wr.sv

@@ -0,0 +1,125 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module long_axis_to_axi4_wr #(
+    parameter  BYTE_DEPTH = 16384
+)(
+    input [31:0]            addr,
+    input [31:0]            max_length,
+    axi_stream_inf.slaver   axis_in,
+    axi_inf.master_wr       axi_wr
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic [32-1:0]  addr_cur ;
+logic [axi_wr.IDSIZE-1:0]  id ;
+logic [axi_wr.ASIZE-1:0]  addr_s ;
+logic [axi_wr.LSIZE-1:0]  len_s ;
+logic [axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE-1:0]  fifo_rdata ;
+logic fifo_rd_en;
+logic fifo_empty;
+logic fifo_full;
+logic stream_en;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_length_split_with_addr #(
+    .ADDR_STEP (axi_wr.ADDR_STEP )
+)axis_length_split_with_addr_inst(
+/* input                 */.origin_addr (addr       ),
+/* input                 */.length      (max_length ),
+/* output                */.band_addr   (addr_cur   ),
+/* axi_stream_inf.slaver */.axis_in     (axis_in    ),
+/* axi_stream_inf.master */.axis_out    (split_out  )
+);
+axi_stream_long_fifo_verb #(
+    .DEPTH      (4          ),
+    .BYTE_DEPTH (BYTE_DEPTH )
+)axi_stream_long_fifo_verb_inst(
+/* axi_stream_inf.slaver */.axis_in  (split_out ),
+/* axi_stream_inf.master */.axis_out (fifo_axis )
+);
+independent_clock_fifo #(
+    .DEPTH (4                                           ),
+    .DSIZE (axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE )
+)independent_clock_fifo_inst(
+/* input  */.wr_clk   (axis_in.aclk                                                             ),
+/* input  */.wr_rst_n (axis_in.aresetn                                                          ),
+/* input  */.rd_clk   (axi_wr.axi_aclk                                                          ),
+/* input  */.rd_rst_n (axi_wr.axi_aresetn                                                       ),
+/* input  */.wdata    ({id[axi_wr.IDSIZE-1:0],addr_s[axi_wr.ASIZE-1:0],len_s[axi_wr.LSIZE-1:0]} ),
+/* input  */.wr_en    (split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast   ),
+/* output */.rdata    (fifo_rdata                                                               ),
+/* input  */.rd_en    (fifo_rd_en                                                               ),
+/* output */.empty    (fifo_empty                                                               ),
+/* output */.full     (fifo_full                                                                )
+);
+axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
+/* output                        */.stream_en     (stream_en           ),
+/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R0000 )
+);
+vcs_axi4_comptable #(
+    .ORIGIN ("master_wr_aux_no_resp" ),
+    .TO     ("master_wr"             )
+)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R0000 ),
+/* output */.to     (axi_wr              )
+);
+axis_valve_with_pipe #(
+    .MODE ("OUT" )
+)axis_valve_with_pipe_inst(
+/* input                 */.button   (stream_en ),
+/* axi_stream_inf.slaver */.axis_in  (fifo_axis ),
+/* axi_stream_inf.master */.axis_out (pipe_axis )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+    assert(axis_in.DSIZE==axi_wr.DSIZE)else begin
+        $error("STREAM DSIZE<%d> should eql AXI4 DSIZE<%d>",axis_in.DSIZE,axi_wr.DSIZE);
+        $stop;
+    end
+end
+
+always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin 
+    if(~axis_in.aresetn)begin
+        id <= 0;
+    end
+    else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
+        id <= (id+1);
+    end
+    else begin
+        id <= id;
+    end
+end
+
+assign addr_s = addr_cur;
+assign len_s = split_out.axis_tcnt;
+assign id_add_len_in.axis_tvalid = ~fifo_empty;
+assign id_add_len_in.axis_tdata = fifo_rdata;
+assign id_add_len_in.axis_tlast = 1'b1;
+assign fifo_rd_en = id_add_len_in.axis_tready;
+
+assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
+assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
+assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
+assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
+assign pipe_axis.axis_tready = axi_wr.axi_wready;
+assign axi_wr.axi_bready = 1'b1;
+
+endmodule

data/lib/axi/AXI4/odata_pool_axi4_A3.sv

@@ -10,6 +10,8 @@ Version: VERA.2.0 ###### Tue Jan 7 09:47:51 CST 2020
     data_inf_c replace valid ready
 Version: VERA.3.0 ###### Mon Sep 21 14:31:30 CST 2020
     add ex info
+Version: VERA.3.1 
+    use axi4_rd_auxiliary_gen_A2 
 creaded: 2017/3/1 下午6:12:34
 madified:
 ***********************************************/
@@ -75,10 +77,13 @@ assign  id      = '0;
 assign  addr    = fifo_addr[axi_master.ASIZE-1:0];
 assign  length  = fifo_size[axi_master.LSIZE:0];
 
+logic   ex_wait_nofull;
+
 assign addr_len_inf.axis_tdata  = {id,addr,length};
 
 `VCS_AXI4_CPT_LT(axi_master,master_rd,master_rd_aux,)
-axi4_rd_auxiliary_gen_A1 axi4_rd_auxiliary_gen_inst(
+axi4_rd_auxiliary_gen_A2 axi4_rd_auxiliary_gen_inst(
+/*        input                 */  .ex_wait_nofull (ex_wait_nofull ),
 /*    axi_stream_inf.slaver     */  .id_add_len_in  (addr_len_inf   ),      //tlast is not necessary
 /*    axi_inf.master_rd_aux     */  .axi_rd_aux     (`axi_master_vcs_cpt            )
 );
@@ -98,7 +103,7 @@ logic [out_axis.DSIZE+1-1:0]    axis_fifo_rd_data;
 
 logic   force_rd_en;
 
-logic   cmded_empty;
+logic   cmded_empty,cmded_full;
 
 independent_clock_fifo #(
     .DEPTH  (4  ),
@@ -113,12 +118,15 @@ independent_clock_fifo #(
 /*  output logic[DSIZE-1:0]  */   .rdata            (),
 /*  input                    */   .rd_en            (out_axis.axis_tvalid && out_axis.axis_tready && out_axis.axis_tlast),
 /*  output logic             */   .empty            (cmded_empty           ),
-/*  output logic             */   .full             ()
+/*  output logic             */   .full             (cmded_full            )
 );
 
 assign force_rd_en  = cmded_empty && !axis_fifo_empty;
+assign ex_wait_nofull = !cmded_full;
 //---<< forece rd_en >>---------------------------
 
+logic[axi_master.DSIZE-1:0] tmp_data;
+assign tmp_data = axi_master.axi_rdata;
 xilinx_fifo_verb #(
 //xilinx_fifo #(
     .DSIZE      (out_axis.DSIZE+1 )
@@ -127,7 +135,7 @@ xilinx_fifo_verb #(
 /*    input              */ .wr_rst     (!axi_master.axi_aresetn),
 /*    input              */ .rd_clk     (out_axis.aclk         ),
 /*    input              */ .rd_rst     (!out_axis.aresetn     ),
-/*    input [DSIZE-1:0]  */ .din        ({axi_master.axi_rlast,axi_master.axi_rdata}  ),
+/*    input [DSIZE-1:0]  */ .din        ({axi_master.axi_rlast,tmp_data}  ),
 /*    input              */ .wr_en      ((axi_master.axi_rvalid && axi_master.axi_rready) ),
 /*    input              */ .rd_en      (axis_fifo_rd_en  || force_rd_en     ),
 /*    output [DSIZE-1:0] */ .dout       (axis_fifo_rd_data     ),