axi_tdl 0.1.8 → 0.1.19
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +2 -2
- data/lib/axi/AXI4/axi4_dpram_cache.sv +3 -3
- data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +5 -5
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -23
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/Logic/logic_edge.rb +14 -6
- data/lib/tdl/Logic/logic_latency.rb +7 -7
- data/lib/tdl/auto_script/import_hdl.rb +1 -0
- data/lib/tdl/auto_script/import_sdl.rb +43 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
- data/lib/tdl/class_hdl/hdl_data.rb +1 -1
- data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
- data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
- data/lib/tdl/examples/11_test_unit/tu0.sv +3 -6
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +6 -153
- data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
- data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
- data/lib/tdl/exlib/axis_verify.rb +2 -2
- data/lib/tdl/exlib/logic_verify.rb +1 -1
- data/lib/tdl/rebuild_ele/axi4.rb +6 -2
- data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
- data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +17 -1
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb +3 -1
- metadata +7 -2
@@ -60,7 +60,7 @@ if(TO=="mirror")begin
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assign to.axi_rvalid = origin.axi_rvalid ;
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end else begin
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initial begin
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-
$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -85,7 +85,7 @@ end else if(TO=="mirror_rd")begin
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assign to.axi_rvalid = origin.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -131,7 +131,7 @@ end else if(ORIGIN=="slaver")begin
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assign origin.axi_rvalid = to.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -173,7 +173,7 @@ end else if(ORIGIN == "master_rd")begin
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assign origin.axi_rvalid = to.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -239,7 +239,7 @@ end else if(ORIGIN=="master")begin
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assign origin.axi_rvalid = to.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -261,7 +261,7 @@ end else if(ORIGIN == "master_wr_aux_no_resp")begin
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assign origin.axi_wready = to.axi_wready ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -285,7 +285,7 @@ end else if(ORIGIN == "master_rd_aux")begin
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assign origin.axi_rvalid = to.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -313,13 +313,39 @@ end else if(ORIGIN=="master_wr")begin
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assign origin.axi_bvalid = to.axi_bvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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end else if(ORIGIN=="slaver_rd")begin
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if(TO=="slaver")begin
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assign to.axi_arid = origin.axi_arid ;
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assign to.axi_araddr = origin.axi_araddr ;
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assign to.axi_arlen = origin.axi_arlen ;
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assign to.axi_arsize = origin.axi_arsize ;
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assign to.axi_arburst = origin.axi_arburst;
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assign to.axi_arlock = origin.axi_arlock ;
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assign to.axi_arcache = origin.axi_arcache;
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assign to.axi_arprot = origin.axi_arprot ;
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assign to.axi_arqos = origin.axi_arqos ;
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assign to.axi_arvalid = origin.axi_arvalid;
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assign origin.axi_arready = to.axi_arready;
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assign to.axi_rready = origin.axi_rready ;
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assign origin.axi_rid = to.axi_rid ;
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assign origin.axi_rresp = to.axi_rresp ;
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assign origin.axi_rlast = to.axi_rlast ;
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assign origin.axi_rdata = to.axi_rdata ;
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assign origin.axi_rvalid = to.axi_rvalid ;
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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end else begin
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initial begin
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$error("vcs_axi4_comptable ORIGIN[%
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$error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
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$stop;
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end
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end
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@@ -95,7 +95,7 @@ new_m.instance_exec do
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len_s <= split_out.axis_tcnt
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id_add_len_in.axis_tvalid <= ~independent_clock_fifo_inst[:empty]
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id_add_len_in.axis_tdata <= independent_clock_fifo_inst[:rdata]
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id_add_len_in.axis_tlast <=
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id_add_len_in.axis_tlast <= 1.b1
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independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
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end
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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-
creaded:
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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@@ -56,7 +56,7 @@ logic stream_en;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM))
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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@@ -93,13 +93,13 @@ independent_clock_fifo #(
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
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/* output */.stream_en (stream_en ),
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R0000 )
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);
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vcs_axi4_comptable #(
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.ORIGIN ("master_wr_aux_no_resp" ),
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.TO ("master_wr" )
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)
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/* input */.origin (
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)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
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/* input */.origin (axi_wr_vcs_cp_R0000 ),
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/* output */.to (axi_wr )
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);
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axis_valve_with_pipe #(
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@@ -19,8 +19,11 @@ TdlBuild.axi_stream_split_channel(__dir__) do
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addr <= 1.b0
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new_last <= 1.b0
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end
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ELSE do
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IF origin_inf.
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ELSE do
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IF origin_inf.vld_rdy_last do
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new_last <= 1.b0
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end
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ELSIF origin_inf.vld_rdy do
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new_last <= (origin_inf.axis_tcnt == (split_len - 2))
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end
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ELSE do
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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);
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//-------- CLOCKs Total 3 ----------------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_8,cc_same_8;
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integer cc_afreq_8,cc_bfreq_8;
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ClockSameDomain CheckPClock_inst_8(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (first_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_8),
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/* output logic */ .same (cc_same_8),
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/* output integer */ .aFreqK (cc_afreq_8),
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/* output integer */ .bFreqK (cc_bfreq_8)
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);
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initial begin
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wait(
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assert(
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wait(cc_done_8);
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assert(cc_same_8)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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//---<< CheckClock >>----------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_9,cc_same_9;
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integer cc_afreq_9,cc_bfreq_9;
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ClockSameDomain CheckPClock_inst_9(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (end_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_9),
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/* output logic */ .same (cc_same_9),
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/* output integer */ .aFreqK (cc_afreq_9),
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/* output integer */ .bFreqK (cc_bfreq_9)
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);
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initial begin
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wait(
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assert(
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wait(cc_done_9);
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assert(cc_same_9)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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new_last <= 1'b0;
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end
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else begin
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if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
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new_last <=
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if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
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new_last <= 1'b0;
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end
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else if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
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new_last <= (origin_inf.axis_tcnt==(split_len-2));
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end
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else begin
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new_last <= new_last;
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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Version: VERC.0.0
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creaded:
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+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -45,7 +45,7 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) or
|
|
45
45
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
46
46
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
47
47
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
48
|
-
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1))
|
48
|
+
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR0000 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
|
49
49
|
//==========================================================================
|
50
50
|
//-------- instance --------------------------------------------------------
|
51
51
|
axis_pipe_sync_seam #(
|
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
|
|
122
122
|
axis_head_cut_verb last_cut_inst(
|
123
123
|
/* input */.length (16'd1 ),
|
124
124
|
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
|
125
|
-
/* axi_stream_inf.master */.axis_out (
|
125
|
+
/* axi_stream_inf.master */.axis_out (out_inf_branchR0000 )
|
126
126
|
);
|
127
127
|
//==========================================================================
|
128
128
|
//-------- expression ------------------------------------------------------
|
@@ -136,7 +136,7 @@ axis_direct axis_direct_out_inf_inst0 (
|
|
136
136
|
);
|
137
137
|
|
138
138
|
axis_direct axis_direct_out_inf_inst1 (
|
139
|
-
/* axi_stream_inf.slaver*/ .slaver (
|
139
|
+
/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR0000),
|
140
140
|
/* axi_stream_inf.master*/ .master (sub_out_inf[1])
|
141
141
|
);
|
142
142
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
|
author : Cook.Darwin
|
7
7
|
Version: VERA.0.0
|
8
|
-
creaded:
|
8
|
+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
|
|
48
48
|
endgenerate
|
49
49
|
//-------- CLOCKs Total 2 ----------------------
|
50
50
|
//--->> CheckClock <<----------------
|
51
|
-
logic
|
52
|
-
integer
|
53
|
-
ClockSameDomain
|
51
|
+
logic cc_done_10,cc_same_10;
|
52
|
+
integer cc_afreq_10,cc_bfreq_10;
|
53
|
+
ClockSameDomain CheckPClock_inst_10(
|
54
54
|
/* input */ .aclk (in_inf.clock ),
|
55
55
|
/* input */ .bclk (out_inf.clock ),
|
56
|
-
/* output logic */ .done (
|
57
|
-
/* output logic */ .same (
|
58
|
-
/* output integer */ .aFreqK (
|
59
|
-
/* output integer */ .bFreqK (
|
56
|
+
/* output logic */ .done (cc_done_10),
|
57
|
+
/* output logic */ .same (cc_same_10),
|
58
|
+
/* output integer */ .aFreqK (cc_afreq_10),
|
59
|
+
/* output integer */ .bFreqK (cc_bfreq_10)
|
60
60
|
);
|
61
61
|
|
62
62
|
initial begin
|
63
|
-
wait(
|
64
|
-
assert(
|
63
|
+
wait(cc_done_10);
|
64
|
+
assert(cc_same_10)
|
65
65
|
else begin
|
66
|
-
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/
|
66
|
+
$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
|
67
67
|
repeat(10)begin
|
68
68
|
@(posedge in_inf.clock);
|
69
69
|
end
|
data/lib/axi_tdl/version.rb
CHANGED
data/lib/tdl/Logic/logic_edge.rb
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
|
2
2
|
|
3
3
|
class Logic ## EDGE METHOD
|
4
|
-
def raising(cnt:1,clock:nil,reset: 1.b1 )
|
4
|
+
def raising(name: nil, cnt: 1,clock: nil,reset: 1.b1 )
|
5
5
|
|
6
6
|
# if cnt==1 && clock == nil && reset==nil && @raising_record
|
7
7
|
# return @raising_record
|
@@ -26,11 +26,19 @@ class Logic ## EDGE METHOD
|
|
26
26
|
# GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str }
|
27
27
|
belong_to_module.Logic_draw << head_str
|
28
28
|
inst_edge(@clock,@reset)
|
29
|
-
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
|
29
|
+
unless name
|
30
|
+
if cnt>1
|
31
|
+
inst_raise_edge_cnt(cnt-1)
|
32
|
+
str = inst_cnt_edge_signal(cnt-1,:raise)
|
33
|
+
else
|
34
|
+
str = "#{signal}_raising"
|
35
|
+
|
36
|
+
end
|
37
|
+
else
|
38
|
+
if cnt>1
|
39
|
+
inst_raise_edge_cnt(cnt-1)
|
40
|
+
end
|
41
|
+
str = name
|
34
42
|
end
|
35
43
|
# @@logic_expression << lambda{ end_str }
|
36
44
|
# GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str }
|
@@ -81,7 +81,7 @@ cross_clk_sync #(
|
|
81
81
|
if wclk.nil? || rclk.nil?
|
82
82
|
raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
|
83
83
|
end
|
84
|
-
new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{
|
84
|
+
new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
|
85
85
|
large_name_len(phase,len,wclk,wreset,rclk,rreset)
|
86
86
|
body =
|
87
87
|
"
|
@@ -89,7 +89,7 @@ broaden_and_cross_clk #(
|
|
89
89
|
.PHASE (#{align_signal(phase)}), //POSITIVE NEGATIVE
|
90
90
|
.LEN (#{align_signal(len)}),
|
91
91
|
.LAT (#{align_signal(lat)})
|
92
|
-
)#{new_l.signal}_inst_#{
|
92
|
+
)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
|
93
93
|
/* input */ .rclk (#{align_signal(rclk,q_mark=false)}),
|
94
94
|
/* input */ .rd_rst_n (#{align_signal(rreset,q_mark=false)}),
|
95
95
|
/* input */ .wclk (#{align_signal(wclk,q_mark=false)}),
|
@@ -125,7 +125,7 @@ module CtrlLogic
|
|
125
125
|
latency #(
|
126
126
|
.LAT (#{num}),
|
127
127
|
.DSIZE (1)
|
128
|
-
)#{new_l.signal}_lat_#{
|
128
|
+
)#{new_l.signal}_lat_#{belong_to_module._auto_name_incr_index_()}(
|
129
129
|
#{clock},
|
130
130
|
#{reset_str},
|
131
131
|
#{self.to_s},
|
@@ -145,13 +145,13 @@ latency #(
|
|
145
145
|
|
146
146
|
# new_l = Logic.new(name:"crock_clk",dsize:self.dsize)
|
147
147
|
# new_l = self.logic(name:"crock_clk",dsize:self.dsize)
|
148
|
-
new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{
|
148
|
+
new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:dsize)
|
149
149
|
str = %Q{
|
150
150
|
//----->> #{self.to_s} cross clock <<------------------
|
151
151
|
cross_clk_sync #(
|
152
152
|
.LAT (2 ),
|
153
153
|
.DSIZE (#{dsize})
|
154
|
-
)#{new_l.signal}_cross_clk_inst__#{
|
154
|
+
)#{new_l.signal}_cross_clk_inst__#{belong_to_module._auto_name_incr_index_()}(
|
155
155
|
/* input */ .clk (#{align_signal(clock)}),
|
156
156
|
/* input */ .rst_n (#{align_signal(reset)}),
|
157
157
|
/* input [DSIZE-1:0] */ .d (#{align_signal(self)}),
|
@@ -168,7 +168,7 @@ cross_clk_sync #(
|
|
168
168
|
if wclk.nil? || rclk.nil?
|
169
169
|
raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
|
170
170
|
end
|
171
|
-
new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{
|
171
|
+
new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
|
172
172
|
large_name_len(phase,len,wclk,wreset,rclk,rreset)
|
173
173
|
body =
|
174
174
|
"
|
@@ -176,7 +176,7 @@ broaden_and_cross_clk #(
|
|
176
176
|
.PHASE (#{align_signal(phase)}), //POSITIVE NEGATIVE
|
177
177
|
.LEN (#{align_signal(len)}),
|
178
178
|
.LAT (#{align_signal(lat)})
|
179
|
-
)#{new_l.signal}_inst_#{
|
179
|
+
)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
|
180
180
|
/* input */ .rclk (#{align_signal(rclk,q_mark=false)}),
|
181
181
|
/* input */ .rd_rst_n (#{align_signal(rreset,q_mark=false)}),
|
182
182
|
/* input */ .wclk (#{align_signal(wclk,q_mark=false)}),
|
@@ -23,4 +23,46 @@ def require_sdl(sdl_path)
|
|
23
23
|
end
|
24
24
|
# require_relative File.join(__dir__,"tmp","#{basename}_sdl.rb")
|
25
25
|
end
|
26
|
-
end
|
26
|
+
end
|
27
|
+
|
28
|
+
## 添加 模糊引入
|
29
|
+
def require_shdl(*shdl_name)
|
30
|
+
shdl_name.each do |s|
|
31
|
+
unless s.is_a? Array
|
32
|
+
__require_shdl__(s)
|
33
|
+
else
|
34
|
+
__require_shdl__(s[0],s[1])
|
35
|
+
end
|
36
|
+
end
|
37
|
+
end
|
38
|
+
|
39
|
+
def __require_shdl__(shdl_name,encoding='utf-8')
|
40
|
+
|
41
|
+
unless SdlModule.exist_module? shdl_name
|
42
|
+
sdl_path = "#{shdl_name}.rb"
|
43
|
+
rel = find_first_hdl_path(sdl_path)
|
44
|
+
## 匹配 SDL
|
45
|
+
if rel
|
46
|
+
require_relative rel
|
47
|
+
return
|
48
|
+
end
|
49
|
+
## 匹配 SV
|
50
|
+
sv_path = "#{shdl_name}.sv"
|
51
|
+
v_path = "#{shdl_name}.v"
|
52
|
+
vv_path = "#{shdl_name}.V"
|
53
|
+
|
54
|
+
rel = find_first_hdl_path(sv_path) || find_first_hdl_path(v_path) || find_first_hdl_path(vv_path)
|
55
|
+
if rel
|
56
|
+
AutoGenSdl.new(rel,File.join(__dir__,"tmp"),encoding=encoding).auto_rb
|
57
|
+
|
58
|
+
unless $__contain_hdl__.include? rel
|
59
|
+
$__contain_hdl__ << rel
|
60
|
+
end
|
61
|
+
|
62
|
+
require_relative File.join(__dir__,"tmp","#{shdl_name}_sdl.rb")
|
63
|
+
return
|
64
|
+
end
|
65
|
+
|
66
|
+
raise TdlError.new("Can find <#{shdl_name}> in tdl paths !!!")
|
67
|
+
end
|
68
|
+
end
|
@@ -68,7 +68,7 @@ class Axi4
|
|
68
68
|
e.band_params_from(self)
|
69
69
|
|
70
70
|
## e is a Vector
|
71
|
-
if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
|
71
|
+
if e.dimension && e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
|
72
72
|
# require_hdl 'axi4_direct_B1.sv'
|
73
73
|
require_hdl 'axi4_direct_verc.sv'
|
74
74
|
|
@@ -189,8 +189,10 @@ class Axi4
|
|
189
189
|
@_long_slim_to_wide << new_master
|
190
190
|
else
|
191
191
|
if !(e.dsize.eql? self.dsize)
|
192
|
+
require_hdl 'axi4_long_to_axi4_wide_verb.sv'
|
193
|
+
TopModule.contain_hdl 'axi4_direct_verb.sv'
|
192
194
|
# puts "#{e.dsize} == #{self.dsize} #{e.dsize != self.dsize} #{e.dsize.class}"
|
193
|
-
new_master = self.copy(mode:e.mode,idsize:e.idsize)
|
195
|
+
new_master = self.copy(name: "#{e.name}_renew_dir",mode:e.mode,idsize:e.idsize)
|
194
196
|
# new_master.axi4_data_convert(up_stream: e)
|
195
197
|
# @_long_slim_to_wide << Axi4.axi4_pipe(up_stream:new_master)
|
196
198
|
|
@@ -245,20 +247,13 @@ class Axi4
|
|
245
247
|
else
|
246
248
|
mode_str = "ONLY_READ_to_BOTH"
|
247
249
|
end
|
248
|
-
|
249
|
-
# # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
250
|
-
# belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
|
251
|
-
# # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
252
|
-
# h.slaver_inf lo
|
253
|
-
# h.master_inf "#{sub_name}[#{index}]".to_nq
|
254
|
-
# end
|
255
|
-
|
250
|
+
|
256
251
|
require_hdl 'axi4_direct_verc.sv'
|
257
|
-
belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{
|
252
|
+
belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
|
258
253
|
h.param.MODE mode_str # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
259
254
|
h.param.SLAVER_MODE (wr_lg ? "ONLY_WRITE" : "ONLY_READ") # //
|
260
255
|
h.param.MASTER_MODE "BOTH" # //
|
261
|
-
h.slaver_inf (lo.respond_to?(:dimension) && lo.dimension[0]==1 && lo[0]) || lo
|
256
|
+
h.slaver_inf (lo.respond_to?(:dimension) && (lo.dimension.nil? || lo.dimension[0]==1) && lo[0]) || lo
|
262
257
|
h.master_inf "#{sub_name}[#{index}]".to_nq
|
263
258
|
end
|
264
259
|
|
@@ -268,14 +263,14 @@ class Axi4
|
|
268
263
|
require_hdl 'axi4_combin_wr_rd_batch.sv'
|
269
264
|
if wr_lg
|
270
265
|
# Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
271
|
-
belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
|
266
|
+
belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
|
272
267
|
h.wr_slaver lo
|
273
268
|
h.rd_slaver los
|
274
269
|
h.master "#{sub_name}[#{index}]".to_nq
|
275
270
|
end
|
276
271
|
else
|
277
272
|
# Axi4.axi4_combin_wr_rd_batch(wr_slaver:los,rd_slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
278
|
-
belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
|
273
|
+
belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
|
279
274
|
h.wr_slaver los
|
280
275
|
h.rd_slaver lo
|
281
276
|
h.master "#{sub_name}[#{index}]".to_nq
|
@@ -1,7 +1,7 @@
|
|
1
1
|
class Integer
|
2
2
|
|
3
3
|
def method_missing(method,arg=nil)
|
4
|
-
if method.to_s =~ /^s?[h|d]\d+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f]+$/i
|
4
|
+
if method.to_s =~ /^s?[h|d][\d|_]+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f|_]+$/i
|
5
5
|
if self.nonzero?
|
6
6
|
return "#{self.to_s}'#{method}".to_nq
|
7
7
|
else
|
@@ -19,7 +19,7 @@ module ClassHDL
|
|
19
19
|
attr_accessor :block_index
|
20
20
|
def initialize(belong_to_module)
|
21
21
|
@belong_to_module = belong_to_module
|
22
|
-
super("genblk#{
|
22
|
+
super("genblk#{belong_to_module._auto_name_incr_index_}")
|
23
23
|
unless @belong_to_module
|
24
24
|
raise TdlError.new("GenerateBlock must have belong_to_module")
|
25
25
|
end
|