axi_tdl 0.1.8 → 0.1.19

data/lib/axi/AXI4/vcs_axi4_comptable.sv

@@ -60,7 +60,7 @@ if(TO=="mirror")begin
         assign to.axi_rvalid   = origin.axi_rvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end
@@ -85,7 +85,7 @@ end else if(TO=="mirror_rd")begin
         assign  to.axi_rvalid   = origin.axi_rvalid ;
     end else begin
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end 
     end
@@ -131,7 +131,7 @@ end else if(ORIGIN=="slaver")begin
         assign    origin.axi_rvalid   = to.axi_rvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -173,7 +173,7 @@ end  else if(ORIGIN == "master_rd")begin
         assign     origin.axi_rvalid  = to.axi_rvalid  ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -239,7 +239,7 @@ end else if(ORIGIN=="master")begin
         assign   origin.axi_rvalid  = to.axi_rvalid   ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end
@@ -261,7 +261,7 @@ end else if(ORIGIN == "master_wr_aux_no_resp")begin
         assign   origin.axi_wready   = to.axi_wready ;
     end else begin
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -285,7 +285,7 @@ end else if(ORIGIN == "master_rd_aux")begin
         assign   origin.axi_rvalid  = to.axi_rvalid   ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -313,13 +313,39 @@ end else if(ORIGIN=="master_wr")begin
         assign    origin.axi_bvalid   = to.axi_bvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
+            $stop;
+        end
+    end 
+end else if(ORIGIN=="slaver_rd")begin 
+    if(TO=="slaver")begin 
+        assign    to.axi_arid     = origin.axi_arid   ;
+        assign    to.axi_araddr   = origin.axi_araddr ;
+        assign    to.axi_arlen    = origin.axi_arlen  ;
+        assign    to.axi_arsize   = origin.axi_arsize ;
+        assign    to.axi_arburst  = origin.axi_arburst;
+        assign    to.axi_arlock   = origin.axi_arlock ;
+        assign    to.axi_arcache  = origin.axi_arcache;
+        assign    to.axi_arprot   = origin.axi_arprot ;
+        assign    to.axi_arqos    = origin.axi_arqos  ;
+        assign    to.axi_arvalid  = origin.axi_arvalid;
+        assign    origin.axi_arready    = to.axi_arready;
+
+        assign    to.axi_rready             = origin.axi_rready ;
+        assign    origin.axi_rid            = to.axi_rid    ;
+        assign    origin.axi_rresp          = to.axi_rresp  ;
+        assign    origin.axi_rlast          = to.axi_rlast  ;
+        assign    origin.axi_rdata          = to.axi_rdata  ;
+        assign    origin.axi_rvalid         = to.axi_rvalid ;
+    end else begin 
+        initial begin
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
 end else begin 
     initial begin
-        $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+        $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
         $stop;
     end
 end

data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb

@@ -95,7 +95,7 @@ new_m.instance_exec do
         len_s   <= split_out.axis_tcnt
         id_add_len_in.axis_tvalid           <= ~independent_clock_fifo_inst[:empty]
         id_add_len_in.axis_tdata            <= independent_clock_fifo_inst[:rdata]
-        id_add_len_in.axis_tlast            <= "1'b1"
+        id_add_len_in.axis_tlast            <= 1.b1
         independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
     end
 

data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded:
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1219 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -93,13 +93,13 @@ independent_clock_fifo #(
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
 /* output                        */.stream_en     (stream_en           ),
 /* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1219 )
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R0000 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R827_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1219 ),
+)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R0000 ),
 /* output */.to     (axi_wr              )
 );
 axis_valve_with_pipe #(

data/lib/axi/AXI4/width_convert/odd_width_convert.sv

@@ -31,7 +31,7 @@ assign wr_ready = rd_ready;
 initial begin
     assert(ISIZE < OSIZE)
     else begin
-        $error("ISIZE MUST BE MORE SMALLER THAN OSIZE\n");
+        $error("ISIZE<%d> MUST BE MORE SMALLER THAN OSIZE<%d>\n",ISIZE,OSIZE);
         $stop;
     end
 end

data/lib/axi/AXI_stream/axi_stream_split_channel.rb

@@ -19,8 +19,11 @@ TdlBuild.axi_stream_split_channel(__dir__) do
             addr        <= 1.b0 
             new_last    <= 1.b0
         end
-        ELSE do 
-            IF origin_inf.vld_rdy do 
+        ELSE do
+            IF origin_inf.vld_rdy_last do
+                new_last    <= 1.b0
+            end
+            ELSIF origin_inf.vld_rdy do 
                 new_last    <= (origin_inf.axis_tcnt == (split_len - 2))
             end
             ELSE do 

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: 
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -55,22 +55,22 @@ axis_direct  axis_direct_end_inf_inst0 (
 );
 //-------- CLOCKs Total 3 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_6,cc_same_6;
-integer cc_afreq_6,cc_bfreq_6;
-ClockSameDomain CheckPClock_inst_6(
+logic cc_done_8,cc_same_8;
+integer cc_afreq_8,cc_bfreq_8;
+ClockSameDomain CheckPClock_inst_8(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (first_inf.aclk         ),
-/*  output logic  */      .done     (cc_done_6),
-/*  output logic  */      .same     (cc_same_6),
-/*  output integer */     .aFreqK   (cc_afreq_6),
-/*  output integer */     .bFreqK   (cc_bfreq_6)
+/*  output logic  */      .done     (cc_done_8),
+/*  output logic  */      .same     (cc_same_8),
+/*  output integer */     .aFreqK   (cc_afreq_8),
+/*  output integer */     .bFreqK   (cc_bfreq_8)
 );
 
 initial begin
-    wait(cc_done_6);
-    assert(cc_same_6)
+    wait(cc_done_8);
+    assert(cc_same_8)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_6, 1000000.0/cc_bfreq_6);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -80,22 +80,22 @@ end
 //---<< CheckClock >>----------------
 
 //--->> CheckClock <<----------------
-logic cc_done_7,cc_same_7;
-integer cc_afreq_7,cc_bfreq_7;
-ClockSameDomain CheckPClock_inst_7(
+logic cc_done_9,cc_same_9;
+integer cc_afreq_9,cc_bfreq_9;
+ClockSameDomain CheckPClock_inst_9(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (end_inf.aclk           ),
-/*  output logic  */      .done     (cc_done_7),
-/*  output logic  */      .same     (cc_same_7),
-/*  output integer */     .aFreqK   (cc_afreq_7),
-/*  output integer */     .bFreqK   (cc_bfreq_7)
+/*  output logic  */      .done     (cc_done_9),
+/*  output logic  */      .same     (cc_same_9),
+/*  output integer */     .aFreqK   (cc_afreq_9),
+/*  output integer */     .bFreqK   (cc_bfreq_9)
 );
 
 initial begin
-    wait(cc_done_7);
-    assert(cc_same_7)
+    wait(cc_done_9);
+    assert(cc_same_9)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -114,8 +114,11 @@ always_ff@(posedge clock,negedge rst_n) begin
         new_last <= 1'b0;
     end
     else begin
-        if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
-            new_last <= origin_inf.axis_tcnt==(split_len-2);
+        if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
+            new_last <= 1'b0;
+        end
+        else if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
+            new_last <= (origin_inf.axis_tcnt==(split_len-2));
         end
         else begin
             new_last <= new_last;

data/lib/axi/AXI_stream/axis_head_cut_verc.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERC.0.0
-creaded:
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -45,7 +45,7 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) or
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR325 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR0000 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_pipe_sync_seam #(
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
 axis_head_cut_verb last_cut_inst(
 /* input                 */.length   (16'd1               ),
 /* axi_stream_inf.slaver */.axis_in  (origin_inf_ss_E0_CH ),
-/* axi_stream_inf.master */.axis_out (out_inf_branchR325  )
+/* axi_stream_inf.master */.axis_out (out_inf_branchR0000 )
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
@@ -136,7 +136,7 @@ axis_direct  axis_direct_out_inf_inst0 (
 );
 
 axis_direct  axis_direct_out_inf_inst1 (
-/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR325),
+/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR0000),
 /*  axi_stream_inf.master*/ .master (sub_out_inf[1])
 );
 

data/lib/axi/common/common_ram_wrapper.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded:
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded:
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
 endgenerate
 //-------- CLOCKs Total 2 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_8,cc_same_8;
-integer cc_afreq_8,cc_bfreq_8;
-ClockSameDomain CheckPClock_inst_8(
+logic cc_done_10,cc_same_10;
+integer cc_afreq_10,cc_bfreq_10;
+ClockSameDomain CheckPClock_inst_10(
 /*  input         */      .aclk     (in_inf.clock           ),
 /*  input         */      .bclk     (out_inf.clock          ),
-/*  output logic  */      .done     (cc_done_8),
-/*  output logic  */      .same     (cc_same_8),
-/*  output integer */     .aFreqK   (cc_afreq_8),
-/*  output integer */     .bFreqK   (cc_bfreq_8)
+/*  output logic  */      .done     (cc_done_10),
+/*  output logic  */      .same     (cc_same_10),
+/*  output integer */     .aFreqK   (cc_afreq_10),
+/*  output integer */     .bFreqK   (cc_bfreq_10)
 );
 
 initial begin
-    wait(cc_done_8);
-    assert(cc_same_8)
+    wait(cc_done_10);
+    assert(cc_same_10)
     else begin
-        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
         repeat(10)begin 
             @(posedge in_inf.clock);
         end

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.1.8"
+  VERSION = "0.1.19"
 end

data/lib/tdl/Logic/logic_edge.rb

@@ -1,7 +1,7 @@
 
 
 class Logic     ## EDGE METHOD
-    def raising(cnt:1,clock:nil,reset: 1.b1 )
+    def raising(name: nil, cnt: 1,clock: nil,reset: 1.b1 )
 
         # if cnt==1 && clock == nil && reset==nil && @raising_record
         #     return @raising_record
@@ -26,11 +26,19 @@ class Logic     ## EDGE METHOD
                 # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str }
                 belong_to_module.Logic_draw << head_str
                 inst_edge(@clock,@reset)
-                if cnt>1
-                    inst_raise_edge_cnt(cnt-1)
-                    str = inst_cnt_edge_signal(cnt-1,:raise)
-                else
-                    str = "#{signal}_raising"
+                unless name 
+                    if cnt>1
+                        inst_raise_edge_cnt(cnt-1)
+                        str = inst_cnt_edge_signal(cnt-1,:raise)
+                    else
+                        str = "#{signal}_raising"
+                    
+                    end
+                else 
+                    if cnt>1
+                        inst_raise_edge_cnt(cnt-1)
+                    end
+                    str = name 
                 end
                 # @@logic_expression << lambda{ end_str }
                 # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str }

data/lib/tdl/Logic/logic_latency.rb

@@ -81,7 +81,7 @@ cross_clk_sync #(
         if wclk.nil? || rclk.nil?
             raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
         end
-        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{globle_random_name_flag()}",dsize:1)
+        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
         large_name_len(phase,len,wclk,wreset,rclk,rreset)
 body =
 "
@@ -89,7 +89,7 @@ broaden_and_cross_clk #(
     .PHASE     (#{align_signal(phase)}),  //POSITIVE NEGATIVE
     .LEN       (#{align_signal(len)}),
     .LAT       (#{align_signal(lat)})
-)#{new_l.signal}_inst_#{globle_random_name_flag()}(
+)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
 /* input    */  .rclk       (#{align_signal(rclk,q_mark=false)}),
 /* input    */  .rd_rst_n   (#{align_signal(rreset,q_mark=false)}),
 /* input    */  .wclk       (#{align_signal(wclk,q_mark=false)}),
@@ -125,7 +125,7 @@ module  CtrlLogic
 latency #(
     .LAT    (#{num}),
     .DSIZE  (1)
-)#{new_l.signal}_lat_#{globle_random_name_flag()}(
+)#{new_l.signal}_lat_#{belong_to_module._auto_name_incr_index_()}(
     #{clock},
     #{reset_str},
     #{self.to_s},
@@ -145,13 +145,13 @@ latency #(
 
         # new_l = Logic.new(name:"crock_clk",dsize:self.dsize)
         # new_l = self.logic(name:"crock_clk",dsize:self.dsize)
-        new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{globle_random_name_flag()}",dsize:dsize)
+        new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:dsize)
         str = %Q{
 //----->> #{self.to_s} cross clock <<------------------
 cross_clk_sync #(
 	.LAT   (2      ),
 	.DSIZE (#{dsize})
-)#{new_l.signal}_cross_clk_inst__#{globle_random_name_flag()}(
+)#{new_l.signal}_cross_clk_inst__#{belong_to_module._auto_name_incr_index_()}(
 /* input              */ .clk       (#{align_signal(clock)}),
 /* input              */ .rst_n     (#{align_signal(reset)}),
 /* input [DSIZE-1:0]  */ .d         (#{align_signal(self)}),
@@ -168,7 +168,7 @@ cross_clk_sync #(
         if wclk.nil? || rclk.nil?
             raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
         end
-        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{globle_random_name_flag()}",dsize:1)
+        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
         large_name_len(phase,len,wclk,wreset,rclk,rreset)
 body =
 "
@@ -176,7 +176,7 @@ broaden_and_cross_clk #(
 	.PHASE     (#{align_signal(phase)}),  //POSITIVE NEGATIVE
 	.LEN       (#{align_signal(len)}),
 	.LAT       (#{align_signal(lat)})
-)#{new_l.signal}_inst_#{globle_random_name_flag()}(
+)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
 /* input    */  .rclk       (#{align_signal(rclk,q_mark=false)}),
 /* input    */  .rd_rst_n   (#{align_signal(rreset,q_mark=false)}),
 /* input    */  .wclk       (#{align_signal(wclk,q_mark=false)}),

data/lib/tdl/auto_script/import_hdl.rb

@@ -36,6 +36,7 @@ def __require_hdl__(hdl_path,current_sdlm=nil,encoding='utf-8')
                 raise TdlError.new("path<#{hdl_path}> error!!!")
             end
         end
+        
         require_relative File.join(__dir__,"tmp","#{basename}_sdl.rb")
     end
 end

data/lib/tdl/auto_script/import_sdl.rb

@@ -23,4 +23,46 @@ def require_sdl(sdl_path)
         end
         # require_relative File.join(__dir__,"tmp","#{basename}_sdl.rb")
     end
-end
+end
+
+## 添加 模糊引入 
+def require_shdl(*shdl_name)
+    shdl_name.each do |s|
+        unless s.is_a? Array
+            __require_shdl__(s)
+        else 
+            __require_shdl__(s[0],s[1])
+        end
+    end    
+end
+
+def __require_shdl__(shdl_name,encoding='utf-8')
+    
+    unless SdlModule.exist_module? shdl_name
+        sdl_path = "#{shdl_name}.rb"
+        rel = find_first_hdl_path(sdl_path)
+        ## 匹配 SDL
+        if rel 
+            require_relative rel
+            return 
+        end
+        ## 匹配 SV 
+        sv_path = "#{shdl_name}.sv"
+        v_path = "#{shdl_name}.v"
+        vv_path = "#{shdl_name}.V"
+
+        rel = find_first_hdl_path(sv_path) || find_first_hdl_path(v_path) || find_first_hdl_path(vv_path)
+        if rel 
+            AutoGenSdl.new(rel,File.join(__dir__,"tmp"),encoding=encoding).auto_rb
+
+            unless  $__contain_hdl__.include? rel
+                $__contain_hdl__ << rel
+            end
+
+            require_relative File.join(__dir__,"tmp","#{shdl_name}_sdl.rb")
+            return 
+        end
+
+        raise TdlError.new("Can find <#{shdl_name}> in tdl paths !!!")    
+    end
+end

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -68,7 +68,7 @@ class Axi4
                 e.band_params_from(self)
                 
                 ## e is a Vector 
-                if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
+                if e.dimension && e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
                     # require_hdl 'axi4_direct_B1.sv'
                     require_hdl 'axi4_direct_verc.sv'
 
@@ -189,8 +189,10 @@ class Axi4
                 @_long_slim_to_wide << new_master
             else
                 if !(e.dsize.eql? self.dsize)
+                    require_hdl 'axi4_long_to_axi4_wide_verb.sv'
+                    TopModule.contain_hdl 'axi4_direct_verb.sv'
                     # puts "#{e.dsize} == #{self.dsize} #{e.dsize != self.dsize} #{e.dsize.class}"
-                    new_master = self.copy(mode:e.mode,idsize:e.idsize)
+                    new_master = self.copy(name: "#{e.name}_renew_dir",mode:e.mode,idsize:e.idsize)
                     # new_master.axi4_data_convert(up_stream: e)
                     # @_long_slim_to_wide << Axi4.axi4_pipe(up_stream:new_master)
 
@@ -245,20 +247,13 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
-                # require_hdl 'axi4_direct_B1.sv'
-                # # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                # belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
-                #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                #     h.slaver_inf        lo
-                #     h.master_inf        "#{sub_name}[#{index}]".to_nq
-                # end
-
+                
                 require_hdl 'axi4_direct_verc.sv'
-                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                     h.param.MODE            mode_str    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                     h.param.SLAVER_MODE     (wr_lg ? "ONLY_WRITE" : "ONLY_READ")    #    //
                     h.param.MASTER_MODE     "BOTH"    #    //
-                    h.slaver_inf        (lo.respond_to?(:dimension) && lo.dimension[0]==1 && lo[0])  || lo
+                    h.slaver_inf        (lo.respond_to?(:dimension) && (lo.dimension.nil? || lo.dimension[0]==1) && lo[0])  || lo
                     h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
@@ -268,14 +263,14 @@ class Axi4
                 require_hdl 'axi4_combin_wr_rd_batch.sv'
                 if wr_lg
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
+                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                         h.wr_slaver         lo
                         h.rd_slaver         los
                         h.master            "#{sub_name}[#{index}]".to_nq
                     end 
                 else
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:los,rd_slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
+                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                         h.wr_slaver         los
                         h.rd_slaver         lo
                         h.master            "#{sub_name}[#{index}]".to_nq

data/lib/tdl/class_hdl/hdl_data.rb

@@ -1,7 +1,7 @@
 class Integer
 
     def method_missing(method,arg=nil)
-        if method.to_s =~ /^s?[h|d]\d+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f]+$/i
+        if method.to_s =~ /^s?[h|d][\d|_]+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f|_]+$/i
             if self.nonzero?
                 return "#{self.to_s}'#{method}".to_nq
             else 

data/lib/tdl/class_hdl/hdl_generate.rb

@@ -19,7 +19,7 @@ module ClassHDL
         attr_accessor :block_index
         def initialize(belong_to_module)
             @belong_to_module = belong_to_module
-            super("genblk#{globle_random_name_flag()}")
+            super("genblk#{belong_to_module._auto_name_incr_index_}")
             unless @belong_to_module
                 raise TdlError.new("GenerateBlock must have belong_to_module")
             end