axi_tdl 0.1.8 → 0.1.19

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Files changed (47) hide show
  1. checksums.yaml +4 -4
  2. data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
  3. data/lib/axi/AXI4/axi4_dpram_cache.rb +2 -2
  4. data/lib/axi/AXI4/axi4_dpram_cache.sv +3 -3
  5. data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
  6. data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
  7. data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
  8. data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
  9. data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
  10. data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
  11. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
  12. data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
  13. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +5 -5
  15. data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
  16. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
  17. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -23
  18. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
  19. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  20. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  21. data/lib/axi_tdl/version.rb +1 -1
  22. data/lib/tdl/Logic/logic_edge.rb +14 -6
  23. data/lib/tdl/Logic/logic_latency.rb +7 -7
  24. data/lib/tdl/auto_script/import_hdl.rb +1 -0
  25. data/lib/tdl/auto_script/import_sdl.rb +43 -1
  26. data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
  27. data/lib/tdl/class_hdl/hdl_data.rb +1 -1
  28. data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
  29. data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
  30. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
  31. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
  32. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
  33. data/lib/tdl/examples/11_test_unit/tu0.sv +3 -6
  34. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  35. data/lib/tdl/examples/9_itegration/dve.tcl +6 -153
  36. data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
  37. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
  38. data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
  39. data/lib/tdl/exlib/axis_verify.rb +2 -2
  40. data/lib/tdl/exlib/logic_verify.rb +1 -1
  41. data/lib/tdl/rebuild_ele/axi4.rb +6 -2
  42. data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
  43. data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
  44. data/lib/tdl/sdlmodule/sdlmodule.rb +17 -1
  45. data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
  46. data/lib/tdl/sdlmodule/test_unit_module.rb +3 -1
  47. metadata +7 -2
@@ -12,8 +12,128 @@ gui_set_time_units 1ps
12
12
  ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
+ ## -------------- sub_md0_logic -------------------------
16
+ set _wave_session_group_sub_md0_logic sub_md0_logic
17
+ # set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
18
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
19
+ set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
20
+ }
21
+ set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
22
+
23
+ ## 添加信号到 group
24
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt} }
25
+ ## ============== sub_md0_logic =========================
26
+
27
+
28
+ ## -------------- sub_md0_interface -------------------------
29
+ set _wave_session_group_sub_md0_interface sub_md0_interface
30
+ # set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
31
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
32
+ set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
33
+ }
34
+ set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
35
+
36
+ ## 添加信号到 group
37
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.axis_in} }
38
+ ## ============== sub_md0_interface =========================
39
+
40
+
41
+ ## -------------- sub_md0_default -------------------------
42
+ set _wave_session_group_sub_md0_default sub_md0_default
43
+ # set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
44
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
45
+ set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
46
+ }
47
+ set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
48
+
49
+ ## 添加信号到 group
50
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
51
+ ## ============== sub_md0_default =========================
52
+
53
+
54
+ ## -------------- sub_md0_default.inter_tf -------------------------
55
+ ## set _wave_session_group_sub_md0_default_inter_tf Group1
56
+ ## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
15
57
 
58
+ set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
59
+ append _wave_session_group_sub_md0_default_inter_tf inter_tf
60
+ set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
61
+
62
+ # set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
63
+
64
+ ## 添加信号到 group
65
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.inter_tf} }
66
+ ## ============== sub_md0_default.inter_tf =========================
67
+
68
+
69
+ ## -------------- sub_md1_default -------------------------
70
+ set _wave_session_group_sub_md1_default sub_md1_default
71
+ # set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
72
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
73
+ set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
74
+ }
75
+ set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
76
+
77
+ ## 添加信号到 group
78
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable} }
79
+ ## ============== sub_md1_default =========================
80
+
81
+
82
+ ## -------------- sub_md1_inner -------------------------
83
+ set _wave_session_group_sub_md1_inner sub_md1_inner
84
+ # set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
85
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
86
+ set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
87
+ }
88
+ set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
89
+
90
+ ## 添加信号到 group
91
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
92
+ ## ============== sub_md1_inner =========================
93
+
16
94
 
95
+ ## -------------- sub_md1_inner.inter_tf -------------------------
96
+ ## set _wave_session_group_sub_md1_inner_inter_tf Group1
97
+ ## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
98
+
99
+ set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
100
+ append _wave_session_group_sub_md1_inner_inter_tf inter_tf
101
+ set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
102
+
103
+ # set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
104
+
105
+ ## 添加信号到 group
106
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.inter_tf} }
107
+ ## ============== sub_md1_inner.inter_tf =========================
108
+
109
+
110
+ ## -------------- exp_test_unit_sim_default -------------------------
111
+ set _wave_session_group_exp_test_unit_sim_default exp_test_unit_sim_default
112
+ # set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name -seed exp_test_unit_sim_default]
113
+ if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_sim_default"]} {
114
+ set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name]
115
+ }
116
+ set Group2_exp_test_unit_sim_default "$_wave_session_group_exp_test_unit_sim_default"
117
+
118
+ ## 添加信号到 group
119
+ gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default" { }
120
+ ## ============== exp_test_unit_sim_default =========================
121
+
122
+
123
+ ## -------------- exp_test_unit_sim_default.axis_data_inf -------------------------
124
+ ## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf Group1
125
+ ## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_sim_default ]
126
+
127
+ set _wave_session_group_exp_test_unit_sim_default_axis_data_inf $_wave_session_group_exp_test_unit_sim_default|
128
+ append _wave_session_group_exp_test_unit_sim_default_axis_data_inf axis_data_inf
129
+ set exp_test_unit_sim_default|axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
130
+
131
+ # set Group2_exp_test_unit_sim_default_axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
132
+
133
+ ## 添加信号到 group
134
+ gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf" { {Sim:tb_exp_test_unit_sim.rtl_top.axis_data_inf} }
135
+ ## ============== exp_test_unit_sim_default.axis_data_inf =========================
136
+
17
137
 
18
138
  ## 创建波形窗口
19
139
  if {![info exists useOldWindow]} {
@@ -42,9 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
42
162
  ## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
43
163
  ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
44
164
  ## === [add_signal_wave] === ##
45
-
46
-
47
-
165
+ ## -------------- Group2_sub_md0_logic -------------------------
166
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
167
+ ## ============== Group2_sub_md0_logic =========================
168
+ ## -------------- Group2_sub_md0_interface -------------------------
169
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
170
+ ## ============== Group2_sub_md0_interface =========================
171
+ ## -------------- Group2_sub_md0_default -------------------------
172
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
173
+ ## ============== Group2_sub_md0_default =========================
174
+ ## -------------- sub_md0_default|inter_tf -------------------------
175
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
176
+ ## ============== sub_md0_default|inter_tf =========================
177
+ ## -------------- Group2_sub_md1_default -------------------------
178
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
179
+ ## ============== Group2_sub_md1_default =========================
180
+ ## -------------- Group2_sub_md1_inner -------------------------
181
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
182
+ ## ============== Group2_sub_md1_inner =========================
183
+ ## -------------- sub_md1_inner|inter_tf -------------------------
184
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
185
+ ## ============== sub_md1_inner|inter_tf =========================
186
+ ## -------------- Group2_exp_test_unit_sim_default -------------------------
187
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_sim_default}]
188
+ ## ============== Group2_exp_test_unit_sim_default =========================
189
+ ## -------------- exp_test_unit_sim_default|axis_data_inf -------------------------
190
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_sim_default|axis_data_inf}]
191
+ ## ============== exp_test_unit_sim_default|axis_data_inf =========================
48
192
 
49
193
  gui_seek_criteria -id ${Wave.3} {Any Edge}
50
194
 
@@ -61,9 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
61
205
  gui_list_set_filter -id ${Wave.3} -text {*}
62
206
  ##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
63
207
  ## === [add_bar] === ##
64
-
65
-
66
-
208
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
209
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
210
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
211
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
212
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
213
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_sim_default} -position in
67
214
 
68
215
  gui_marker_move -id ${Wave.3} {C1} 560248001
69
216
  gui_view_scroll -id ${Wave.3} -vertical -set 35
@@ -31,10 +31,11 @@ TopModule.exp_test_unit(__dir__) do
31
31
  # add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
32
32
 
33
33
  test_unit_init do
34
- sub_md1.enable <= 1.b1
35
- initial_exec("#(1us)")
36
- sub_md1.enable <= 1.b0
37
- initial_exec("#(500us)")
34
+ sub_md0.cnt <= sub_md1.enable + 1
35
+ # sub_md1.enable <= 1.b1
36
+ # initial_exec("#(1us)")
37
+ # sub_md1.enable <= 1.b0
38
+ # initial_exec("#(500us)")
38
39
  end
39
40
 
40
41
  end
@@ -1,35 +1,9 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: 2021-05-04 20:03:48 +0800
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module exp_test_unit (
14
- input clock,
15
- input rst_n
16
- );
17
-
18
- //==========================================================================
19
- //-------- define ----------------------------------------------------------
20
- logic enable;
21
- axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
22
- //==========================================================================
23
- //-------- instance --------------------------------------------------------
24
- sub_md1 sub_md1_inst(
25
- /* axi_stream_inf.master */.axis_out (axis_data_inf ),
26
- /* output */.enable (enable )
27
- );
28
- sub_md0 sub_md0_inst(
29
- /* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
30
- /* input */.enable (enable )
31
- );
32
- //==========================================================================
33
- //-------- expression ------------------------------------------------------
34
1
 
2
+ `timescale 1ns/1ps
3
+ module exp_test_unit();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
35
9
  endmodule
@@ -1,9 +1,35 @@
1
-
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-09-24 23:32:18 +0800
9
+ madified:
10
+ ***********************************************/
2
11
  `timescale 1ns/1ps
3
- module exp_test_unit_sim();
4
- initial begin
5
- #(1us);
6
- $warning("Check TopModule.sim,please!!!");
7
- $stop;
8
- end
12
+
13
+ module exp_test_unit_sim (
14
+ input clock,
15
+ input rst_n
16
+ );
17
+
18
+ //==========================================================================
19
+ //-------- define ----------------------------------------------------------
20
+ logic enable;
21
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
22
+ //==========================================================================
23
+ //-------- instance --------------------------------------------------------
24
+ sub_md1 sub_md1_inst(
25
+ /* axi_stream_inf.master */.axis_out (axis_data_inf ),
26
+ /* output */.enable (enable )
27
+ );
28
+ sub_md0 sub_md0_inst(
29
+ /* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
30
+ /* input */.enable (enable )
31
+ );
32
+ //==========================================================================
33
+ //-------- expression ------------------------------------------------------
34
+
9
35
  endmodule
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-05-04 20:03:48 +0800
8
+ created: 2021-09-24 23:32:18 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -27,12 +27,9 @@ module tu0 (
27
27
  initial begin
28
28
  to_down_pass = 1'b0;
29
29
  wait(from_up_pass);
30
- $root.tb_exp_test_unit.test_unit_region = "tu0";
30
+ $root.tb_exp_test_unit_sim.test_unit_region = "tu0";
31
31
  $display("--------------- Current test_unit <%0s> --------------------", "tu0");
32
- $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
33
- #(1us);
34
- $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
35
- #(500us);
32
+ $root.tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt = ($root.tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable+1);
36
33
  to_down_pass = 1'b1;
37
34
  end
38
35
 
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-05-30 12:21:54 +0800
8
+ created: 2021-09-24 23:32:38 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -12,128 +12,8 @@ gui_set_time_units 1ps
12
12
  ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
- ## -------------- sub_md0_logic -------------------------
16
- set _wave_session_group_sub_md0_logic sub_md0_logic
17
- # set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
18
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
19
- set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
20
- }
21
- set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
22
-
23
- ## 添加信号到 group
24
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
25
- ## ============== sub_md0_logic =========================
26
-
27
-
28
- ## -------------- sub_md0_interface -------------------------
29
- set _wave_session_group_sub_md0_interface sub_md0_interface
30
- # set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
31
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
32
- set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
33
- }
34
- set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
35
-
36
- ## 添加信号到 group
37
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
38
- ## ============== sub_md0_interface =========================
39
-
40
-
41
- ## -------------- sub_md0_default -------------------------
42
- set _wave_session_group_sub_md0_default sub_md0_default
43
- # set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
44
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
45
- set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
46
- }
47
- set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
48
-
49
- ## 添加信号到 group
50
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
51
- ## ============== sub_md0_default =========================
52
-
53
-
54
- ## -------------- sub_md0_default.inter_tf -------------------------
55
- ## set _wave_session_group_sub_md0_default_inter_tf Group1
56
- ## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
57
15
 
58
- set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
59
- append _wave_session_group_sub_md0_default_inter_tf inter_tf
60
- set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
61
-
62
- # set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
63
-
64
- ## 添加信号到 group
65
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
66
- ## ============== sub_md0_default.inter_tf =========================
67
-
68
-
69
- ## -------------- sub_md1_default -------------------------
70
- set _wave_session_group_sub_md1_default sub_md1_default
71
- # set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
72
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
73
- set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
74
- }
75
- set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
76
-
77
- ## 添加信号到 group
78
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
79
- ## ============== sub_md1_default =========================
80
-
81
-
82
- ## -------------- sub_md1_inner -------------------------
83
- set _wave_session_group_sub_md1_inner sub_md1_inner
84
- # set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
85
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
86
- set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
87
- }
88
- set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
89
-
90
- ## 添加信号到 group
91
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
92
- ## ============== sub_md1_inner =========================
93
-
94
16
 
95
- ## -------------- sub_md1_inner.inter_tf -------------------------
96
- ## set _wave_session_group_sub_md1_inner_inter_tf Group1
97
- ## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
98
-
99
- set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
100
- append _wave_session_group_sub_md1_inner_inter_tf inter_tf
101
- set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
102
-
103
- # set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
104
-
105
- ## 添加信号到 group
106
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
107
- ## ============== sub_md1_inner.inter_tf =========================
108
-
109
-
110
- ## -------------- exp_test_unit_default -------------------------
111
- set _wave_session_group_exp_test_unit_default exp_test_unit_default
112
- # set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
113
- if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
114
- set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
115
- }
116
- set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
117
-
118
- ## 添加信号到 group
119
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
120
- ## ============== exp_test_unit_default =========================
121
-
122
-
123
- ## -------------- exp_test_unit_default.axis_data_inf -------------------------
124
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
125
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
126
-
127
- set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
128
- append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
129
- set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
130
-
131
- # set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
132
-
133
- ## 添加信号到 group
134
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
135
- ## ============== exp_test_unit_default.axis_data_inf =========================
136
-
137
17
 
138
18
  ## 创建波形窗口
139
19
  if {![info exists useOldWindow]} {
@@ -162,33 +42,9 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
162
42
  ## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
163
43
  ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
164
44
  ## === [add_signal_wave] === ##
165
- ## -------------- Group2_sub_md0_logic -------------------------
166
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
167
- ## ============== Group2_sub_md0_logic =========================
168
- ## -------------- Group2_sub_md0_interface -------------------------
169
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
170
- ## ============== Group2_sub_md0_interface =========================
171
- ## -------------- Group2_sub_md0_default -------------------------
172
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
173
- ## ============== Group2_sub_md0_default =========================
174
- ## -------------- sub_md0_default|inter_tf -------------------------
175
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
176
- ## ============== sub_md0_default|inter_tf =========================
177
- ## -------------- Group2_sub_md1_default -------------------------
178
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
179
- ## ============== Group2_sub_md1_default =========================
180
- ## -------------- Group2_sub_md1_inner -------------------------
181
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
182
- ## ============== Group2_sub_md1_inner =========================
183
- ## -------------- sub_md1_inner|inter_tf -------------------------
184
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
185
- ## ============== sub_md1_inner|inter_tf =========================
186
- ## -------------- Group2_exp_test_unit_default -------------------------
187
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
188
- ## ============== Group2_exp_test_unit_default =========================
189
- ## -------------- exp_test_unit_default|axis_data_inf -------------------------
190
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
191
- ## ============== exp_test_unit_default|axis_data_inf =========================
45
+
46
+
47
+
192
48
 
193
49
  gui_seek_criteria -id ${Wave.3} {Any Edge}
194
50
 
@@ -205,12 +61,9 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
205
61
  gui_list_set_filter -id ${Wave.3} -text {*}
206
62
  ##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
207
63
  ## === [add_bar] === ##
208
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
209
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
210
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
211
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
212
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
213
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
64
+
65
+
66
+
214
67
 
215
68
  gui_marker_move -id ${Wave.3} {C1} 560248001
216
69
  gui_view_scroll -id ${Wave.3} -vertical -set 35
@@ -1,9 +1,40 @@
1
-
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-09-24 23:32:18 +0800
9
+ madified:
10
+ ***********************************************/
2
11
  `timescale 1ns/1ps
3
- module test_tttop();
4
- initial begin
5
- #(1us);
6
- $warning("Check TopModule.sim,please!!!");
7
- $stop;
8
- end
12
+
13
+ module test_tttop (
14
+ input global_sys_clk
15
+ );
16
+
17
+ //==========================================================================
18
+ //-------- define ----------------------------------------------------------
19
+ logic clock_100M;
20
+ logic rstn_100M;
21
+ axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
+ //==========================================================================
23
+ //-------- instance --------------------------------------------------------
24
+ simple_clock simple_clock_inst(
25
+ /* input clock */.sys_clk (global_sys_clk ),
26
+ /* output clock */.clock (clock_100M ),
27
+ /* output reset */.rst_n (rstn_100M )
28
+ );
29
+ a_test_md a_test_md_inst(
30
+ /* input clock */.clock (clock_100M ),
31
+ /* input reset */.rst (~rstn_100M ),
32
+ /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
+ );
34
+ //==========================================================================
35
+ //-------- expression ------------------------------------------------------
36
+ assign x_origin_inf.axis_tvalid = 1'b0;
37
+ assign x_origin_inf.axis_tdata = '0;
38
+ assign x_origin_inf.axis_tlast = 1'b0;
39
+
9
40
  endmodule
@@ -1,40 +1,9 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: 2021-05-30 12:21:54 +0800
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module test_tttop_sim (
14
- input global_sys_clk
15
- );
16
-
17
- //==========================================================================
18
- //-------- define ----------------------------------------------------------
19
- logic clock_100M;
20
- logic rstn_100M;
21
- axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
22
- //==========================================================================
23
- //-------- instance --------------------------------------------------------
24
- simple_clock simple_clock_inst(
25
- /* input clock */.sys_clk (global_sys_clk ),
26
- /* output clock */.clock (clock_100M ),
27
- /* output reset */.rst_n (rstn_100M )
28
- );
29
- a_test_md a_test_md_inst(
30
- /* input clock */.clock (clock_100M ),
31
- /* input reset */.rst (~rstn_100M ),
32
- /* axi_stream_inf.master */.origin_inf (x_origin_inf )
33
- );
34
- //==========================================================================
35
- //-------- expression ------------------------------------------------------
36
- assign x_origin_inf.axis_tvalid = 1'b0;
37
- assign x_origin_inf.axis_tdata = '0;
38
- assign x_origin_inf.axis_tlast = 1'b0;
39
1
 
2
+ `timescale 1ns/1ps
3
+ module test_tttop_sim();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
40
9
  endmodule
@@ -27,7 +27,7 @@ class AxiStream
27
27
  return AxiTdl::EthernetStreamDefAtom.new(belong_to_module: @belong_to_module, stream: self, start: start, length: length)
28
28
  end
29
29
 
30
- def x_all_bits_slice(name: "slice_#{globle_random_name_flag()}", start: 8*4,length:32)
30
+ def x_all_bits_slice(name: "slice_#{@belong_to_module._auto_name_incr_index_()}", start: 8*4,length:32)
31
31
  raise TdlError.new("#{name} is not ethernet stream, before used it must be call to_eth") unless @__ethernet_type__
32
32
  # @belong_to_module.logic[length] - name
33
33
  @belong_to_module.instance_exec(self,name,start,length,@__ethernet_type__) do |_targget_axis, _name, _start, _length, _ethernet_type|
@@ -130,7 +130,7 @@ class AxiStream
130
130
 
131
131
  def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
132
132
  # raise TdlError.new "file cant be empty" unless file
133
- file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
133
+ file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
134
134
  _sps = nil
135
135
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
136
136
  require_sdl 'axis_sim_master_model.rb'
@@ -218,7 +218,7 @@ class AxiStream
218
218
  def simple_verify_by_coe(file)
219
219
  unless File.file?(file)
220
220
  if file.is_a?(String)
221
- wfile = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
221
+ wfile = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
222
222
  File.open(wfile,'w') do |f|
223
223
  f.puts file
224
224
  end
@@ -59,7 +59,7 @@ class Logic
59
59
  raise TdlError.new(" posedge negedge both nil") unless (posedge || negedge )
60
60
  # raise TdlError.new "file cant be empty" unless file
61
61
 
62
- file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
62
+ file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
63
63
  _len = 1000
64
64
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
65
65
  require_hdl 'logic_sim_model.sv'
@@ -125,9 +125,13 @@ class Axi4 < TdlSpace::TdlBaseInterface
125
125
  return new_obj
126
126
  end
127
127
 
128
- def branch(name:@name,clock:@clock,reset:@reset,mode:@mode,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,dimension:[],freqM:nil)
128
+ def branch(name: nil,clock:@clock,reset:@reset,mode:@mode,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,dimension:[],freqM:nil)
129
129
  # puts "freqM :: ",freqM
130
- a = inherited(name:name,clock:clock,reset:reset,mode:mode,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,addr_step:addr_step,dimension:dimension,freqM:freqM)
130
+ xx_name = name
131
+ ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
132
+ xx_name = name || "#{belong_to_module.module_name}_axi4_branch#{belong_to_module._auto_name_incr_index_()}"
133
+ end
134
+ a = inherited(name:xx_name,clock:clock,reset:reset,mode:mode,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,addr_step:addr_step,dimension:dimension,freqM:freqM)
131
135
  self << a
132
136
  return a
133
137
  end