axi_tdl 0.1.8 → 0.1.19
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +2 -2
- data/lib/axi/AXI4/axi4_dpram_cache.sv +3 -3
- data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +5 -5
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +5 -5
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -23
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +4 -4
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/Logic/logic_edge.rb +14 -6
- data/lib/tdl/Logic/logic_latency.rb +7 -7
- data/lib/tdl/auto_script/import_hdl.rb +1 -0
- data/lib/tdl/auto_script/import_sdl.rb +43 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
- data/lib/tdl/class_hdl/hdl_data.rb +1 -1
- data/lib/tdl/class_hdl/hdl_generate.rb +1 -1
- data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
- data/lib/tdl/examples/11_test_unit/tu0.sv +3 -6
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +6 -153
- data/lib/tdl/examples/9_itegration/test_tttop.sv +38 -7
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +7 -38
- data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
- data/lib/tdl/exlib/axis_verify.rb +2 -2
- data/lib/tdl/exlib/logic_verify.rb +1 -1
- data/lib/tdl/rebuild_ele/axi4.rb +6 -2
- data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
- data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +17 -1
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb +3 -1
- metadata +7 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 57844b234767b1f242f4e45cab8bcf5db08c75d34e00cee9c60589e1b3879a79
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data.tar.gz: d94bd22852a5b0a5f1bb2cc2326a6c67c0ba29875eba154fe001b63021aeb3d2
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 898f843d39f3fe10ef1eab55d83b52bc2cf238e3783d30be95a580b7b91d2e38ef86328bd4f14ed58331b42de41f7554d7c0941551ea0941cc9bb431ceb9a7fd
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data.tar.gz: 5740e4dff8c816d6607bf11d37808d1c32082e495ed7a97ddb6c0915104ee1f47465d0c95bd65529e6d3e422112d621a451e73b5fd183d8f6d558970d14a4618
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@@ -70,6 +70,9 @@ initial begin
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"ONLY_READ_to_ONLY_READ":
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assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_TO_ONLY_WRITE":
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assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
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else $error("SLAVER AXIS MODE != ONLY_WRITE");
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default:
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assert(slaver_inf.MODE == "_____")
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else $error("SLAVER AXIS MODE ERROR") ;
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@@ -88,6 +91,9 @@ initial begin
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"ONLY_READ_to_ONLY_READ":
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assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
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else $error("MASTER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_TO_ONLY_WRITE":
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assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
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else $error("MASTER AXIS MODE != ONLY_WRITE");
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default:
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assert(master_inf.MODE == "_____")
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else $error("MASTER AXIS MODE ERROR");
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@@ -14,8 +14,8 @@ TdlBuild.axi4_dpram_cache(__dir__) do
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cm_ram_inf(dsize: a_inf.dsize,rsize: a_inf.asize,msize: a_inf.DSIZE/8) - 'xram_inf'
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initial do
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assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE != b_inf.ASIZE")
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assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE != b_inf.ASIZE")
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assert(a_inf.ASIZE == b_inf.ASIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.ASIZE, b_inf.ASIZE)
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assert(a_inf.DSIZE == b_inf.DSIZE,"a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>", a_inf.DSIZE, b_inf.DSIZE)
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end
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full_axi4_to_axis.full_axi4_to_axis_ainst do |h|
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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//-------- expression ------------------------------------------------------
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initial begin
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assert(a_inf.ASIZE==b_inf.ASIZE)else begin
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$error("a_inf.ASIZE != b_inf.ASIZE");
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$error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.ASIZE,b_inf.ASIZE);
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$stop;
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end
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assert(a_inf.DSIZE==b_inf.DSIZE)else begin
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$error("a_inf.ASIZE != b_inf.ASIZE");
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$error("a_inf.ASIZE<%0d> != b_inf.ASIZE<%0d>",a_inf.DSIZE,b_inf.DSIZE);
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$stop;
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end
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end
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@@ -0,0 +1,23 @@
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require_shdl 'axi4_dpram_cache'
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TdlBuild.axi4_ram_cache(__dir__) do
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parameter.INIT_FILE ''
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port.axi4.slaver - 'a_inf'
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axi4_dpram_cache.axi4_dpram_cache_inst do |h|
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h.parameter.INIT_FILE param.INIT_FILE
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h.port.axi4.slaver.a_inf a_inf
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h.port.axi4.slaver.b_inf a_inf.copy(name: 'b_inf')
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end
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Assign do
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b_inf.axi_awvalid <= 1.b0
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b_inf.axi_arvalid <= 1.b0
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b_inf.axi_wvalid <= 1.b0
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b_inf.axi_rready <= 1.b1
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b_inf.axi_bready <= 1.b1
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end
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end
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_ram_cache #(
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parameter INIT_FILE = ""
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)(
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axi_inf.slaver a_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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axi_inf #(.DSIZE(a_inf.DSIZE),.IDSIZE(a_inf.IDSIZE),.ASIZE(a_inf.ASIZE),.LSIZE(a_inf.LSIZE),.MODE(a_inf.MODE),.ADDR_STEP(a_inf.ADDR_STEP),.FreqM(a_inf.FreqM)) b_inf (.axi_aclk(a_inf.axi_aclk),.axi_aresetn(a_inf.axi_aresetn)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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axi4_dpram_cache #(
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.INIT_FILE (INIT_FILE )
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)axi4_dpram_cache_inst(
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/* axi_inf.slaver */.a_inf (a_inf ),
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/* axi_inf.slaver */.b_inf (b_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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assign b_inf.axi_awvalid = 1'b0;
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assign b_inf.axi_arvalid = 1'b0;
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assign b_inf.axi_wvalid = 1'b0;
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assign b_inf.axi_rready = 1'b1;
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assign b_inf.axi_bready = 1'b1;
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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it burst next after current be responed
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author : Cook.Darwin
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Version: VERA.1.0
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dont wait last
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Version: VERA.2.0
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ex wait
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creaded: 2017/3/1
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi4_rd_auxiliary_gen_A2 (
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input ex_wait_nofull,
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axi_stream_inf.slaver id_add_len_in, //tlast is not necessary
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axi_inf.master_rd_aux axi_rd_aux
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);
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logic clock,rst_n;
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assign clock = axi_rd_aux.axi_aclk;
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assign rst_n = axi_rd_aux.axi_aresetn;
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typedef enum {IDLE,SET_AR,WAIT_EMPTY} STATUS;
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STATUS nstate,cstate;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) cstate = IDLE;
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else cstate = nstate;
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logic cmd_fifo_empty;
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logic cmd_fifo_full;
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always_comb
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case(cstate)
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IDLE:
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if(id_add_len_in.axis_tvalid && id_add_len_in.axis_tready)
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nstate = SET_AR;
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else nstate = IDLE;
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SET_AR:
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if(axi_rd_aux.axi_arvalid && axi_rd_aux.axi_arready)
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nstate = WAIT_EMPTY;
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else nstate = SET_AR;
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WAIT_EMPTY:
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if(!cmd_fifo_full && ex_wait_nofull)
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nstate = IDLE;
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else nstate = WAIT_EMPTY;
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default: nstate = IDLE;
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endcase
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logic [axi_rd_aux.ASIZE-1:0] addr;
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logic [axi_rd_aux.IDSIZE-1:0] id;
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logic [axi_rd_aux.LSIZE-1:0] length;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) {id,addr,length} <= '0;
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else begin
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if(id_add_len_in.axis_tvalid && id_add_len_in.axis_tready)
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{id,addr,length} <= id_add_len_in.axis_tdata;
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else {id,addr,length} <= {id,addr,length};
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end
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assign axi_rd_aux.axi_araddr = addr;
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assign axi_rd_aux.axi_arlen = length;
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assign axi_rd_aux.axi_arid = id;
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always@(posedge clock,negedge rst_n)
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if(~rst_n) axi_rd_aux.axi_arvalid <= 1'b0;
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else
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case(nstate)
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SET_AR: axi_rd_aux.axi_arvalid <= 1'b1;
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default:axi_rd_aux.axi_arvalid <= 1'b0;
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endcase
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always@(posedge clock,negedge rst_n)
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if(~rst_n) id_add_len_in.axis_tready <= 1'b0;
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else
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case(nstate)
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IDLE: id_add_len_in.axis_tready <= 1'b1;
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default:id_add_len_in.axis_tready <= 1'b0;
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endcase
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//--->> CMD FIFO <<--------------
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common_fifo #(
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.DEPTH (4 ),
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.DSIZE (axi_rd_aux.IDSIZE )
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)common_fifo_inst(
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/* input */ .clock (clock ),
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/* input */ .rst_n (rst_n ),
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/* input [DSIZE-1:0] */ .wdata (axi_rd_aux.axi_arid ),
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/* input */ .wr_en ((axi_rd_aux.axi_arvalid && axi_rd_aux.axi_arready)),
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/* output logic[DSIZE-1:0] */ .rdata (),
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/* input */ .rd_en ((axi_rd_aux.axi_rvalid && axi_rd_aux.axi_rready && axi_rd_aux.axi_rlast)),
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/* output logic[CSIZE-1:0] */ .count (),
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/* output logic */ .empty (cmd_fifo_empty ),
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/* output logic */ .full (cmd_fifo_full )
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);
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//---<< CMD FIFO >>--------------
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//-->> TRACK <<-----------------
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// (* dont_touch="true" *)
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// logic [axi_rd_aux.LSIZE-1:0] rcnt;
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// always@(posedge clock,negedge rst_n)
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// if(~rst_n) rcnt <= '0;
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// else rcnt <= axi_rd_aux.axi_rcnt;
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//--<< TRACK >>-----------------
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endmodule
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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-
creaded:
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM))
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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60
60
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
61
61
|
//==========================================================================
|
62
62
|
//-------- instance --------------------------------------------------------
|
@@ -94,13 +94,13 @@ independent_clock_fifo #(
|
|
94
94
|
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
95
95
|
/* output */.stream_en (stream_en ),
|
96
96
|
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
97
|
-
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
|
97
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R0000 )
|
98
98
|
);
|
99
99
|
vcs_axi4_comptable #(
|
100
100
|
.ORIGIN ("master_wr_aux_no_resp" ),
|
101
101
|
.TO ("master_wr" )
|
102
|
-
)
|
103
|
-
/* input */.origin (
|
102
|
+
)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
|
103
|
+
/* input */.origin (axi_wr_vcs_cp_R0000 ),
|
104
104
|
/* output */.to (axi_wr )
|
105
105
|
);
|
106
106
|
axis_valve_with_pipe #(
|
@@ -0,0 +1,113 @@
|
|
1
|
+
# require_relative "../prj_lib"
|
2
|
+
require_hdl "axis_length_split_with_addr.sv"
|
3
|
+
require_hdl 'axi_stream_long_fifo_verb.sv'
|
4
|
+
require_shdl 'axi4_wr_auxiliary_gen_without_resp','axis_valve_with_pipe'
|
5
|
+
|
6
|
+
TdlBuild.long_axis_to_axi4_wr(__dir__) do
|
7
|
+
parameter.BYTE_DEPTH 8192*2
|
8
|
+
|
9
|
+
input[32] - :addr
|
10
|
+
input[32] - :max_length
|
11
|
+
port.axis.slaver - 'axis_in'
|
12
|
+
port.axi4.master_wr - 'axi_wr'
|
13
|
+
|
14
|
+
Initial do
|
15
|
+
assert(axis_in.DSIZE == axi_wr.DSIZE, "STREAM DSIZE<%d> should eql AXI4 DSIZE<%d>",axis_in.DSIZE, axi_wr.DSIZE)
|
16
|
+
end
|
17
|
+
|
18
|
+
Def().logic(name: "addr_cur",dsize:32)
|
19
|
+
|
20
|
+
axis_length_split_with_addr.axis_length_split_with_addr_inst do |h|
|
21
|
+
h.param.ADDR_STEP axi_wr.ADDR_STEP
|
22
|
+
h.origin_addr addr
|
23
|
+
h.length max_length
|
24
|
+
h.band_addr addr_cur
|
25
|
+
h.axis_in axis_in
|
26
|
+
h.axis_out axis_in.copy(name: 'split_out')
|
27
|
+
end
|
28
|
+
|
29
|
+
axi_stream_long_fifo_verb.axi_stream_long_fifo_verb_inst do |h|
|
30
|
+
h.param.DEPTH 4
|
31
|
+
h.param.BYTE_DEPTH param.BYTE_DEPTH
|
32
|
+
h.port.axis.slaver.axis_in split_out
|
33
|
+
h.port.axis.master.axis_out split_out.copy(name:'fifo_axis',clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:axis_in.DSIZE)
|
34
|
+
end
|
35
|
+
|
36
|
+
Def().logic(name: :id,dsize:axi_wr.idsize)
|
37
|
+
Def().logic(name: :addr_s,dsize:axi_wr.asize)
|
38
|
+
Def().logic(name: :len_s,dsize:axi_wr.lsize)
|
39
|
+
|
40
|
+
Instance(:independent_clock_fifo,"independent_clock_fifo_inst") do |h|
|
41
|
+
h[:DEPTH] = 4
|
42
|
+
h[:DSIZE] = NqString.new("#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
43
|
+
h[:wr_clk] = axis_in.aclk
|
44
|
+
h[:wr_rst_n] = axis_in.aresetn
|
45
|
+
h[:rd_clk] = axi_wr.axi_aclk
|
46
|
+
h[:rd_rst_n] = axi_wr.axi_aresetn
|
47
|
+
h[:wdata] = "{#{id.s},#{addr_s.s},#{len_s.s}}".to_nq
|
48
|
+
h[:wr_en] = split_out.vld_rdy_last
|
49
|
+
h[:rdata] = Def().logic(name:"fifo_rdata",dsize:h[:DSIZE])
|
50
|
+
h[:rd_en] = Def().logic(name:"fifo_rd_en")
|
51
|
+
h[:empty] = Def().logic(name:"fifo_empty")
|
52
|
+
h[:full] = Def().logic(name:"fifo_full")
|
53
|
+
end
|
54
|
+
|
55
|
+
# AxiStream.axi4_wr_auxiliary_gen_without_resp(
|
56
|
+
# stream_en: Def().logic(name:"stream_en"),
|
57
|
+
# id_add_len_in: Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}"),
|
58
|
+
# axi_wr_aux: axi_wr,
|
59
|
+
# belong_to_module: self
|
60
|
+
# )
|
61
|
+
|
62
|
+
Instance(:axi4_wr_auxiliary_gen_without_resp,"axi4_wr_auxiliary_gen_without_resp_inst") do |h|
|
63
|
+
h[:stream_en] = Def().logic(name: "stream_en")
|
64
|
+
# h[:id_add_len_in] = Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
65
|
+
h[:id_add_len_in] = axi_stream_inf(clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}".to_nq).id_add_len_in
|
66
|
+
h[:axi_wr_aux] = axi_wr
|
67
|
+
end
|
68
|
+
|
69
|
+
Always(posedge:axis_in.aclk,negedge:axis_in.aresetn) do
|
70
|
+
IF ~axis_in.aresetn do
|
71
|
+
id <= 0
|
72
|
+
end
|
73
|
+
ELSIF split_out.vld_rdy_last do
|
74
|
+
id <= id + 1
|
75
|
+
end
|
76
|
+
ELSE do
|
77
|
+
id <= id
|
78
|
+
end
|
79
|
+
end
|
80
|
+
|
81
|
+
Assign do
|
82
|
+
addr_s <= addr_cur
|
83
|
+
len_s <= split_out.axis_tcnt
|
84
|
+
id_add_len_in.axis_tvalid <= ~independent_clock_fifo_inst[:empty]
|
85
|
+
id_add_len_in.axis_tdata <= independent_clock_fifo_inst[:rdata]
|
86
|
+
id_add_len_in.axis_tlast <= 1.b1
|
87
|
+
independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
|
88
|
+
end
|
89
|
+
|
90
|
+
# pipe_axis = AxiStream.axis_valve_with_pipe(
|
91
|
+
# mode: "OUT",
|
92
|
+
# button: stream_en,
|
93
|
+
# up_stream: fifo_axis,
|
94
|
+
# belong_to_module:self)
|
95
|
+
|
96
|
+
axis_valve_with_pipe.axis_valve_with_pipe_inst do |h|
|
97
|
+
h.parameter.MODE "OUT"
|
98
|
+
h.input.button stream_en # //[1] OPEN ; [0] CLOSE
|
99
|
+
h.axis_in fifo_axis
|
100
|
+
h.axis_out fifo_axis.copy(name: 'pipe_axis')
|
101
|
+
end
|
102
|
+
|
103
|
+
Assign do
|
104
|
+
axi_wr.axi_wdata <= pipe_axis.axis_tdata
|
105
|
+
axi_wr.axi_wstrb <= ~pipe_axis.axis_tkeep
|
106
|
+
axi_wr.axi_wvalid <= pipe_axis.axis_tvalid
|
107
|
+
axi_wr.axi_wlast <= pipe_axis.axis_tlast
|
108
|
+
pipe_axis.axis_tready <= axi_wr.axi_wready
|
109
|
+
axi_wr.axi_bready <= 1.b1
|
110
|
+
end
|
111
|
+
|
112
|
+
|
113
|
+
end
|
@@ -0,0 +1,125 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: XXXX.XX.XX
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module long_axis_to_axi4_wr #(
|
14
|
+
parameter BYTE_DEPTH = 16384
|
15
|
+
)(
|
16
|
+
input [31:0] addr,
|
17
|
+
input [31:0] max_length,
|
18
|
+
axi_stream_inf.slaver axis_in,
|
19
|
+
axi_inf.master_wr axi_wr
|
20
|
+
);
|
21
|
+
|
22
|
+
//==========================================================================
|
23
|
+
//-------- define ----------------------------------------------------------
|
24
|
+
logic [32-1:0] addr_cur ;
|
25
|
+
logic [axi_wr.IDSIZE-1:0] id ;
|
26
|
+
logic [axi_wr.ASIZE-1:0] addr_s ;
|
27
|
+
logic [axi_wr.LSIZE-1:0] len_s ;
|
28
|
+
logic [axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE-1:0] fifo_rdata ;
|
29
|
+
logic fifo_rd_en;
|
30
|
+
logic fifo_empty;
|
31
|
+
logic fifo_full;
|
32
|
+
logic stream_en;
|
33
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
|
34
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
35
|
+
axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
36
|
+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
|
37
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
38
|
+
//==========================================================================
|
39
|
+
//-------- instance --------------------------------------------------------
|
40
|
+
axis_length_split_with_addr #(
|
41
|
+
.ADDR_STEP (axi_wr.ADDR_STEP )
|
42
|
+
)axis_length_split_with_addr_inst(
|
43
|
+
/* input */.origin_addr (addr ),
|
44
|
+
/* input */.length (max_length ),
|
45
|
+
/* output */.band_addr (addr_cur ),
|
46
|
+
/* axi_stream_inf.slaver */.axis_in (axis_in ),
|
47
|
+
/* axi_stream_inf.master */.axis_out (split_out )
|
48
|
+
);
|
49
|
+
axi_stream_long_fifo_verb #(
|
50
|
+
.DEPTH (4 ),
|
51
|
+
.BYTE_DEPTH (BYTE_DEPTH )
|
52
|
+
)axi_stream_long_fifo_verb_inst(
|
53
|
+
/* axi_stream_inf.slaver */.axis_in (split_out ),
|
54
|
+
/* axi_stream_inf.master */.axis_out (fifo_axis )
|
55
|
+
);
|
56
|
+
independent_clock_fifo #(
|
57
|
+
.DEPTH (4 ),
|
58
|
+
.DSIZE (axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE )
|
59
|
+
)independent_clock_fifo_inst(
|
60
|
+
/* input */.wr_clk (axis_in.aclk ),
|
61
|
+
/* input */.wr_rst_n (axis_in.aresetn ),
|
62
|
+
/* input */.rd_clk (axi_wr.axi_aclk ),
|
63
|
+
/* input */.rd_rst_n (axi_wr.axi_aresetn ),
|
64
|
+
/* input */.wdata ({id[axi_wr.IDSIZE-1:0],addr_s[axi_wr.ASIZE-1:0],len_s[axi_wr.LSIZE-1:0]} ),
|
65
|
+
/* input */.wr_en (split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast ),
|
66
|
+
/* output */.rdata (fifo_rdata ),
|
67
|
+
/* input */.rd_en (fifo_rd_en ),
|
68
|
+
/* output */.empty (fifo_empty ),
|
69
|
+
/* output */.full (fifo_full )
|
70
|
+
);
|
71
|
+
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
72
|
+
/* output */.stream_en (stream_en ),
|
73
|
+
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
74
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R0000 )
|
75
|
+
);
|
76
|
+
vcs_axi4_comptable #(
|
77
|
+
.ORIGIN ("master_wr_aux_no_resp" ),
|
78
|
+
.TO ("master_wr" )
|
79
|
+
)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
|
80
|
+
/* input */.origin (axi_wr_vcs_cp_R0000 ),
|
81
|
+
/* output */.to (axi_wr )
|
82
|
+
);
|
83
|
+
axis_valve_with_pipe #(
|
84
|
+
.MODE ("OUT" )
|
85
|
+
)axis_valve_with_pipe_inst(
|
86
|
+
/* input */.button (stream_en ),
|
87
|
+
/* axi_stream_inf.slaver */.axis_in (fifo_axis ),
|
88
|
+
/* axi_stream_inf.master */.axis_out (pipe_axis )
|
89
|
+
);
|
90
|
+
//==========================================================================
|
91
|
+
//-------- expression ------------------------------------------------------
|
92
|
+
initial begin
|
93
|
+
assert(axis_in.DSIZE==axi_wr.DSIZE)else begin
|
94
|
+
$error("STREAM DSIZE<%d> should eql AXI4 DSIZE<%d>",axis_in.DSIZE,axi_wr.DSIZE);
|
95
|
+
$stop;
|
96
|
+
end
|
97
|
+
end
|
98
|
+
|
99
|
+
always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
|
100
|
+
if(~axis_in.aresetn)begin
|
101
|
+
id <= 0;
|
102
|
+
end
|
103
|
+
else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
|
104
|
+
id <= (id+1);
|
105
|
+
end
|
106
|
+
else begin
|
107
|
+
id <= id;
|
108
|
+
end
|
109
|
+
end
|
110
|
+
|
111
|
+
assign addr_s = addr_cur;
|
112
|
+
assign len_s = split_out.axis_tcnt;
|
113
|
+
assign id_add_len_in.axis_tvalid = ~fifo_empty;
|
114
|
+
assign id_add_len_in.axis_tdata = fifo_rdata;
|
115
|
+
assign id_add_len_in.axis_tlast = 1'b1;
|
116
|
+
assign fifo_rd_en = id_add_len_in.axis_tready;
|
117
|
+
|
118
|
+
assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
|
119
|
+
assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
|
120
|
+
assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
|
121
|
+
assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
|
122
|
+
assign pipe_axis.axis_tready = axi_wr.axi_wready;
|
123
|
+
assign axi_wr.axi_bready = 1'b1;
|
124
|
+
|
125
|
+
endmodule
|
@@ -10,6 +10,8 @@ Version: VERA.2.0 ###### Tue Jan 7 09:47:51 CST 2020
|
|
10
10
|
data_inf_c replace valid ready
|
11
11
|
Version: VERA.3.0 ###### Mon Sep 21 14:31:30 CST 2020
|
12
12
|
add ex info
|
13
|
+
Version: VERA.3.1
|
14
|
+
use axi4_rd_auxiliary_gen_A2
|
13
15
|
creaded: 2017/3/1 下午6:12:34
|
14
16
|
madified:
|
15
17
|
***********************************************/
|
@@ -75,10 +77,13 @@ assign id = '0;
|
|
75
77
|
assign addr = fifo_addr[axi_master.ASIZE-1:0];
|
76
78
|
assign length = fifo_size[axi_master.LSIZE:0];
|
77
79
|
|
80
|
+
logic ex_wait_nofull;
|
81
|
+
|
78
82
|
assign addr_len_inf.axis_tdata = {id,addr,length};
|
79
83
|
|
80
84
|
`VCS_AXI4_CPT_LT(axi_master,master_rd,master_rd_aux,)
|
81
|
-
|
85
|
+
axi4_rd_auxiliary_gen_A2 axi4_rd_auxiliary_gen_inst(
|
86
|
+
/* input */ .ex_wait_nofull (ex_wait_nofull ),
|
82
87
|
/* axi_stream_inf.slaver */ .id_add_len_in (addr_len_inf ), //tlast is not necessary
|
83
88
|
/* axi_inf.master_rd_aux */ .axi_rd_aux (`axi_master_vcs_cpt )
|
84
89
|
);
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@@ -98,7 +103,7 @@ logic [out_axis.DSIZE+1-1:0] axis_fifo_rd_data;
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logic force_rd_en;
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-
logic cmded_empty;
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106
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+
logic cmded_empty,cmded_full;
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independent_clock_fifo #(
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.DEPTH (4 ),
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@@ -113,12 +118,15 @@ independent_clock_fifo #(
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/* output logic[DSIZE-1:0] */ .rdata (),
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/* input */ .rd_en (out_axis.axis_tvalid && out_axis.axis_tready && out_axis.axis_tlast),
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/* output logic */ .empty (cmded_empty ),
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-
/* output logic */ .full ()
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121
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+
/* output logic */ .full (cmded_full )
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);
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assign force_rd_en = cmded_empty && !axis_fifo_empty;
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+
assign ex_wait_nofull = !cmded_full;
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//---<< forece rd_en >>---------------------------
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+
logic[axi_master.DSIZE-1:0] tmp_data;
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+
assign tmp_data = axi_master.axi_rdata;
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xilinx_fifo_verb #(
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//xilinx_fifo #(
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.DSIZE (out_axis.DSIZE+1 )
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@@ -127,7 +135,7 @@ xilinx_fifo_verb #(
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/* input */ .wr_rst (!axi_master.axi_aresetn),
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/* input */ .rd_clk (out_axis.aclk ),
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/* input */ .rd_rst (!out_axis.aresetn ),
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-
/* input [DSIZE-1:0] */ .din ({axi_master.axi_rlast,
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+
/* input [DSIZE-1:0] */ .din ({axi_master.axi_rlast,tmp_data} ),
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/* input */ .wr_en ((axi_master.axi_rvalid && axi_master.axi_rready) ),
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/* input */ .rd_en (axis_fifo_rd_en || force_rd_en ),
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/* output [DSIZE-1:0] */ .dout (axis_fifo_rd_data ),
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