axi_tdl 0.1.3 → 0.1.19

data/lib/tdl/examples/6_module_with_interface/inf_collect.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:45 +0800
+created: 2021-05-04 20:03:32 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -24,14 +24,14 @@ module inf_collect (
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
-data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
-axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(8),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
-axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
-axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
-axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
+data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
+data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
+axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
+axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
+axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
+axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 

data/lib/tdl/examples/8_top_module/dve.tcl

@@ -13,6 +13,8 @@ gui_set_time_units 1ps
 ## ==== [add_signal] ===== ##
 
 
+
+
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
     set useOldWindow true
@@ -42,6 +44,8 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## === [add_signal_wave] === ##
 
 
+
+
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
 
@@ -59,6 +63,8 @@ gui_list_set_filter -id ${Wave.3} -text {*}
 ## === [add_bar] === ##
 
 
+
+
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35
 gui_show_grid -id ${Wave.3} -enable false

data/lib/tdl/examples/8_top_module/tb_test_top.sv

@@ -5,11 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:45 +0800
+created: 2021-04-03 14:05:10 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_top();
 //==========================================================================

data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:08 +0800
+created: 2021-04-03 13:35:39 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/8_top_module/test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:45 +0800
+created: 2021-05-30 12:21:54 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-03-20 23:48:13 +0800
+created: 2021-05-04 20:03:49 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -28,6 +28,7 @@ initial begin
     to_down_pass = 1'b0;
     wait(from_up_pass);
     $root.tb_test_tttop_sim.test_unit_region = "test_clock_bb";
+    $display("--------------- Current test_unit <%0s> --------------------", "test_clock_bb");
     to_down_pass = 1'b1;
 end
 

data/lib/tdl/examples/9_itegration/dve.tcl

@@ -13,6 +13,8 @@ gui_set_time_units 1ps
 ## ==== [add_signal] ===== ##
 
 
+
+
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
     set useOldWindow true
@@ -42,6 +44,8 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## === [add_signal_wave] === ##
 
 
+
+
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
 
@@ -59,6 +63,8 @@ gui_list_set_filter -id ${Wave.3} -text {*}
 ## === [add_bar] === ##
 
 
+
+
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35
 gui_show_grid -id ${Wave.3} -enable false

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -5,12 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:45 +0800
+created: 2021-04-03 13:47:04 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_tttop();
 //==========================================================================

data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv

@@ -5,11 +5,10 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 12:39:31 +0800
+created: 2021-04-03 14:05:10 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_tttop_sim();
 //==========================================================================

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 13:14:45 +0800
+created: 2021-09-24 23:32:18 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -18,7 +18,7 @@ module test_tttop (
 //-------- define ----------------------------------------------------------
 logic  clock_100M;
 logic  rstn_100M;
-axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 simple_clock simple_clock_inst(

data/lib/tdl/exlib/axis_eth_ex.rb

@@ -27,7 +27,7 @@ class AxiStream
         return AxiTdl::EthernetStreamDefAtom.new(belong_to_module: @belong_to_module, stream: self, start: start, length: length)
     end
 
-    def x_all_bits_slice(name: "slice_#{globle_random_name_flag()}", start: 8*4,length:32)
+    def x_all_bits_slice(name: "slice_#{@belong_to_module._auto_name_incr_index_()}", start: 8*4,length:32)
         raise TdlError.new("#{name} is not ethernet stream, before used it must be call to_eth") unless @__ethernet_type__
         # @belong_to_module.logic[length]     - name
         @belong_to_module.instance_exec(self,name,start,length,@__ethernet_type__) do |_targget_axis, _name, _start, _length, _ethernet_type|

data/lib/tdl/exlib/axis_verify.rb

@@ -130,7 +130,7 @@ class AxiStream
 
     def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
         # raise TdlError.new "file cant be empty"  unless file
-        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
         _sps = nil
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
             require_sdl 'axis_sim_master_model.rb'
@@ -218,7 +218,7 @@ class AxiStream
     def simple_verify_by_coe(file)
         unless File.file?(file)
             if file.is_a?(String)
-                wfile = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+                wfile = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
                 File.open(wfile,'w') do |f|
                     f.puts file
                 end

data/lib/tdl/exlib/constraints_verb.rb

@@ -41,6 +41,7 @@ class ConstraintsVerb
             pulltype = ([pulltype] * pin_name.size ) unless pulltype.is_a? Array
             drive = ([drive] * pin_name.size ) unless drive.is_a? Array
 
+            pin_name = ((pin_name.is_a?(Array) && pin_name) || [pin_name] )
             pin_name.each_index do |index|
                 @package_pin_and_IOSTANDARD << [port_name[index],pin_name[index].to_s.upcase,iostandard[index].to_s.upcase,pulltype[index].to_s,drive[index].to_s]
 

data/lib/tdl/exlib/itegration_verb.rb

@@ -671,39 +671,42 @@ class ItegrationVerb
                 end
             end
             ## 先从 已经加入的隐性itgt搜索
-            @top_module.implicit_itgt_collect.each do |i|
-                explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
-                if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
-                    # puts "Itgt Good"
-                    mark = true
-                    unless self.respond_to? e
-                        define_singleton_method(e) do
-                            ## 如果从其他模块调用则出发 dynac_active
-                            ItegrationVerbAgent.new(i)
+            ## 去除隐性引入
+            unless TopModule.itgt_implicit_reject
+                @top_module.implicit_itgt_collect.each do |i|
+                    explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
+                    if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
+                        # puts "Itgt Good"
+                        mark = true
+                        unless self.respond_to? e
+                            define_singleton_method(e) do
+                                ## 如果从其他模块调用则出发 dynac_active
+                                ItegrationVerbAgent.new(i)
+                            end
+                            i.link_eval
+                            i.child_inst_itgt << self
                         end
-                        i.link_eval
-                        i.child_inst_itgt << self
+                        break
                     end
-                    break
                 end
-            end
-            next if mark    ## 找到了 就处理下一个Link
-            ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
-            @@child.each do |c|
-                explort_attrs = c.get_itgt_var('itegration_explort_collect')
-                # puts explort_attrs
-                if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
-                    # puts "Child Good"
-                    isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
-                    @top_module.implicit_itgt_collect << isp
-                    ## 如果是隐性添加，先不要加入pin_map
-                    define_singleton_method(e) do
-                        ItegrationVerbAgent.new(isp)
+                next if mark    ## 找到了 就处理下一个Link
+                ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
+                @@child.each do |c|
+                    explort_attrs = c.get_itgt_var('itegration_explort_collect')
+                    # puts explort_attrs
+                    if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
+                        # puts "Child Good"
+                        isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
+                        @top_module.implicit_itgt_collect << isp
+                        ## 如果是隐性添加，先不要加入pin_map
+                        define_singleton_method(e) do
+                            ItegrationVerbAgent.new(isp)
+                        end
+                        isp.link_eval
+                        isp.child_inst_itgt << self
+                        mark = true
+                        break
                     end
-                    isp.link_eval
-                    isp.child_inst_itgt << self
-                    mark = true
-                    break
                 end
             end
 
@@ -736,18 +739,21 @@ class ItegrationVerb
             next if mark    ## 找到了 就处理下一个Link
             ##
             ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
-            @@child.each do |c|
-                explort_attrs = c.get_itgt_var('itegration_explort_collect')
-                if (explort_attrs & container_attrs).sort == container_attrs.sort
-                    isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
-                    @top_module.implicit_itgt_collect << isp
-                    ## 如果是隐性添加，先不要加入pin_map
+            ## 去除隐性引入
+            unless TopModule.itgt_implicit_reject
+                @@child.each do |c|
+                    explort_attrs = c.get_itgt_var('itegration_explort_collect')
+                    if (explort_attrs & container_attrs).sort == container_attrs.sort
+                        isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
+                        @top_module.implicit_itgt_collect << isp
+                        ## 如果是隐性添加，先不要加入pin_map
 
-                    define_singleton_method(e) do
-                        ItegrationVerbAgent.new(isp)
+                        define_singleton_method(e) do
+                            ItegrationVerbAgent.new(isp)
+                        end
+                        mark = true
+                        break
                     end
-                    mark = true
-                    break
                 end
             end
 

data/lib/tdl/exlib/logic_verify.rb

@@ -59,7 +59,7 @@ class Logic
         raise TdlError.new(" posedge negedge both nil") unless (posedge || negedge )
         # raise TdlError.new "file cant be empty"  unless file
 
-        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{@belong_to_module._auto_name_incr_index_}.coe")
         _len = 1000
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
             require_hdl 'logic_sim_model.sv'

data/lib/tdl/rebuild_ele/axi4.rb

@@ -125,9 +125,13 @@ class Axi4 < TdlSpace::TdlBaseInterface
         return new_obj
     end
 
-    def branch(name:@name,clock:@clock,reset:@reset,mode:@mode,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,dimension:[],freqM:nil)
+    def branch(name: nil,clock:@clock,reset:@reset,mode:@mode,dsize:@dsize,idsize:@idsize,asize:@asize,lsize:@lsize,addr_step:@addr_step,dimension:[],freqM:nil)
         # puts "freqM :: ",freqM
-        a = inherited(name:name,clock:clock,reset:reset,mode:mode,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,addr_step:addr_step,dimension:dimension,freqM:freqM)
+        xx_name = name
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
+            xx_name = name || "#{belong_to_module.module_name}_axi4_branch#{belong_to_module._auto_name_incr_index_()}"
+        end
+        a = inherited(name:xx_name,clock:clock,reset:reset,mode:mode,dsize:dsize,idsize:idsize,asize:asize,lsize:lsize,addr_step:addr_step,dimension:dimension,freqM:freqM)
         self << a
         return a
     end

data/lib/tdl/rebuild_ele/axi_stream.rb

@@ -62,7 +62,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
     def inherited(name: nil ,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
         a = nil 
         unless name 
-            name = "#{inst_name}_inherited#{globle_random_name_flag()}"
+            name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
         end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
             append_name = name_copy(name)
@@ -88,7 +88,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
 
     ## =======================
     def self.leave_empty(curr_type: :master,dsize:8,clock:"",reset:"",belong_to_module:nil)
-        nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{globle_random_name_flag()}"
+        nc = belong_to_module.axi_stream_inf(dsize:dsize,clock:clock,reset:reset) - "empty_axis_#{belong_to_module._auto_name_incr_index_()}"
         # puts belong_to_module.module_name
         if curr_type.to_sym == :slaver
             # self.axis_master_empty(master:nc)
@@ -109,7 +109,7 @@ class AxiStream < TdlSpace::TdlBaseInterface
 
     def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
         unless name 
-            name = "#{inst_name}_branch#{globle_random_name_flag()}"
+            name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
         end
         a =  inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
         self << a

data/lib/tdl/rebuild_ele/data_inf_c.rb

@@ -41,7 +41,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
     def inherited(name: nil,clock: nil,reset: nil,dsize: nil,freqM: nil,dimension:[])
         a = nil 
         unless name 
-            name = "#{inst_name}_inherited#{globle_random_name_flag()}"
+            name = "#{inst_name}_inherited#{belong_to_module._auto_name_incr_index_()}"
         end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
             append_name = name_copy(name)
@@ -71,7 +71,7 @@ class DataInf_C < TdlSpace::TdlBaseInterface
 
     def branch(name: nil,clock:@clock,reset:@reset,dsize:@dsize,freqM:nil)
         unless name 
-            name = "#{inst_name}_branch#{globle_random_name_flag()}"
+            name = "#{inst_name}_branch#{belong_to_module._auto_name_incr_index_()}"
         end
         a =  inherited(name: name,clock: clock,reset: reset,dsize: dsize,freqM: freqM)
         self << a

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -432,11 +432,16 @@ module TdlSpace
                 vv = rel || v[1]
                 # vv = self.send(k) || v[1]
                 ## 不例化 FreqM，FreqM只是为了SDL兼容
-                if vv && k.to_s != 'freqM'
+                # if vv && k.to_s != 'freqM'
+                if vv 
                     if vv.instance_of?(String)
                         str << ".#{v[0]}(\"#{vv}\")"
                     else
-                        str << ".#{v[0]}(#{vv})"
+                        if k.to_s == 'freqM'
+                            str << ".#{v[0]}(#{(respond_to?(:clock) && self.clock.is_a?(Clock) && self.clock.freqM ) || vv})"
+                        else 
+                            str << ".#{v[0]}(#{vv})"
+                        end
                     end
                 end
             end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -411,7 +411,11 @@ class SdlModule
         ref_modules.each do |e| 
             _indexs << index 
             _names << e.module_name
-            _paths << File.expand_path(e.real_sv_path)
+            begin 
+                _paths << File.expand_path(e.real_sv_path)
+            rescue 
+                _paths << " ___ dont have a path !!!!! ____"
+            end
             index += 1
             if e.module_name.size > max_size
                 max_size = e.module_name.size 
@@ -483,3 +487,71 @@ class SdlModule
     end
 
 end
+
+## 迭代 本模块及本模块的子模块
+class SdlModule 
+
+    def all_ref_sdlmodules(&block) 
+        sdlms = instance_and_children_module.values.uniq
+        sdlms = sdlms.map do |e|
+            if e.instance_and_children_module.any? 
+                e.all_ref_sdlmodules(&block)
+            else 
+                e 
+            end
+        end
+        sdlms = sdlms.unshift(self)
+        sdlms = sdlms.flatten
+        sdlms.map(&block)
+    end
+
+end
+
+### 有时候 sdlmodule 引用的是 HDL文件，为了能够 正常引用到 需要特殊处理
+class SdlModule
+    def contain_hdl(*hdl_names)
+        __contain_hdl__(false,*hdl_names)
+    end
+
+    def __contain_hdl__(recreate,*hdl_names)
+        hdl_names = hdl_names.map do |e| 
+
+            if e.include?("/") || e.include?("\\")
+                e 
+            else  
+                
+                ee = find_first_hdl_path(e)
+                if recreate && !ee 
+                    raise TdlError.new("Cant find #{e} in tdl_paths")
+                end
+                ee || e
+            end
+        end 
+        unless recreate
+            @__contain_hdl__ ||= []
+            @__contain_hdl__ += hdl_names
+        else 
+            @__contain_hdl__ = hdl_names
+        end
+        @__contain_hdl__.uniq!
+        @__contain_hdl__
+    end
+
+    def require_hdl(*hdl_path)
+        hdl_path.each do |hp|
+            __require_hdl__(hp,self)
+        end
+    end
+end
+
+## 定义自动变量递增
+class SdlModule
+
+    def _auto_name_incr_index_(flag='R')
+        @__auto_name_incr_index__ ||= 0
+        index = @__auto_name_incr_index__
+        @__auto_name_incr_index__ += 1
+        return "#{flag}#{"%04d" % index}" 
+    end
+
+end

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -57,7 +57,7 @@ class SdlModule
 
             head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
             new_str = head_str+body_str
-            if body_str.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").strip != old_str
+            if body_str.gsub(/\/\/.*/,"").strip != old_str
                 File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
                     f.print new_str
                 end

data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb

@@ -81,7 +81,7 @@ module VCSCompatable
     # end
 
     def self.common_instance(sdlmodule,inst_name,inst_modport,cn_modport)
-        vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{globle_random_name_flag()}")
+        vcs_cpt_inf = cn_modport.inherited(name: "#{cn_modport.name}_vcs_cp_#{sdlmodule._auto_name_incr_index_()}")
         if vcs_cpt_inf.is_a? Axi4 
             # vcs_cpt_inf.origin_freqM   = cn_modport.FreqM
             vcs_cpt_inf.addr_step = cn_modport.ADDR_STEP 
@@ -90,7 +90,7 @@ module VCSCompatable
     
         if inst_modport.modport_type.to_s =~ /master/ || inst_modport.modport_type.to_s == "out_mirror"
             # puts "+++++++ Match Master ModPort ++++++ #{sdlmodule.module_name}"
-            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
+            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
                 h[:ORIGIN]  = "#{inst_modport.modport_type}"
                 h[:TO]      = "#{cn_modport.modport_type}" 
                 h[:origin]  = vcs_cpt_inf
@@ -98,7 +98,7 @@ module VCSCompatable
             end
         elsif inst_modport.modport_type.to_s =~ /slaver/ || inst_modport.modport_type.to_s =~ /mirror/
             # puts "+++++++ Match Slaver ModPort ++++++"
-            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{globle_random_name_flag()}_#{cn_modport.name}_inst") do |h|
+            sdlmodule.Instance(inst_name,"#{inst_name}_#{inst_modport.name}_#{sdlmodule._auto_name_incr_index_()}_#{cn_modport.name}_inst") do |h|
                 h[:TO]      = "#{inst_modport.modport_type}"
                 h[:ORIGIN]  = "#{cn_modport.modport_type}" 
                 h[:to]      = vcs_cpt_inf

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -20,7 +20,9 @@ class SdlModule
         @__track_signals_hash__[flag] ||= Hash.new
 
         if @__track_signals_hash__[flag].has_key?(base_ele)
-            raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
+            # raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!")
+            puts "WAINNING: `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!"
+            return 
         end
 
         @__track_signals_hash__[flag][base_ele] = block
@@ -215,6 +217,7 @@ class TestUnitModule < SdlModule ##TestUnitModule 是在编译完 TopModule TB
             to_down_pass    <= 1.b0
             initial_exec("wait(from_up_pass)")
             initial_exec("$root.#{TopModule.current.techbench.module_name}.test_unit_region = \"#{module_name}\"")
+            initial_exec("$display(\"--------------- Current test_unit <%0s> --------------------\", \"#{module_name}\")")
             block.call ## collect __root_ref_eles__ at here
             to_down_pass    <= 1.b1
         end

data/lib/tdl/sdlmodule/top_module.rb

@@ -340,6 +340,7 @@ endmodule\n"
     end
 
     define_global("sim",nil)
+    define_global("itgt_implicit_reject",nil)
 
 end
 ## 添加 itegration verb
@@ -437,6 +438,9 @@ class TopModule
                 SdlModule.gen_dev_wave_tcl File.join(sdlm.vcs_path,"dve.tcl")
             end
             sdlm.create_xdc
+
+            ## 全局contain_hdl 引入到 TopModule
+            sdlm.contain_hdl(*$__contain_hdl__)
         else 
             sdlm.origin_sv = true 
         end

data/lib/tdl/tdl.rb

@@ -138,7 +138,7 @@ require_relative "./exlib/logic_verify.rb"
 $argvs_hash = {}
 $argvs_hash = Parser.parse($TdlARGV || ARGV) 
 TopModule.sim = $argvs_hash[:sim]
-
+TopModule.itgt_implicit_reject = $argvs_hash[:itgt_implicit_reject]
 class Tdl
 
     def self.comment(c="-",info="_____")
@@ -271,16 +271,6 @@ class Tdl
         puts(pagination("SUMMARY"))
         puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
 
-        ## ----------- 
-        # TopModule.current.ref_modules.uniq.each do |e| 
-        #     unless  e.is_a? ClassHDL::ClearSdlModule
-        #         puts "#{e.real_sv_path}: #{e.module_name}"
-        #     end
-        # end
-        ## ===========
-        # File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
-        #     f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
-        # end
     end
 
 end