axi_tdl 0.1.3 → 0.1.19

data/lib/axi/platform_ip/wide_fifo.sv

@@ -25,7 +25,7 @@ module wide_fifo #(
 );
 
 
-import GlobalPkg::*;
+import SystemPkg::*;
 generate
 if(FAMIRY == "kintexu" || FAMIRY == "ultrascale")begin
 fifo_ku #(

data/lib/axi/platform_ip/xilinx_fifo_verb.sv

@@ -30,7 +30,7 @@ module xilinx_fifo_verb #(
     output [LSIZE-1:0]  wrcount
 );
 
-import GlobalPkg::*;
+import  SystemPkg::*;
 
 parameter LLSIZE =
 (DSIZE>= 37             )?  9 :         //

data/lib/axi/platform_ip/xilinx_fifo_verc.sv

@@ -33,7 +33,8 @@ module xilinx_fifo_verc #(
     // output [LSIZE-1:0]  wrcount
 );
 
-import GlobalPkg::*;
+// import GlobalPkg::*;
+import SystemPkg::*;
 
 // parameter LLSIZE =
 // (DSIZE>= 37             )?  9 :         //

data/lib/axi/techbench/tb_axi_stream_split_channel.rb

@@ -1,3 +1,4 @@
+
 require_relative '../../axi_tdl.rb'
 require_sdl 'axi_stream_split_channel.rb'
 

data/lib/axi/techbench/tb_axi_stream_split_channel.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 12:04:15 +0800
+created: 2021-04-03 14:03:23 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -47,11 +47,11 @@ axis_sim_master_model #(
     .LOOP      ("TRUE" ),
     .RAM_DEPTH (246    )
 )sim_model_inst_origin_inf(
-/* input                 */.enable       (/*unused */                                                                  ),
-/* input                 */.load_trigger (1'b0                                                                         ),
-/* input                 */.total_length (246                                                                          ),
-/* input                 */.mem_file     ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/origin_inf_R1699.coe" ),
-/* axi_stream_inf.master */.out_inf      (origin_inf                                                                   )
+/* input                 */.enable       (1'b1                                                                             ),
+/* input                 */.load_trigger (1'b0                                                                             ),
+/* input                 */.total_length (246                                                                              ),
+/* input                 */.mem_file     ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/coe_origin_inf_R1699.coe" ),
+/* axi_stream_inf.master */.out_inf      (origin_inf                                                                       )
 );
 axis_sim_verify_by_coe #(
     .RAM_DEPTH   (21    ),

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.1.3"
+  VERSION = "0.1.19"
 end

data/lib/axi_tdl.rb

@@ -4,6 +4,7 @@ require "tdl/tdl.rb"
 module AxiTdl
     AXI_PATH = File.expand_path(File.join(__dir__,"axi"))
     TDL_PATH = File.expand_path(File.join(__dir__,"tdl"))
+    PUBLIC_ATOM_PATH = File.expand_path(File.join(__dir__,"public_atom_module"))
 end
 
 
@@ -15,14 +16,43 @@ add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/axi4_pipe"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/interconnect"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/width_convert"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/packet_fifo"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/packet_partition"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/axi4_to_xilinx_ddr_native"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common_fifo"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface")) 
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/techbench"))
-
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/platform_ip"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "public_atom_module"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "public_atom_module/sim"))
 ## base require 
 require_hdl 'axis_master_empty.sv'
 require_hdl 'axis_slaver_empty.sv'
 
+## contain common HDL 
+TopModule.contain_hdl("CheckPClock.sv","edge_generator.v","ClockSameDomain.sv","broaden_and_cross_clk.v","broaden.v","cross_clk_sync.v","latency.v","latency_long.v",'pipe_vld.sv')
+
+### 这里引入可能不合适
+TopModule.contain_hdl('axis_full_to_data_c.sv','data_c_pipe_inf.sv','data_c_to_axis_full.sv')
+TopModule.contain_hdl('axi_stream_interconnect_M2S_A1.sv', 'data_c_pipe_intc_M2S_best_last.sv',"data_pipe_interconnect_S2M_verb.sv","data_valve.sv")
+TopModule.contain_hdl('axis_direct_A1.sv',"axis_direct.sv", 'axi4_direct_A1.sv')
+TopModule.contain_hdl 'axi_stream_interconnect_M2S.sv','data_pipe_interconnect_M2S_verb.sv'
+# TopModule.contain_hdl('simple_data_pipe.sv')
+TopModule.contain_hdl('long_fifo_verb.sv',"long_fifo_4bit.sv","long_fifo_4bit_SL8192.sv","long_fifo_4bit_8192.sv","wide_fifo.sv","wide_fifo_7series.sv")
+
+TopModule.contain_hdl 'width_combin.sv'
+
+TopModule.contain_hdl "data_inf_A2B.sv","data_inf_B2A.sv","data_c_direct.sv"
+
+### 兼容性引入 
+require_hdl 'odata_pool_axi4_A3.sv'
+require_hdl 'axis_append_A1.sv'
+odata_pool_axi4_A3.contain_hdl('axi4_rd_auxiliary_gen_A1.sv',"xilinx_fifo_verb.sv","xilinx_fifo_A1.sv","fifo_36bit.sv","fifo_wr_rd_mark.sv")
+axis_append_A1.contain_hdl('axi_streams_combin_A1.sv','data_c_scaler_A1.sv')
+
+require_hdl 'axis_head_cut.sv'
+axis_head_cut.contain_hdl("axis_filter.sv")
+
+

data/lib/public_atom_module/sim/clock_rst_verc.sv

@@ -0,0 +1,69 @@
+/**********************************************
+______________________________________________
+_______  ___   ___          ___   __   _    _
+_______ |     |   | |\  /| |___  |  \  |   /_\
+_______ |___  |___| | \/ | |___  |__/  |  /   \
+_______________________________________________
+descript:
+author : Young
+Version: VERB.0.0
+	create a module for it
+Version: VERC.0.0 ###### Tue Oct 13 14:44:58 CST 2020
+    add restart
+creaded: 2015/10/16 10:50:52
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* data_inf = "true" *)
+module clock_rst_verc #(
+	parameter bit		ACTIVE			= 1,
+	parameter longint	PERIOD_CNT		= 0,
+	parameter			RST_HOLD		= 5,
+	parameter real		FreqM			= 100
+)(
+    input           reboot,
+	output			clock,
+	output			rst_x
+);
+
+bit clk_pause = 1;
+bit	clock_reg;
+bit	rst_reg;
+
+longint ccnt = 0;
+
+initial begin
+	clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end
+
+
+always@(posedge reboot) begin 
+    clk_pause	= 1;
+	clock_reg	= 0;
+	rst_reg		= ACTIVE;
+	#(1000/FreqM*2);
+	clk_pause	= 0;
+	repeat(RST_HOLD)
+		@(posedge clock_reg);
+	rst_reg		= ~rst_reg;
+end 
+
+always #(1000/FreqM/2) begin
+	if(clk_pause == 0 && (PERIOD_CNT==0 || ccnt < PERIOD_CNT))
+		clock_reg	= ~clock_reg;
+end
+
+always@(posedge clock)
+	ccnt	<= ccnt + 1;
+
+assign	clock	= clock_reg;
+assign	rst_x	= rst_reg;
+
+endmodule

data/lib/public_atom_module/sim_system_pkg.sv

@@ -0,0 +1,4 @@
+package SystemPkg;
+    parameter SIM = "ON";
+
+endpackage

data/lib/public_atom_module/synth_system_pkg.sv

@@ -0,0 +1,4 @@
+package SystemPkg;
+    parameter SIM = "OFF";
+
+endpackage

data/lib/tdl/Logic/logic_edge.rb

@@ -1,7 +1,7 @@
 
 
 class Logic     ## EDGE METHOD
-    def raising(cnt:1,clock:nil,reset: 1.b1 )
+    def raising(name: nil, cnt: 1,clock: nil,reset: 1.b1 )
 
         # if cnt==1 && clock == nil && reset==nil && @raising_record
         #     return @raising_record
@@ -26,11 +26,19 @@ class Logic     ## EDGE METHOD
                 # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str }
                 belong_to_module.Logic_draw << head_str
                 inst_edge(@clock,@reset)
-                if cnt>1
-                    inst_raise_edge_cnt(cnt-1)
-                    str = inst_cnt_edge_signal(cnt-1,:raise)
-                else
-                    str = "#{signal}_raising"
+                unless name 
+                    if cnt>1
+                        inst_raise_edge_cnt(cnt-1)
+                        str = inst_cnt_edge_signal(cnt-1,:raise)
+                    else
+                        str = "#{signal}_raising"
+                    
+                    end
+                else 
+                    if cnt>1
+                        inst_raise_edge_cnt(cnt-1)
+                    end
+                    str = name 
                 end
                 # @@logic_expression << lambda{ end_str }
                 # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str }

data/lib/tdl/Logic/logic_latency.rb

@@ -81,7 +81,7 @@ cross_clk_sync #(
         if wclk.nil? || rclk.nil?
             raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
         end
-        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{globle_random_name_flag()}",dsize:1)
+        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
         large_name_len(phase,len,wclk,wreset,rclk,rreset)
 body =
 "
@@ -89,7 +89,7 @@ broaden_and_cross_clk #(
     .PHASE     (#{align_signal(phase)}),  //POSITIVE NEGATIVE
     .LEN       (#{align_signal(len)}),
     .LAT       (#{align_signal(lat)})
-)#{new_l.signal}_inst_#{globle_random_name_flag()}(
+)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
 /* input    */  .rclk       (#{align_signal(rclk,q_mark=false)}),
 /* input    */  .rd_rst_n   (#{align_signal(rreset,q_mark=false)}),
 /* input    */  .wclk       (#{align_signal(wclk,q_mark=false)}),
@@ -125,7 +125,7 @@ module  CtrlLogic
 latency #(
     .LAT    (#{num}),
     .DSIZE  (1)
-)#{new_l.signal}_lat_#{globle_random_name_flag()}(
+)#{new_l.signal}_lat_#{belong_to_module._auto_name_incr_index_()}(
     #{clock},
     #{reset_str},
     #{self.to_s},
@@ -145,13 +145,13 @@ latency #(
 
         # new_l = Logic.new(name:"crock_clk",dsize:self.dsize)
         # new_l = self.logic(name:"crock_clk",dsize:self.dsize)
-        new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{globle_random_name_flag()}",dsize:dsize)
+        new_l = belong_to_module.Def().logic(name:name || "crock_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:dsize)
         str = %Q{
 //----->> #{self.to_s} cross clock <<------------------
 cross_clk_sync #(
 	.LAT   (2      ),
 	.DSIZE (#{dsize})
-)#{new_l.signal}_cross_clk_inst__#{globle_random_name_flag()}(
+)#{new_l.signal}_cross_clk_inst__#{belong_to_module._auto_name_incr_index_()}(
 /* input              */ .clk       (#{align_signal(clock)}),
 /* input              */ .rst_n     (#{align_signal(reset)}),
 /* input [DSIZE-1:0]  */ .d         (#{align_signal(self)}),
@@ -168,7 +168,7 @@ cross_clk_sync #(
         if wclk.nil? || rclk.nil?
             raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n")
         end
-        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{globle_random_name_flag()}",dsize:1)
+        new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{belong_to_module._auto_name_incr_index_()}",dsize:1)
         large_name_len(phase,len,wclk,wreset,rclk,rreset)
 body =
 "
@@ -176,7 +176,7 @@ broaden_and_cross_clk #(
 	.PHASE     (#{align_signal(phase)}),  //POSITIVE NEGATIVE
 	.LEN       (#{align_signal(len)}),
 	.LAT       (#{align_signal(lat)})
-)#{new_l.signal}_inst_#{globle_random_name_flag()}(
+)#{new_l.signal}_inst_#{belong_to_module._auto_name_incr_index_()}(
 /* input    */  .rclk       (#{align_signal(rclk,q_mark=false)}),
 /* input    */  .rd_rst_n   (#{align_signal(rreset,q_mark=false)}),
 /* input    */  .wclk       (#{align_signal(wclk,q_mark=false)}),

data/lib/tdl/auto_script/autogensdl.rb

@@ -2,13 +2,12 @@
 
 class AutoGenSdl
     attr_accessor :bad
-    def initialize(filename="",out_file_path=@@auto_path,info=true)
+    def initialize(filename="",out_file_path=@@auto_path,encoding='utf-8')
         @expand_path = File.expand_path(filename)
         sf = File.open(filename,"r")
-        fstr = sf.read.force_encoding("utf-8")
+        fstr = sf.read.force_encoding(encoding)
         sf.close
         @bad = true
-
         # return if exist_origin_sdl(filename,@expand_path)
         # fstr.gsub!(/\/\/\s*\(\*\s*show\s*=\s*"false"\s*\*\)/,"(* show = \"false\" *)")
         # SDL ignore `show`

data/lib/tdl/auto_script/import_hdl.rb

@@ -1,6 +1,6 @@
-
-def require_hdl(hdl_path)
-    basename = File.basename(hdl_path,".sv")
+$__contain_hdl__ = []
+def __require_hdl__(hdl_path,current_sdlm=nil,encoding='utf-8')
+    basename = File.basename(hdl_path,".*")
     unless SdlModule.exist_module? basename
         ## 检测是不是全路径, 或当前路径查得到
         if File.exist? hdl_path
@@ -12,15 +12,47 @@ def require_hdl(hdl_path)
                     raise TdlError.new("Cant find <#{hdl_path}> in tdl paths !!!")    
                 end
 
-                AutoGenSdl.new(rel,File.join(__dir__,"tmp")).auto_rb
+                AutoGenSdl.new(rel,File.join(__dir__,"tmp"),encoding=encoding).auto_rb
+
+                ## 如果是 在非 sdlmodule 内引用需要添加contain_hdl
+                # if !(current_sdlm.is_a?(SdlModule))
+                #     if TopModule.current
+                #         TopModule.current.contain_hdl(rel)
+                #     else
+                #         unless  $__contain_hdl__.include? rel
+                #             $__contain_hdl__ << rel
+                #         end
+                #     end
+                # end
+                if current_sdlm 
+                    current_sdlm.contain_hdl(rel)
+                else 
+                    unless  $__contain_hdl__.include? rel
+                        $__contain_hdl__ << rel
+                    end
+                end
+                
             else 
                 raise TdlError.new("path<#{hdl_path}> error!!!")
             end
         end
+        
         require_relative File.join(__dir__,"tmp","#{basename}_sdl.rb")
     end
 end
 
+def TopModule.contain_hdl(*hdl_paths)
+    hdl_paths.each do |hdl_path|
+        rel = find_first_hdl_path(hdl_path)
+        unless rel 
+            return nil 
+        end
+        unless  $__contain_hdl__.include? rel
+            $__contain_hdl__ << rel
+        end
+    end
+end
+
 unless File.exist? File.join(__dir__,'tmp')  
     Dir.mkdir File.join(__dir__,'tmp')
 end
@@ -28,8 +60,12 @@ end
 def find_first_hdl_path(basename)
     $__tdl_paths__.each do |e|
         if File.exist? File.join(e,basename)
-            return File.join(e,basename)
+            return File.expand_path(File.join(e,basename))
         end
     end
     return nil
 end
+
+def require_hdl(hdl_path,encoding='utf-8')
+    __require_hdl__(hdl_path,nil,encoding)
+end

data/lib/tdl/auto_script/import_sdl.rb

@@ -23,4 +23,46 @@ def require_sdl(sdl_path)
         end
         # require_relative File.join(__dir__,"tmp","#{basename}_sdl.rb")
     end
-end
+end
+
+## 添加 模糊引入 
+def require_shdl(*shdl_name)
+    shdl_name.each do |s|
+        unless s.is_a? Array
+            __require_shdl__(s)
+        else 
+            __require_shdl__(s[0],s[1])
+        end
+    end    
+end
+
+def __require_shdl__(shdl_name,encoding='utf-8')
+    
+    unless SdlModule.exist_module? shdl_name
+        sdl_path = "#{shdl_name}.rb"
+        rel = find_first_hdl_path(sdl_path)
+        ## 匹配 SDL
+        if rel 
+            require_relative rel
+            return 
+        end
+        ## 匹配 SV 
+        sv_path = "#{shdl_name}.sv"
+        v_path = "#{shdl_name}.v"
+        vv_path = "#{shdl_name}.V"
+
+        rel = find_first_hdl_path(sv_path) || find_first_hdl_path(v_path) || find_first_hdl_path(vv_path)
+        if rel 
+            AutoGenSdl.new(rel,File.join(__dir__,"tmp"),encoding=encoding).auto_rb
+
+            unless  $__contain_hdl__.include? rel
+                $__contain_hdl__ << rel
+            end
+
+            require_relative File.join(__dir__,"tmp","#{shdl_name}_sdl.rb")
+            return 
+        end
+
+        raise TdlError.new("Can find <#{shdl_name}> in tdl paths !!!")    
+    end
+end

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -68,7 +68,7 @@ class Axi4
                 e.band_params_from(self)
                 
                 ## e is a Vector 
-                if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
+                if e.dimension && e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
                     # require_hdl 'axi4_direct_B1.sv'
                     require_hdl 'axi4_direct_verc.sv'
 
@@ -189,8 +189,10 @@ class Axi4
                 @_long_slim_to_wide << new_master
             else
                 if !(e.dsize.eql? self.dsize)
+                    require_hdl 'axi4_long_to_axi4_wide_verb.sv'
+                    TopModule.contain_hdl 'axi4_direct_verb.sv'
                     # puts "#{e.dsize} == #{self.dsize} #{e.dsize != self.dsize} #{e.dsize.class}"
-                    new_master = self.copy(mode:e.mode,idsize:e.idsize)
+                    new_master = self.copy(name: "#{e.name}_renew_dir",mode:e.mode,idsize:e.idsize)
                     # new_master.axi4_data_convert(up_stream: e)
                     # @_long_slim_to_wide << Axi4.axi4_pipe(up_stream:new_master)
 
@@ -245,20 +247,13 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
-                # require_hdl 'axi4_direct_B1.sv'
-                # # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                # belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
-                #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                #     h.slaver_inf        lo
-                #     h.master_inf        "#{sub_name}[#{index}]".to_nq
-                # end
-
+                
                 require_hdl 'axi4_direct_verc.sv'
-                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                     h.param.MODE            mode_str    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
                     h.param.SLAVER_MODE     (wr_lg ? "ONLY_WRITE" : "ONLY_READ")    #    //
                     h.param.MASTER_MODE     "BOTH"    #    //
-                    h.slaver_inf        lo
+                    h.slaver_inf        (lo.respond_to?(:dimension) && (lo.dimension.nil? || lo.dimension[0]==1) && lo[0])  || lo
                     h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
@@ -268,14 +263,14 @@ class Axi4
                 require_hdl 'axi4_combin_wr_rd_batch.sv'
                 if wr_lg
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
+                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                         h.wr_slaver         lo
                         h.rd_slaver         los
                         h.master            "#{sub_name}[#{index}]".to_nq
                     end 
                 else
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:los,rd_slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|
+                    belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}_#{belong_to_module._auto_name_incr_index_}") do |h|
                         h.wr_slaver         los
                         h.rd_slaver         lo
                         h.master            "#{sub_name}[#{index}]".to_nq

data/lib/tdl/class_hdl/hdl_always_ff.rb

@@ -89,7 +89,7 @@ module ClassHDL
                     str.push op.instance(:always_ff).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff,belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end

data/lib/tdl/class_hdl/hdl_data.rb

@@ -1,7 +1,7 @@
 class Integer
 
     def method_missing(method,arg=nil)
-        if method.to_s =~ /^s?[h|d]\d+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f]+$/i
+        if method.to_s =~ /^s?[h|d][\d|_]+$/i || method.to_s =~ /^s?[b](0|1|_)+$/i || method.to_s =~ /^s?[h][\d]?[\d|a-f|_]+$/i
             if self.nonzero?
                 return "#{self.to_s}'#{method}".to_nq
             else 

data/lib/tdl/class_hdl/hdl_generate.rb

@@ -19,7 +19,7 @@ module ClassHDL
         attr_accessor :block_index
         def initialize(belong_to_module)
             @belong_to_module = belong_to_module
-            super("genblk#{globle_random_name_flag()}")
+            super("genblk#{belong_to_module._auto_name_incr_index_}")
             unless @belong_to_module
                 raise TdlError.new("GenerateBlock must have belong_to_module")
             end
@@ -70,7 +70,7 @@ module ClassHDL
         def ELSIF(cond,&block)
             if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
                 if cond.respond_to?(:instance)
-                    head_str = "else if(#{cond.instance(:cond)})begin\n"
+                    head_str = "else if(#{cond.instance(:cond,@belong_to_module)})begin\n"
                 else 
                     head_str = "else if(#{cond})begin\n"
                 end