axi_tdl 0.1.3 → 0.1.19

data/lib/axi/AXI4/packet_partition/data_inf_partition.rb

@@ -31,8 +31,8 @@ TdlBuild.data_inf_partition(__dir__) do
     logic   - 'tail_len'
     logic   - 'one_long_stream'
     logic   - 'fifo_wr'
-    debugLogic   - 'fifo_full'
-    debugLogic   - 'fifo_empty'
+    logic   - 'fifo_full'
+    logic   - 'fifo_empty'
 
     always_comb do 
         CASE ps.C do 
@@ -267,8 +267,12 @@ TdlBuild.data_inf_partition(__dir__) do
     end
 
     ### Track 
-    debugLogic[10]  - 'st5_cnt'
-    debugLogic      - 'track_st5'
+    # debugLogic[10]  - 'st5_cnt'
+    # debugLogic      - 'track_st5'
+
+    logic[10]  - 'st5_cnt'
+    logic      - 'track_st5'
+
     always_ff(posedge.clock,negedge.rst_n) do 
         IF ~rst_n do
             st5_cnt     <= 0.A 

data/lib/axi/AXI4/packet_partition/data_inf_partition.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: XXXX.XX.XX
+creaded:
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -29,14 +29,14 @@ logic  rst_n;
 logic tail_len;
 logic one_long_stream;
 logic fifo_wr;
+logic fifo_full;
+logic fifo_empty;
 logic [IDSIZE+4-1:0]  curr_id ;
 logic [LSIZE-1:0]  curr_length ;
 logic [(data_in.DSIZE - IDSIZE)-LSIZE-1:0]  curr_addr ;
 logic [LSIZE-1:0]  wr_length ;
-(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
-(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
-(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic [9:0]  st5_cnt ;
-(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic track_st5;
+logic [10-1:0]  st5_cnt ;
+logic track_st5;
 
 //==========================================================================
 //-------- instance --------------------------------------------------------

data/lib/axi/AXI4/vcs_axi4_comptable.sv

@@ -60,7 +60,7 @@ if(TO=="mirror")begin
         assign to.axi_rvalid   = origin.axi_rvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end
@@ -85,7 +85,7 @@ end else if(TO=="mirror_rd")begin
         assign  to.axi_rvalid   = origin.axi_rvalid ;
     end else begin
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end 
     end
@@ -131,7 +131,7 @@ end else if(ORIGIN=="slaver")begin
         assign    origin.axi_rvalid   = to.axi_rvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -173,7 +173,7 @@ end  else if(ORIGIN == "master_rd")begin
         assign     origin.axi_rvalid  = to.axi_rvalid  ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -239,7 +239,7 @@ end else if(ORIGIN=="master")begin
         assign   origin.axi_rvalid  = to.axi_rvalid   ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end
@@ -261,7 +261,7 @@ end else if(ORIGIN == "master_wr_aux_no_resp")begin
         assign   origin.axi_wready   = to.axi_wready ;
     end else begin
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -285,7 +285,7 @@ end else if(ORIGIN == "master_rd_aux")begin
         assign   origin.axi_rvalid  = to.axi_rvalid   ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
@@ -313,13 +313,39 @@ end else if(ORIGIN=="master_wr")begin
         assign    origin.axi_bvalid   = to.axi_bvalid ;
     end else begin 
         initial begin
-            $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
+            $stop;
+        end
+    end 
+end else if(ORIGIN=="slaver_rd")begin 
+    if(TO=="slaver")begin 
+        assign    to.axi_arid     = origin.axi_arid   ;
+        assign    to.axi_araddr   = origin.axi_araddr ;
+        assign    to.axi_arlen    = origin.axi_arlen  ;
+        assign    to.axi_arsize   = origin.axi_arsize ;
+        assign    to.axi_arburst  = origin.axi_arburst;
+        assign    to.axi_arlock   = origin.axi_arlock ;
+        assign    to.axi_arcache  = origin.axi_arcache;
+        assign    to.axi_arprot   = origin.axi_arprot ;
+        assign    to.axi_arqos    = origin.axi_arqos  ;
+        assign    to.axi_arvalid  = origin.axi_arvalid;
+        assign    origin.axi_arready    = to.axi_arready;
+
+        assign    to.axi_rready             = origin.axi_rready ;
+        assign    origin.axi_rid            = to.axi_rid    ;
+        assign    origin.axi_rresp          = to.axi_rresp  ;
+        assign    origin.axi_rlast          = to.axi_rlast  ;
+        assign    origin.axi_rdata          = to.axi_rdata  ;
+        assign    origin.axi_rvalid         = to.axi_rvalid ;
+    end else begin 
+        initial begin
+            $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
             $stop;
         end
     end 
 end else begin 
     initial begin
-        $error("vcs_axi4_comptable ORIGIN[%s] => [%s] ERROR",ORIGIN,TO);
+        $error("vcs_axi4_comptable ORIGIN[%0s] => [%0s] ERROR",ORIGIN,TO);
         $stop;
     end
 end

data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb

@@ -95,7 +95,7 @@ new_m.instance_exec do
         len_s   <= split_out.axis_tcnt
         id_add_len_in.axis_tvalid           <= ~independent_clock_fifo_inst[:empty]
         id_add_len_in.axis_tdata            <= independent_clock_fifo_inst[:rdata]
-        id_add_len_in.axis_tlast            <= "1'b1"
+        id_add_len_in.axis_tlast            <= 1.b1
         independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
     end
 

data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv

@@ -53,11 +53,11 @@ logic fifo_rd_en;
 logic fifo_empty;
 logic fifo_full;
 logic stream_en;
-axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1342 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
-axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R0000 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_length_split_with_addr #(
@@ -93,13 +93,13 @@ independent_clock_fifo #(
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
 /* output                        */.stream_en     (stream_en           ),
 /* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1342 )
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R0000 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R700_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R1342 ),
+)vcs_axi4_comptable_axi_wr_aux_R0001_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R0000 ),
 /* output */.to     (axi_wr              )
 );
 axis_valve_with_pipe #(

data/lib/axi/AXI4/width_convert/odd_width_convert.sv

@@ -31,7 +31,7 @@ assign wr_ready = rd_ready;
 initial begin
     assert(ISIZE < OSIZE)
     else begin
-        $error("ISIZE MUST BE MORE SMALLER THAN OSIZE\n");
+        $error("ISIZE<%d> MUST BE MORE SMALLER THAN OSIZE<%d>\n",ISIZE,OSIZE);
         $stop;
     end
 end

data/lib/axi/AXI_stream/axi_stream_split_channel.rb

@@ -19,8 +19,11 @@ TdlBuild.axi_stream_split_channel(__dir__) do
             addr        <= 1.b0 
             new_last    <= 1.b0
         end
-        ELSE do 
-            IF origin_inf.vld_rdy do 
+        ELSE do
+            IF origin_inf.vld_rdy_last do
+                new_last    <= 1.b0
+            end
+            ELSIF origin_inf.vld_rdy do 
                 new_last    <= (origin_inf.axis_tcnt == (split_len - 2))
             end
             ELSE do 

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 12:04:15 +0800
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -23,8 +23,8 @@ logic  clock;
 logic  rst_n;
 logic addr;
 logic new_last;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axi_stream_interconnect_S2M #(
@@ -55,22 +55,22 @@ axis_direct  axis_direct_end_inf_inst0 (
 );
 //-------- CLOCKs Total 3 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_0,cc_same_0;
-integer cc_afreq_0,cc_bfreq_0;
-ClockSameDomain CheckPClock_inst_0(
-/*  input         */      .aclk     (origin_inf.aclk),
-/*  input         */      .bclk     (first_inf.aclk),
-/*  output logic  */      .done     (cc_done_0),
-/*  output logic  */      .same     (cc_same_0),
-/*  output integer */     .aFreqK   (cc_afreq_0),
-/*  output integer */     .bFreqK   (cc_bfreq_0)
+logic cc_done_8,cc_same_8;
+integer cc_afreq_8,cc_bfreq_8;
+ClockSameDomain CheckPClock_inst_8(
+/*  input         */      .aclk     (origin_inf.aclk        ),
+/*  input         */      .bclk     (first_inf.aclk         ),
+/*  output logic  */      .done     (cc_done_8),
+/*  output logic  */      .same     (cc_same_8),
+/*  output integer */     .aFreqK   (cc_afreq_8),
+/*  output integer */     .bFreqK   (cc_bfreq_8)
 );
 
 initial begin
-    wait(cc_done_0);
-    assert(cc_same_0)
+    wait(cc_done_8);
+    assert(cc_same_8)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_0, 1000000.0/cc_bfreq_0);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -80,22 +80,22 @@ end
 //---<< CheckClock >>----------------
 
 //--->> CheckClock <<----------------
-logic cc_done_1,cc_same_1;
-integer cc_afreq_1,cc_bfreq_1;
-ClockSameDomain CheckPClock_inst_1(
-/*  input         */      .aclk     (origin_inf.aclk),
-/*  input         */      .bclk     (end_inf.aclk),
-/*  output logic  */      .done     (cc_done_1),
-/*  output logic  */      .same     (cc_same_1),
-/*  output integer */     .aFreqK   (cc_afreq_1),
-/*  output integer */     .bFreqK   (cc_bfreq_1)
+logic cc_done_9,cc_same_9;
+integer cc_afreq_9,cc_bfreq_9;
+ClockSameDomain CheckPClock_inst_9(
+/*  input         */      .aclk     (origin_inf.aclk        ),
+/*  input         */      .bclk     (end_inf.aclk           ),
+/*  output logic  */      .done     (cc_done_9),
+/*  output logic  */      .same     (cc_same_9),
+/*  output integer */     .aFreqK   (cc_afreq_9),
+/*  output integer */     .bFreqK   (cc_bfreq_9)
 );
 
 initial begin
-    wait(cc_done_1);
-    assert(cc_same_1)
+    wait(cc_done_9);
+    assert(cc_same_9)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_1, 1000000.0/cc_bfreq_1);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -114,8 +114,11 @@ always_ff@(posedge clock,negedge rst_n) begin
         new_last <= 1'b0;
     end
     else begin
-        if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
-            new_last <= origin_inf.axis_tcnt==(split_len-2);
+        if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
+            new_last <= 1'b0;
+        end
+        else if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
+            new_last <= (origin_inf.axis_tcnt==(split_len-2));
         end
         else begin
             new_last <= new_last;

data/lib/axi/AXI_stream/axis_head_cut_verc.sv

@@ -4,7 +4,7 @@ ___________    Cook Darwin   __________
 _______________________________________
 descript:
 author : Cook.Darwin
-Version: VERA.0.0
+Version: VERC.0.0
 creaded: XXXX.XX.XX
 madified:
 ***********************************************/
@@ -39,13 +39,13 @@ logic [4-1:0]  int_cut_len ;
 logic [4-1:0]  shift_sel_pre ;
 logic fifo_wr_en_lat;
 logic [4-1:0]  shift_sel ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR774 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR0000 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_pipe_sync_seam #(
@@ -122,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
 axis_head_cut_verb last_cut_inst(
 /* input                 */.length   (16'd1               ),
 /* axi_stream_inf.slaver */.axis_in  (origin_inf_ss_E0_CH ),
-/* axi_stream_inf.master */.axis_out (out_inf_branchR774  )
+/* axi_stream_inf.master */.axis_out (out_inf_branchR0000 )
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
@@ -136,7 +136,7 @@ axis_direct  axis_direct_out_inf_inst0 (
 );
 
 axis_direct  axis_direct_out_inf_inst1 (
-/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR774),
+/*  axi_stream_inf.slaver*/ .slaver (out_inf_branchR0000),
 /*  axi_stream_inf.master*/ .master (sub_out_inf[1])
 );
 

data/lib/axi/AXI_stream/axis_insert_copy.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: XXXX.XX.XX
+created: 2021-04-16 17:01:06 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -22,7 +22,7 @@ module axis_insert_copy (
 logic  clock;
 logic  rst_n;
 logic insert_tri;
-axi_stream_inf #(.DSIZE(in_inf.DSIZE),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_connect_pipe axis_connect_pipe_inst(

data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: XXXX.XX.XX
+created: 2021-04-16 17:01:05 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -23,8 +23,8 @@ module axis_pipe_sync_seam #(
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
-data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(1.0)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
+data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(data_in_inf.FreqM)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 data_c_pipe_sync_seam #(

data/lib/axi/AXI_stream/axis_rom_contect_sim.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: XXXX.XX.XX
+created: 2021-04-16 17:01:02 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -25,11 +25,11 @@ module axis_rom_contect_sim #(
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.FreqM(a_axis_zip.FreqM),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.FreqM(b_axis_zip.FreqM),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
 cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
-axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.FreqM(a_rom_contect_inf.FreqM),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.FreqM(b_rom_contect_inf.FreqM),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_uncompress_A1 #(

data/lib/axi/AXI_stream/axis_sim_master_model.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-04-03 12:04:15 +0800
+created: 2021-04-16 17:01:07 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -24,7 +24,7 @@ module axis_sim_master_model #(
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
+data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1),.FreqM(1.0)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 data_c_sim_master_model #(

data/lib/axi/AXI_stream/axis_split_channel_verb.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-creaded: XXXX.XX.XX
+created: 2021-04-16 17:01:06 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -23,7 +23,7 @@ logic  clock;
 logic  rst_n;
 logic [16-1:0]  insert_seed ;
 logic [16-1:0]  next_split_len ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 axis_insert_copy axis_insert_copy_inst(

data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv

@@ -0,0 +1,50 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+(* axi_stream = "true" *)
+module axis_width_convert_verb #(
+    parameter IDSIZE = 8,
+    parameter ODSIZE = 16
+)(
+    axi_stream_inf.slaver   in_axis,
+    axi_stream_inf.master   out_axis
+);
+
+generate
+if(IDSIZE == ODSIZE)
+    axis_direct_A1 #(
+        .IDSIZE     (in_axis.DSIZE),
+        .ODSIZE     (out_axis.DSIZE)
+    )axis_direct_A1_inst(
+    /*  axi_stream_inf.slaver */  .slaver       (in_axis    ),
+    /*  axi_stream_inf.master */  .master       (out_axis   )
+    );
+else
+    width_convert_verb #(
+        .ISIZE      (IDSIZE ),
+        .OSIZE      (ODSIZE )
+    )width_convert_verb_inst(
+    /*  input                    */     .clock          (in_axis.aclk           ),
+    /*  input                    */     .rst_n          (in_axis.aresetn        ),
+    /*  input [ISIZE-1:0]        */     .wr_data        (in_axis.axis_tdata     ),
+    /*  input                    */     .wr_vld         (in_axis.axis_tvalid    ),
+    /*  output logic             */     .wr_ready       (in_axis.axis_tready    ),
+    /*  input                    */     .wr_last        (in_axis.axis_tlast     ),
+    /*  input                    */     .wr_align_last  (1'b0),      //can be leave 1'b0
+    /*  output logic[OSIZE-1:0]  */     .rd_data        (out_axis.axis_tdata    ),
+    /*  output logic             */     .rd_vld         (out_axis.axis_tvalid   ),
+    /*  input                    */     .rd_ready       (out_axis.axis_tready   ),
+    /*  output                   */     .rd_last        (out_axis.axis_tlast    )
+    );
+    
+endgenerate
+
+endmodule

data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv

@@ -21,6 +21,8 @@ module axi_stream_packet_long_fifo #(
     axi_stream_inf.master      axis_out
 );
 
+assign axis_out.axis_tuser  = '0;
+
 //--->> NATIVE FIFO IP <<------------------------------
 // (* dont_touch = "true" *)
 logic   data_fifo_full;

data/lib/axi/AXI_stream/parse_big_field_table_verb.sv

@@ -26,6 +26,8 @@ module parse_big_field_table_verb #(
     axi_stream_inf.mirror                   cm_mirror
 );
 
+localparam  VSIZE = $clog2(FIELD_LEN);
+
 import SystemPkg::*;
 
 initial begin 
@@ -78,13 +80,13 @@ always_ff@(posedge clock,negedge rst_n)begin
     else begin 
         if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
                 region_valid    <= 1'b1;
-        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
                 region_valid    <= 1'b0;
         else    region_valid    <= region_valid;
     end
 end
 
-localparam  VSIZE = $clog2(FIELD_LEN);
+
 logic[DSIZE-1:0]    value_array [0:FIELD_LEN-1];
 
 always_ff@(posedge clock,negedge rst_n)begin 
@@ -107,7 +109,7 @@ always_ff@(posedge clock,negedge rst_n)begin
             if(out_valid)
                     out_valid    <= 1'b0;
             else    out_valid    <= 1'b1;
-        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
+        else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
                 out_valid    <= 1'b1;
         else if(region_valid)
                 out_valid   <= 1'b0;

data/lib/axi/common/test_write_mem.sv

@@ -15,7 +15,7 @@ initial begin
     BRAM[0][2][3] = 14;
     BRAM[0][2][4] = 15;
 
-    $writememh("/home/myw357/work/FPGA/acce_20201211/git_repo/wmy/axi/common/mem_format.coe",BRAM);
+    $writememh("./mem_format.coe",BRAM);
 
 end
 

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -23,8 +23,8 @@ module data_c_pipe_sync_seam #(
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
-data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
+data_inf_c #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
+data_inf_c #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
 
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
 endgenerate
 //-------- CLOCKs Total 2 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_9,cc_same_9;
-integer cc_afreq_9,cc_bfreq_9;
-ClockSameDomain CheckPClock_inst_9(
+logic cc_done_10,cc_same_10;
+integer cc_afreq_10,cc_bfreq_10;
+ClockSameDomain CheckPClock_inst_10(
 /*  input         */      .aclk     (in_inf.clock           ),
 /*  input         */      .bclk     (out_inf.clock          ),
-/*  output logic  */      .done     (cc_done_9),
-/*  output logic  */      .same     (cc_same_9),
-/*  output integer */     .aFreqK   (cc_afreq_9),
-/*  output integer */     .bFreqK   (cc_bfreq_9)
+/*  output logic  */      .done     (cc_done_10),
+/*  output logic  */      .same     (cc_same_10),
+/*  output integer */     .aFreqK   (cc_afreq_10),
+/*  output integer */     .bFreqK   (cc_bfreq_10)
 );
 
 initial begin
-    wait(cc_done_9);
-    assert(cc_same_9)
+    wait(cc_done_10);
+    assert(cc_same_10)
     else begin
-        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
         repeat(10)begin 
             @(posedge in_inf.clock);
         end

data/lib/axi/platform_ip/long_fifo_verb.sv

@@ -26,7 +26,7 @@ module long_fifo_verb #(
     output              empty
 );
 
-import GlobalPkg::FAMIRY;
+import SystemPkg::FAMIRY;
 
 localparam  NUM = DSIZE/4 + (DSIZE%4 != 0);