axi_tdl 0.1.3 → 0.1.19
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- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +3 -2
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +11 -11
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +5 -5
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +32 -29
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +10 -10
- data/lib/axi/AXI_stream/axis_insert_copy.sv +2 -2
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +3 -3
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +5 -5
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +2 -2
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +2 -2
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +12 -12
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +6 -6
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/axi_tdl.rb +31 -1
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +14 -6
- data/lib/tdl/Logic/logic_latency.rb +7 -7
- data/lib/tdl/auto_script/autogensdl.rb +2 -3
- data/lib/tdl/auto_script/import_hdl.rb +41 -5
- data/lib/tdl/auto_script/import_sdl.rb +43 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
- data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
- data/lib/tdl/class_hdl/hdl_data.rb +1 -1
- data/lib/tdl/class_hdl/hdl_generate.rb +2 -2
- data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +4 -6
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +6 -6
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +6 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -3
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +2 -2
- data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
- data/lib/tdl/exlib/axis_verify.rb +2 -2
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +45 -39
- data/lib/tdl/exlib/logic_verify.rb +1 -1
- data/lib/tdl/rebuild_ele/axi4.rb +6 -2
- data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
- data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
- data/lib/tdl/rebuild_ele/ele_base.rb +7 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +73 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb +4 -1
- data/lib/tdl/sdlmodule/top_module.rb +4 -0
- data/lib/tdl/tdl.rb +1 -11
- metadata +12 -3
metadata
CHANGED
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@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: axi_tdl
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3
3
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version: !ruby/object:Gem::Version
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4
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-
version: 0.1.
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4
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+
version: 0.1.19
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5
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platform: ruby
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6
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authors:
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7
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- Cook.Darwin
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8
8
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autorequire:
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9
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bindir: exe
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cert_chain: []
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-
date: 2021-
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11
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+
date: 2021-09-24 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rake
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@@ -91,9 +91,12 @@ files:
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91
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- lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv
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- lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv
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- lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv
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94
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+
- lib/axi/AXI4/axi4_ram_cache.rb
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+
- lib/axi/AXI4/axi4_ram_cache.sv
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- lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv
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- lib/axi/AXI4/axi4_rd_auxiliary_gen.sv
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- lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv
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+
- lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv
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97
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- lib/axi/AXI4/axi4_rd_burst_track.sv
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- lib/axi/AXI4/axi4_wr_aux_bind_data.sv
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- lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv
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@@ -120,6 +123,8 @@ files:
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- lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv
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- lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv
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- lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak
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126
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+
- lib/axi/AXI4/long_axis_to_axi4_wr.rb
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+
- lib/axi/AXI4/long_axis_to_axi4_wr.sv
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- lib/axi/AXI4/odata_pool_axi4.sv
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- lib/axi/AXI4/odata_pool_axi4_A1.sv
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- lib/axi/AXI4/odata_pool_axi4_A2.sv
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@@ -286,6 +291,7 @@ files:
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- lib/axi/AXI_stream/data_width/axis_width_combin.sv
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- lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv
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- lib/axi/AXI_stream/data_width/axis_width_convert.sv
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+
- lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv
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- lib/axi/AXI_stream/data_width/axis_width_destruct.sv
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- lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv
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- lib/axi/AXI_stream/ex_status/axis_ex_status.sv
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@@ -575,8 +581,11 @@ files:
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- lib/public_atom_module/pipe_reg.v
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- lib/public_atom_module/pipe_reg_2write_ports.v
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577
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- lib/public_atom_module/sim/clock_rst_verb.sv
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+
- lib/public_atom_module/sim/clock_rst_verc.sv
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578
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- lib/public_atom_module/sim/latency_long_tb.sv
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- lib/public_atom_module/sim/latency_long_tb.sv.bak
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587
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+
- lib/public_atom_module/sim_system_pkg.sv
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+
- lib/public_atom_module/synth_system_pkg.sv
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- lib/spec/spec_helper.rb
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- lib/tdl/LICENSE
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- lib/tdl/Logic/Logic.tar.gz
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@@ -1327,7 +1336,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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1330
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-
rubygems_version: 3.0.3
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rubygems_version: 3.0.3.1
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signing_key:
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1332
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specification_version: 4
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summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言
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