axi_tdl 0.1.3 → 0.1.19
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- checksums.yaml +4 -4
- data/lib/axi/AXI4/axi4_direct_verc.sv +6 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +3 -2
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_ram_cache.rb +23 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +39 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +112 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +11 -11
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +113 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +125 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +12 -4
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +5 -5
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +35 -9
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +1 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +1 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +5 -2
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +32 -29
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +10 -10
- data/lib/axi/AXI_stream/axis_insert_copy.sv +2 -2
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +3 -3
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +5 -5
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +2 -2
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +2 -2
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +12 -12
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +6 -6
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/axi_tdl.rb +31 -1
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +14 -6
- data/lib/tdl/Logic/logic_latency.rb +7 -7
- data/lib/tdl/auto_script/autogensdl.rb +2 -3
- data/lib/tdl/auto_script/import_hdl.rb +41 -5
- data/lib/tdl/auto_script/import_sdl.rb +43 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +9 -14
- data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
- data/lib/tdl/class_hdl/hdl_data.rb +1 -1
- data/lib/tdl/class_hdl/hdl_generate.rb +2 -2
- data/lib/tdl/examples/11_test_unit/dve.tcl +153 -6
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +5 -4
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +7 -33
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +33 -7
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +4 -6
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +6 -6
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +6 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -3
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +2 -2
- data/lib/tdl/exlib/axis_eth_ex.rb +1 -1
- data/lib/tdl/exlib/axis_verify.rb +2 -2
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +45 -39
- data/lib/tdl/exlib/logic_verify.rb +1 -1
- data/lib/tdl/rebuild_ele/axi4.rb +6 -2
- data/lib/tdl/rebuild_ele/axi_stream.rb +3 -3
- data/lib/tdl/rebuild_ele/data_inf_c.rb +2 -2
- data/lib/tdl/rebuild_ele/ele_base.rb +7 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +73 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +3 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb +4 -1
- data/lib/tdl/sdlmodule/top_module.rb +4 -0
- data/lib/tdl/tdl.rb +1 -11
- metadata +12 -3
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@@ -12,8 +12,128 @@ gui_set_time_units 1ps
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## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
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## ==== [add_signal] ===== ##
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## -------------- sub_md0_logic -------------------------
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set _wave_session_group_sub_md0_logic sub_md0_logic
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# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt} }
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## ============== sub_md0_logic =========================
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## -------------- sub_md0_interface -------------------------
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set _wave_session_group_sub_md0_interface sub_md0_interface
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# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
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set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.axis_in} }
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## ============== sub_md0_interface =========================
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## -------------- sub_md0_default -------------------------
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set _wave_session_group_sub_md0_default sub_md0_default
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# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
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set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
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## ============== sub_md0_default =========================
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## -------------- sub_md0_default.inter_tf -------------------------
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## set _wave_session_group_sub_md0_default_inter_tf Group1
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## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
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set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
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append _wave_session_group_sub_md0_default_inter_tf inter_tf
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set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md0_inst.inter_tf} }
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## ============== sub_md0_default.inter_tf =========================
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## -------------- sub_md1_default -------------------------
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set _wave_session_group_sub_md1_default sub_md1_default
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# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
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set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable} }
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## ============== sub_md1_default =========================
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## -------------- sub_md1_inner -------------------------
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set _wave_session_group_sub_md1_inner sub_md1_inner
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# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
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if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
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set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
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}
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set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
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## ============== sub_md1_inner =========================
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## -------------- sub_md1_inner.inter_tf -------------------------
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## set _wave_session_group_sub_md1_inner_inter_tf Group1
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## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
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set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
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append _wave_session_group_sub_md1_inner_inter_tf inter_tf
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set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit_sim.rtl_top.sub_md1_inst.inter_tf} }
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## ============== sub_md1_inner.inter_tf =========================
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## -------------- exp_test_unit_sim_default -------------------------
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set _wave_session_group_exp_test_unit_sim_default exp_test_unit_sim_default
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# set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name -seed exp_test_unit_sim_default]
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if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_sim_default"]} {
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set _wave_session_group_exp_test_unit_sim_default [gui_sg_generate_new_name]
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}
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set Group2_exp_test_unit_sim_default "$_wave_session_group_exp_test_unit_sim_default"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default" { }
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## ============== exp_test_unit_sim_default =========================
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## -------------- exp_test_unit_sim_default.axis_data_inf -------------------------
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf Group1
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## set _wave_session_group_exp_test_unit_sim_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_sim_default ]
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set _wave_session_group_exp_test_unit_sim_default_axis_data_inf $_wave_session_group_exp_test_unit_sim_default|
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append _wave_session_group_exp_test_unit_sim_default_axis_data_inf axis_data_inf
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set exp_test_unit_sim_default|axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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# set Group2_exp_test_unit_sim_default_axis_data_inf "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf"
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## 添加信号到 group
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gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_sim_default_axis_data_inf" { {Sim:tb_exp_test_unit_sim.rtl_top.axis_data_inf} }
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## ============== exp_test_unit_sim_default.axis_data_inf =========================
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## 创建波形窗口
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if {![info exists useOldWindow]} {
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@@ -42,9 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
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## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
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## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
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## === [add_signal_wave] === ##
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## -------------- Group2_sub_md0_logic -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
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## ============== Group2_sub_md0_logic =========================
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## -------------- Group2_sub_md0_interface -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
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## ============== Group2_sub_md0_interface =========================
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## -------------- Group2_sub_md0_default -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
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## ============== Group2_sub_md0_default =========================
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## -------------- sub_md0_default|inter_tf -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
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## ============== sub_md0_default|inter_tf =========================
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## -------------- Group2_sub_md1_default -------------------------
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gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
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## ============== Group2_sub_md1_default =========================
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## -------------- Group2_sub_md1_inner -------------------------
|
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+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
|
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|
+
## ============== Group2_sub_md1_inner =========================
|
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183
|
+
## -------------- sub_md1_inner|inter_tf -------------------------
|
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|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
|
|
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|
+
## ============== sub_md1_inner|inter_tf =========================
|
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186
|
+
## -------------- Group2_exp_test_unit_sim_default -------------------------
|
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|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_sim_default}]
|
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|
+
## ============== Group2_exp_test_unit_sim_default =========================
|
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|
+
## -------------- exp_test_unit_sim_default|axis_data_inf -------------------------
|
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|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_sim_default|axis_data_inf}]
|
|
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|
+
## ============== exp_test_unit_sim_default|axis_data_inf =========================
|
|
48
192
|
|
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49
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|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
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194
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@@ -61,9 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
|
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|
gui_list_set_filter -id ${Wave.3} -text {*}
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##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
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## === [add_bar] === ##
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-
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-
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-
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+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
|
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+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
|
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|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
|
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|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
|
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|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
|
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|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_sim_default} -position in
|
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|
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|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
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gui_view_scroll -id ${Wave.3} -vertical -set 35
|
|
@@ -31,10 +31,11 @@ TopModule.exp_test_unit(__dir__) do
|
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31
|
# add_to_dve_wave(TdlTestPoint.sub_md1.tp_inter_tf)
|
|
32
32
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|
33
33
|
test_unit_init do
|
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|
-
sub_md1.enable
|
|
35
|
-
|
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36
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-
|
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37
|
-
|
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34
|
+
sub_md0.cnt <= sub_md1.enable + 1
|
|
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|
+
# sub_md1.enable <= 1.b1
|
|
36
|
+
# initial_exec("#(1us)")
|
|
37
|
+
# sub_md1.enable <= 1.b0
|
|
38
|
+
# initial_exec("#(500us)")
|
|
38
39
|
end
|
|
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40
|
|
|
40
41
|
end
|
|
@@ -1,35 +1,9 @@
|
|
|
1
|
-
/**********************************************
|
|
2
|
-
_______________________________________
|
|
3
|
-
___________ Cook Darwin __________
|
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-
_______________________________________
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-
descript:
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|
6
|
-
author : Cook.Darwin
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|
7
|
-
Version: VERA.0.0
|
|
8
|
-
created: 2021-04-03 13:14:45 +0800
|
|
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-
madified:
|
|
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-
***********************************************/
|
|
11
|
-
`timescale 1ns/1ps
|
|
12
|
-
|
|
13
|
-
module exp_test_unit (
|
|
14
|
-
input clock,
|
|
15
|
-
input rst_n
|
|
16
|
-
);
|
|
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|
-
|
|
18
|
-
//==========================================================================
|
|
19
|
-
//-------- define ----------------------------------------------------------
|
|
20
|
-
logic enable;
|
|
21
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
-
//==========================================================================
|
|
23
|
-
//-------- instance --------------------------------------------------------
|
|
24
|
-
sub_md1 sub_md1_inst(
|
|
25
|
-
/* axi_stream_inf.master */.axis_out (axis_data_inf ),
|
|
26
|
-
/* output */.enable (enable )
|
|
27
|
-
);
|
|
28
|
-
sub_md0 sub_md0_inst(
|
|
29
|
-
/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
|
|
30
|
-
/* input */.enable (enable )
|
|
31
|
-
);
|
|
32
|
-
//==========================================================================
|
|
33
|
-
//-------- expression ------------------------------------------------------
|
|
34
1
|
|
|
2
|
+
`timescale 1ns/1ps
|
|
3
|
+
module exp_test_unit();
|
|
4
|
+
initial begin
|
|
5
|
+
#(1us);
|
|
6
|
+
$warning("Check TopModule.sim,please!!!");
|
|
7
|
+
$stop;
|
|
8
|
+
end
|
|
35
9
|
endmodule
|
|
@@ -1,9 +1,35 @@
|
|
|
1
|
-
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-09-24 23:32:18 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
2
11
|
`timescale 1ns/1ps
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
12
|
+
|
|
13
|
+
module exp_test_unit_sim (
|
|
14
|
+
input clock,
|
|
15
|
+
input rst_n
|
|
16
|
+
);
|
|
17
|
+
|
|
18
|
+
//==========================================================================
|
|
19
|
+
//-------- define ----------------------------------------------------------
|
|
20
|
+
logic enable;
|
|
21
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
+
//==========================================================================
|
|
23
|
+
//-------- instance --------------------------------------------------------
|
|
24
|
+
sub_md1 sub_md1_inst(
|
|
25
|
+
/* axi_stream_inf.master */.axis_out (axis_data_inf ),
|
|
26
|
+
/* output */.enable (enable )
|
|
27
|
+
);
|
|
28
|
+
sub_md0 sub_md0_inst(
|
|
29
|
+
/* axi_stream_inf.slaver */.axis_in (axis_data_inf ),
|
|
30
|
+
/* input */.enable (enable )
|
|
31
|
+
);
|
|
32
|
+
//==========================================================================
|
|
33
|
+
//-------- expression ------------------------------------------------------
|
|
34
|
+
|
|
9
35
|
endmodule
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -20,7 +20,7 @@ module sub_md0 (
|
|
|
20
20
|
logic clock;
|
|
21
21
|
logic rst_n;
|
|
22
22
|
logic [10-1:0] cnt ;
|
|
23
|
-
data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
|
|
23
|
+
data_inf_c #(.DSIZE(8),.FreqM(axis_in.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
|
|
24
24
|
//==========================================================================
|
|
25
25
|
//-------- instance --------------------------------------------------------
|
|
26
26
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -20,7 +20,7 @@ module sub_md1 (
|
|
|
20
20
|
logic clock;
|
|
21
21
|
logic rst_n;
|
|
22
22
|
logic [10-1:0] cnt ;
|
|
23
|
-
data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
|
|
23
|
+
data_inf_c #(.DSIZE(8),.FreqM(axis_out.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
|
|
24
24
|
//==========================================================================
|
|
25
25
|
//-------- instance --------------------------------------------------------
|
|
26
26
|
|
|
@@ -5,11 +5,10 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04-03
|
|
8
|
+
created: 2021-04-03 14:05:10 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
12
|
-
`timescale 1ns/1ps
|
|
13
12
|
|
|
14
13
|
module tb_exp_test_unit_sim();
|
|
15
14
|
//==========================================================================
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-
|
|
8
|
+
created: 2021-09-24 23:32:18 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -27,11 +27,9 @@ module tu0 (
|
|
|
27
27
|
initial begin
|
|
28
28
|
to_down_pass = 1'b0;
|
|
29
29
|
wait(from_up_pass);
|
|
30
|
-
$root.
|
|
31
|
-
$
|
|
32
|
-
|
|
33
|
-
$root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
|
|
34
|
-
#(500us);
|
|
30
|
+
$root.tb_exp_test_unit_sim.test_unit_region = "tu0";
|
|
31
|
+
$display("--------------- Current test_unit <%0s> --------------------", "tu0");
|
|
32
|
+
$root.tb_exp_test_unit_sim.rtl_top.sub_md0_inst.cnt = ($root.tb_exp_test_unit_sim.rtl_top.sub_md1_inst.enable+1);
|
|
35
33
|
to_down_pass = 1'b1;
|
|
36
34
|
end
|
|
37
35
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -15,8 +15,8 @@ module always_comb_test ();
|
|
|
15
15
|
//-------- define ----------------------------------------------------------
|
|
16
16
|
logic [1-1:0] tmp0[9-1:0][2-1:0] ;
|
|
17
17
|
logic tmp1;
|
|
18
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
19
|
-
data_inf_c #(.DSIZE(18)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
18
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
19
|
+
data_inf_c #(.DSIZE(18),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- instance --------------------------------------------------------
|
|
22
22
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:32 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -21,8 +21,8 @@ module always_ff_test (
|
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
22
|
logic [1-1:0] tmp0[9-1:0][2-1:0] ;
|
|
23
23
|
logic tmp1;
|
|
24
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
25
|
-
data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
24
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
25
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
26
26
|
//==========================================================================
|
|
27
27
|
//-------- instance --------------------------------------------------------
|
|
28
28
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -21,8 +21,8 @@ module case_test (
|
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
22
|
logic [1-1:0] tmp0[9-1:0][2-1:0] ;
|
|
23
23
|
logic tmp1;
|
|
24
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
25
|
-
data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
24
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
25
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
26
26
|
//==========================================================================
|
|
27
27
|
//-------- instance --------------------------------------------------------
|
|
28
28
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -15,8 +15,8 @@ module simple_assign_test ();
|
|
|
15
15
|
//-------- define ----------------------------------------------------------
|
|
16
16
|
logic [1-1:0] tmp0[9-1:0][2-1:0] ;
|
|
17
17
|
logic tmp1;
|
|
18
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
19
|
-
data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
18
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
19
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
|
|
20
20
|
//==========================================================================
|
|
21
21
|
//-------- instance --------------------------------------------------------
|
|
22
22
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:32 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -21,8 +21,8 @@ module state_case_test (
|
|
|
21
21
|
//-------- define ----------------------------------------------------------
|
|
22
22
|
logic [1-1:0] tmp0[9-1:0][2-1:0] ;
|
|
23
23
|
logic tmp1;
|
|
24
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
|
|
25
|
-
data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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24
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+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
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25
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+
data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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28
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@@ -5,7 +5,7 @@ _______________________________________
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5
5
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descript:
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6
6
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author : Cook.Darwin
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7
7
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Version: VERA.0.0
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8
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-
created: 2021-04
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8
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+
created: 2021-05-04 20:03:33 +0800
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9
9
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madified:
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10
10
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***********************************************/
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11
11
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`timescale 1ns/1ps
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@@ -23,7 +23,7 @@ module test_module (
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23
23
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logic [axi_wr_inf.ASIZE-1:0] addr ;
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24
24
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logic [(axi_wr_inf.IDSIZE - 4)-1:0] id ;
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logic [24-1:0] length ;
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26
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-
axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE((axi_wr_inf.IDSIZE - 4)),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
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26
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+
axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE((axi_wr_inf.IDSIZE - 4)),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192),.FreqM(1.0)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
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//==========================================================================
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28
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//-------- instance --------------------------------------------------------
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29
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axi_stream_cache_35bit cache_inst(
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@@ -5,7 +5,7 @@ _______________________________________
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5
5
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descript:
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6
6
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author : Cook.Darwin
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|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04
|
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8
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+
created: 2021-05-04 20:03:33 +0800
|
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9
9
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madified:
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10
10
|
***********************************************/
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11
11
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`timescale 1ns/1ps
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@@ -21,7 +21,7 @@ module test_module_port (
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21
21
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//==========================================================================
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22
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//-------- define ----------------------------------------------------------
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23
23
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24
|
-
data_inf_c #(.DSIZE(test_data_inf_c.DSIZE)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
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24
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+
data_inf_c #(.DSIZE(test_data_inf_c.DSIZE),.FreqM(test_data_inf_c.FreqM)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
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//==========================================================================
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26
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//-------- instance --------------------------------------------------------
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27
27
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test_module_port_sub test_module_port_sub_inst(
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-
|
|
8
|
+
created: 2021-05-30 12:21:35 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
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|
11
11
|
`timescale 1ns/1ps
|
|
@@ -20,12 +20,12 @@ module test_module_var #(
|
|
|
20
20
|
//==========================================================================
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|
21
21
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//-------- define ----------------------------------------------------------
|
|
22
22
|
localparam ASIZE = 20 ;
|
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23
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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|
25
|
-
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|
|
23
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
24
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
25
|
+
axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
|
|
26
26
|
data_inf #(.DSIZE(5)) tmp_data_inf();
|
|
27
|
-
data_inf_c #(.DSIZE(3)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
|
|
28
|
-
data_inf_c #(.DSIZE(3)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
|
|
27
|
+
data_inf_c #(.DSIZE(3),.FreqM(100)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
|
|
28
|
+
data_inf_c #(.DSIZE(3),.FreqM(100)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
|
|
29
29
|
//==========================================================================
|
|
30
30
|
//-------- instance --------------------------------------------------------
|
|
31
31
|
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created: 2021-04
|
|
8
|
+
created: 2021-05-04 20:03:33 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -19,7 +19,7 @@ module main_md (
|
|
|
19
19
|
//==========================================================================
|
|
20
20
|
//-------- define ----------------------------------------------------------
|
|
21
21
|
|
|
22
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
22
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
|
|
23
23
|
//==========================================================================
|
|
24
24
|
//-------- instance --------------------------------------------------------
|
|
25
25
|
sdl_md sdl_md_inst(
|
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
|
5
5
|
descript:
|
|
6
6
|
author : Cook.Darwin
|
|
7
7
|
Version: VERA.0.0
|
|
8
|
-
created:
|
|
8
|
+
created: 2021-05-04 20:03:32 +0800
|
|
9
9
|
madified:
|
|
10
10
|
***********************************************/
|
|
11
11
|
`timescale 1ns/1ps
|
|
@@ -24,13 +24,13 @@ module example_interface (
|
|
|
24
24
|
//==========================================================================
|
|
25
25
|
//-------- define ----------------------------------------------------------
|
|
26
26
|
|
|
27
|
-
data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
|
|
28
|
-
data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
|
|
29
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
|
|
30
|
-
axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
|
|
31
|
-
axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
|
|
32
|
-
axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
|
|
33
|
-
axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
|
|
27
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
|
|
28
|
+
data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
|
|
29
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
|
|
30
|
+
axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
|
|
31
|
+
axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
|
|
32
|
+
axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
|
|
33
|
+
axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
|
|
34
34
|
//==========================================================================
|
|
35
35
|
//-------- instance --------------------------------------------------------
|
|
36
36
|
|