axi_tdl 0.0.9 → 0.0.19
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +44 -0
- data/.github/workflows/ruby.yml +35 -0
- data/.gitignore +3 -1
- data/.travis.yml +9 -0
- data/Gemfile +4 -0
- data/README.EN.md +322 -0
- data/README.md +24 -20
- data/Rakefile +2 -6
- data/axi_tdl.gemspec +5 -6
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
- data/lib/axi/common/common_ram_wrapper.sv +12 -12
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
- data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
- data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -2
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
- data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
- data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
- data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/originclass.rb +6 -1
- data/lib/tdl/elements/parameter.rb +1 -1
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
- data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -2
- data/lib/tdl/examples/9_itegration/test_tttop.sv +3 -3
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +264 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/test_unit_module.rb +272 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +53 -48
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +19 -4
- metadata +36 -137
- data/Gemfile.lock +0 -28
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
@@ -57,12 +57,14 @@ module ClassHDL
|
|
57
57
|
attr_accessor :opertor_chains,:name
|
58
58
|
attr_accessor :open_ivoke
|
59
59
|
attr_reader :return_type
|
60
|
+
attr_reader :belong_to_module
|
60
61
|
|
61
|
-
def initialize(name,return_type,*argvs)
|
62
|
+
def initialize(belong_to_module,name,return_type,*argvs)
|
62
63
|
@opertor_chains = []
|
63
64
|
@name = name
|
64
65
|
@argvs = argvs
|
65
66
|
@return_type = return_type
|
67
|
+
@belong_to_module = belong_to_module
|
66
68
|
end
|
67
69
|
|
68
70
|
def inst_port
|
@@ -117,7 +119,7 @@ module ClassHDL
|
|
117
119
|
|
118
120
|
def self.Function(sdl_m,name,return_type,*argvs,&block)
|
119
121
|
define_func_block_method(sdl_m,*argvs)
|
120
|
-
func_inst = ClassHDL::HDLFunction.new(name,return_type,*argvs)
|
122
|
+
func_inst = ClassHDL::HDLFunction.new(sdl_m,name,return_type,*argvs)
|
121
123
|
## 给 sdl module 定义函数方法
|
122
124
|
sdl_m.define_singleton_method(name) do |*fargvs|
|
123
125
|
# new_op = OpertorChain.new
|
@@ -3,9 +3,10 @@ module ClassHDL
|
|
3
3
|
class HDLAssignGenerateBlock
|
4
4
|
|
5
5
|
attr_accessor :opertor_chains
|
6
|
-
|
7
|
-
def initialize
|
6
|
+
attr_reader :belong_to_module
|
7
|
+
def initialize(belong_to_module)
|
8
8
|
@opertor_chains = []
|
9
|
+
@belong_to_module = belong_to_module
|
9
10
|
end
|
10
11
|
|
11
12
|
def instance
|
@@ -160,11 +161,11 @@ class SdlModule
|
|
160
161
|
add_children_modules(inst_obj:inst_obj ,module_poit: tmp_sm)
|
161
162
|
|
162
163
|
args.each_index do |e|
|
163
|
-
new_op = ClassHDL::OpertorChain.new
|
164
|
+
new_op = ClassHDL::OpertorChain.new(nil, self)
|
164
165
|
new_op.tree.push(["KK#{e}".to_nq])
|
165
166
|
kk_args << new_op
|
166
167
|
end
|
167
|
-
ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new ) do
|
168
|
+
ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new(self) ) do
|
168
169
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:new) do
|
169
170
|
tmp_sm.instance_exec(*kk_args,&block)
|
170
171
|
end
|
@@ -3,9 +3,10 @@ module ClassHDL
|
|
3
3
|
|
4
4
|
class HDLInitialBlock
|
5
5
|
attr_accessor :opertor_chains
|
6
|
-
|
7
|
-
def initialize
|
6
|
+
attr_reader :belong_to_module
|
7
|
+
def initialize(belong_to_module)
|
8
8
|
@opertor_chains = []
|
9
|
+
@belong_to_module = belong_to_module
|
9
10
|
end
|
10
11
|
|
11
12
|
def instance(block_name=nil)
|
@@ -28,7 +29,7 @@ module ClassHDL
|
|
28
29
|
end
|
29
30
|
|
30
31
|
def self.Initial(sdl_m,block_name=nil,&block)
|
31
|
-
ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new) do |ab|
|
32
|
+
ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new(sdl_m)) do |ab|
|
32
33
|
AssignDefOpertor.with_rollback_opertors(:new,&block)
|
33
34
|
# return ClassHDL::AssignDefOpertor.curr_assign_block
|
34
35
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
@@ -82,7 +83,7 @@ class SdlModule
|
|
82
83
|
return assert_old(cond,argv_str=formats,&block)
|
83
84
|
end
|
84
85
|
|
85
|
-
new_op = ClassHDL::BlocAssertIF.new
|
86
|
+
new_op = ClassHDL::BlocAssertIF.new(self)
|
86
87
|
ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
|
87
88
|
if cond.is_a? ClassHDL::OpertorChain
|
88
89
|
cond.slaver = true
|
@@ -102,7 +103,7 @@ class SdlModule
|
|
102
103
|
end
|
103
104
|
|
104
105
|
def assert_old(cond,argv_str=nil,&block)
|
105
|
-
new_op = ClassHDL::BlocAssertIF.new
|
106
|
+
new_op = ClassHDL::BlocAssertIF.new(self)
|
106
107
|
# if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
|
107
108
|
# new_op.slaver = true
|
108
109
|
# end
|
@@ -130,17 +131,17 @@ class SdlModule
|
|
130
131
|
end
|
131
132
|
|
132
133
|
def assert_error(argv_str)
|
133
|
-
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq]))
|
134
|
-
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
|
134
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq], self))
|
135
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
|
135
136
|
end
|
136
137
|
|
137
138
|
def assert_format_error(formats=[],args=[])
|
138
|
-
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq]))
|
139
|
-
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
|
139
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq], self))
|
140
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
|
140
141
|
end
|
141
142
|
|
142
143
|
def initial_exec(str)
|
143
|
-
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq]))
|
144
|
+
ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq], self))
|
144
145
|
end
|
145
146
|
|
146
147
|
alias_method :always_sim_exec, :initial_exec
|
@@ -70,6 +70,9 @@ module ClassHDL
|
|
70
70
|
def initialize(name,sdlm)
|
71
71
|
@name = name
|
72
72
|
@sdlm = sdlm
|
73
|
+
unless SdlModule.exist_module?(@name)
|
74
|
+
raise TdlError.new("Cant find module `#{name}` !!!")
|
75
|
+
end
|
73
76
|
end
|
74
77
|
|
75
78
|
def inst(dname,&block)
|
@@ -95,9 +98,23 @@ module ClassHDL
|
|
95
98
|
# else
|
96
99
|
# @sdlm.Instance(@name,dname.to_s,&block)
|
97
100
|
# end
|
101
|
+
rel = nil
|
98
102
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
99
|
-
|
103
|
+
if block_given?
|
104
|
+
rel = inst(dname,&block)
|
105
|
+
else
|
106
|
+
## 当没有block 判断 sdlm是否相应方法
|
107
|
+
# if @sdlm.has_signal?(dname)
|
108
|
+
# if SdlModule.call_module(@name).has_signal?(dname)
|
109
|
+
if SdlModule.call_module(@name).respond_to?(dname)
|
110
|
+
rel = SdlModule.call_module(@name).signal(dname)
|
111
|
+
else
|
112
|
+
# super
|
113
|
+
raise TdlError.new( "Cant find signal `#{dname}` in module `#{@name}` path: #{SdlModule.call_module(@name).real_sv_path } !!!" )
|
114
|
+
end
|
115
|
+
end
|
100
116
|
end
|
117
|
+
return rel
|
101
118
|
end
|
102
119
|
|
103
120
|
end
|
@@ -39,13 +39,14 @@ module ClassHDL
|
|
39
39
|
|
40
40
|
class OpertorChain
|
41
41
|
attr_accessor :slaver,:tree,:instance_add_brackets
|
42
|
-
|
43
|
-
def initialize(arg
|
42
|
+
attr_reader :belong_to_module
|
43
|
+
def initialize(arg, belong_to_module)
|
44
44
|
@tree = [] #[[inst0,symb0],[inst1,symb1],[other_chain,symb2],[other_chain,symb3]]
|
45
45
|
# self <symb0> inst0 <symb1> inst1 <symb2> ( other_chain ) <symb3> ( other_chain )
|
46
46
|
if arg
|
47
47
|
@tree << arg
|
48
48
|
end
|
49
|
+
@belong_to_module = belong_to_module
|
49
50
|
end
|
50
51
|
|
51
52
|
ClassHDL::OP_SYMBOLS.each do |os|
|
@@ -61,14 +62,14 @@ module ClassHDL
|
|
61
62
|
new_op = nil
|
62
63
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
63
64
|
if tree.size == 2 && tree.last[1].to_s == "<="
|
64
|
-
new_op = OpertorChain.new
|
65
|
+
new_op = OpertorChain.new(nil,belong_to_module)
|
65
66
|
new_op.tree = new_op.tree + self.tree
|
66
67
|
new_op.tree.push [b,os]
|
67
68
|
elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
|
68
69
|
new_op = brackets
|
69
70
|
new_op.tree.push [b,os]
|
70
71
|
else
|
71
|
-
new_op = OpertorChain.new
|
72
|
+
new_op = OpertorChain.new(nil,belong_to_module)
|
72
73
|
new_op.tree = new_op.tree + self.tree
|
73
74
|
new_op.tree.push [b,os]
|
74
75
|
end
|
@@ -107,12 +108,12 @@ module ClassHDL
|
|
107
108
|
|
108
109
|
def brackets
|
109
110
|
self.slaver = true
|
110
|
-
new_op = OpertorChain.new(["(#{self.instance})".to_nq])
|
111
|
+
new_op = OpertorChain.new(["(#{self.instance})".to_nq], belong_to_module)
|
111
112
|
end
|
112
113
|
|
113
114
|
def clog2
|
114
115
|
self.slaver = true
|
115
|
-
new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq])
|
116
|
+
new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq],belong_to_module)
|
116
117
|
end
|
117
118
|
|
118
119
|
def self.define_op_flag(ruby_op,hdl_op)
|
@@ -126,7 +127,7 @@ module ClassHDL
|
|
126
127
|
# 计算生成新的OpertorChain 是 self 也需要抛弃
|
127
128
|
self.slaver = true
|
128
129
|
# return self
|
129
|
-
new_op = OpertorChain.new
|
130
|
+
new_op = OpertorChain.new(nil, belong_to_module)
|
130
131
|
new_op.tree = new_op.tree + self.tree
|
131
132
|
new_op.tree.push [b,hdl_op]
|
132
133
|
|
@@ -159,10 +160,18 @@ module ClassHDL
|
|
159
160
|
sb = " = "
|
160
161
|
end
|
161
162
|
else
|
162
|
-
|
163
|
+
# if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
|
164
|
+
# sb = "#{node[1].root_ref.to_s}"
|
165
|
+
# else
|
166
|
+
sb = "#{node[1].to_s}"
|
167
|
+
# end
|
163
168
|
end
|
164
169
|
else
|
165
|
-
|
170
|
+
# if(node[1].respond_to?(:belong_to_module) && node[1].belong_to_module && node[1].belong_to_module != belong_to_module)
|
171
|
+
# sb = "#{node[1].root_ref.to_s}"
|
172
|
+
# else
|
173
|
+
sb = "#{node[1].to_s}"
|
174
|
+
# end
|
166
175
|
end
|
167
176
|
|
168
177
|
unless node[0].is_a? OpertorChain
|
@@ -173,7 +182,18 @@ module ClassHDL
|
|
173
182
|
# "如果是字符串 则原始输出"
|
174
183
|
str += (sb + '"' + node[0].to_s + '"')
|
175
184
|
else
|
176
|
-
str += (sb + node[0].to_s)
|
185
|
+
# str += (sb + node[0].to_s)
|
186
|
+
if(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
187
|
+
# sb = "#{node[1].root_ref.to_s}"
|
188
|
+
str += (sb + node[0].root_ref)
|
189
|
+
## 反向添加到 TestUnitModule
|
190
|
+
if belong_to_module.is_a?(TestUnitModule)
|
191
|
+
belong_to_module.add_root_ref_ele(node[0])
|
192
|
+
end
|
193
|
+
else
|
194
|
+
# sb = "#{node[1].to_s}"
|
195
|
+
str += (sb + node[0].to_s)
|
196
|
+
end
|
177
197
|
end
|
178
198
|
else
|
179
199
|
node[0].slaver = true
|
@@ -215,8 +235,8 @@ module ClassHDL
|
|
215
235
|
|
216
236
|
module AssignDefOpertor
|
217
237
|
@@included_class = []
|
218
|
-
@@curr_assign_block = HDLAssignBlock.new ##HDLAssignBlock ##HDLAlwaysCombBlock
|
219
|
-
@@curr_assign_block_stack = [HDLAssignBlock.new ]
|
238
|
+
@@curr_assign_block = HDLAssignBlock.new(nil) ##HDLAssignBlock ##HDLAlwaysCombBlock
|
239
|
+
@@curr_assign_block_stack = [HDLAssignBlock.new(nil) ]
|
220
240
|
@@curr_opertor_stack = [:old]
|
221
241
|
|
222
242
|
def self.curr_opertor_stack
|
@@ -275,7 +295,8 @@ module ClassHDL
|
|
275
295
|
if b.is_a? OpertorChain
|
276
296
|
b.slaver = true
|
277
297
|
end
|
278
|
-
|
298
|
+
## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
|
299
|
+
new_op = OpertorChain.new(nil,@@curr_assign_block && @@curr_assign_block.belong_to_module)
|
279
300
|
new_op.tree.push([self])
|
280
301
|
new_op.tree.push([b,symb])
|
281
302
|
if @@curr_assign_block
|
@@ -642,7 +663,7 @@ module TdlSpace
|
|
642
663
|
end
|
643
664
|
|
644
665
|
module ClassHDL
|
645
|
-
class StructVar
|
666
|
+
class StructVar < AxiTdl::SdlModuleActiveBaseElm
|
646
667
|
include ClassHDL::AssignDefOpertor
|
647
668
|
end
|
648
669
|
end
|
@@ -76,7 +76,7 @@ module ClassHDL
|
|
76
76
|
IF ~intf.rst_n do
|
77
77
|
track_ci <= 0.A
|
78
78
|
end
|
79
|
-
ELSIF intf.vld_rdy do
|
79
|
+
ELSIF intf.vld_rdy do
|
80
80
|
assert(intf.data == "#{mem_args}[#{track_ci}]".to_nq,"TRACK <#{intf.to_s}> Error;","Real<%d>"," != Expect<%d>",intf.data,"#{mem_args}[#{track_ci}]".to_nq)
|
81
81
|
track_ci <= track_ci + 1.b1
|
82
82
|
end
|
@@ -99,8 +99,13 @@ module TdlSpace
|
|
99
99
|
end
|
100
100
|
end
|
101
101
|
|
102
|
+
module AxiTdl
|
103
|
+
class SdlModuleActiveBaseElm
|
104
|
+
end
|
105
|
+
end
|
106
|
+
|
102
107
|
|
103
|
-
class BaseElm
|
108
|
+
class BaseElm < AxiTdl::SdlModuleActiveBaseElm
|
104
109
|
# attr_accessor :belong_module
|
105
110
|
attr_accessor :belong_to_module
|
106
111
|
attr_accessor :name
|
@@ -183,7 +183,7 @@ class Parameter # add +
|
|
183
183
|
else
|
184
184
|
rel = NqString.new(signal.concat("#{symb}").concat('"').concat(a.to_s)).concat('"')
|
185
185
|
end
|
186
|
-
new_op = ClassHDL::OpertorChain.new
|
186
|
+
new_op = ClassHDL::OpertorChain.new(nil,belong_to_module)
|
187
187
|
new_op.tree.push([rel])
|
188
188
|
|
189
189
|
return new_op
|
@@ -28,9 +28,9 @@ module exp_random #(
|
|
28
28
|
//==========================================================================
|
29
29
|
//-------- expression ------------------------------------------------------
|
30
30
|
initial begin
|
31
|
-
|
32
|
-
|
33
|
-
|
31
|
+
param_random_b = $urandom_range(0,99) <= PX;
|
32
|
+
int_random_b = $urandom_range(1,100) > 34;
|
33
|
+
rd_range = $urandom_range(12,1000);
|
34
34
|
end
|
35
35
|
|
36
36
|
endmodule
|
@@ -12,6 +12,128 @@ gui_set_time_units 1ps
|
|
12
12
|
## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
|
13
13
|
## ==== [add_signal] ===== ##
|
14
14
|
|
15
|
+
## -------------- sub_md0_logic -------------------------
|
16
|
+
set _wave_session_group_sub_md0_logic sub_md0_logic
|
17
|
+
# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
|
18
|
+
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
|
19
|
+
set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
|
20
|
+
}
|
21
|
+
set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
|
22
|
+
|
23
|
+
## 添加信号到 group
|
24
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
|
25
|
+
## ============== sub_md0_logic =========================
|
26
|
+
|
27
|
+
|
28
|
+
## -------------- sub_md0_interface -------------------------
|
29
|
+
set _wave_session_group_sub_md0_interface sub_md0_interface
|
30
|
+
# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
|
31
|
+
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
|
32
|
+
set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
|
33
|
+
}
|
34
|
+
set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
|
35
|
+
|
36
|
+
## 添加信号到 group
|
37
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
|
38
|
+
## ============== sub_md0_interface =========================
|
39
|
+
|
40
|
+
|
41
|
+
## -------------- sub_md0_default -------------------------
|
42
|
+
set _wave_session_group_sub_md0_default sub_md0_default
|
43
|
+
# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
|
44
|
+
if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
|
45
|
+
set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
|
46
|
+
}
|
47
|
+
set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
|
48
|
+
|
49
|
+
## 添加信号到 group
|
50
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
|
51
|
+
## ============== sub_md0_default =========================
|
52
|
+
|
53
|
+
|
54
|
+
## -------------- sub_md0_default.inter_tf -------------------------
|
55
|
+
## set _wave_session_group_sub_md0_default_inter_tf Group1
|
56
|
+
## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
|
57
|
+
|
58
|
+
set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
|
59
|
+
append _wave_session_group_sub_md0_default_inter_tf inter_tf
|
60
|
+
set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
|
61
|
+
|
62
|
+
# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
|
63
|
+
|
64
|
+
## 添加信号到 group
|
65
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
|
66
|
+
## ============== sub_md0_default.inter_tf =========================
|
67
|
+
|
68
|
+
|
69
|
+
## -------------- sub_md1_default -------------------------
|
70
|
+
set _wave_session_group_sub_md1_default sub_md1_default
|
71
|
+
# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
|
72
|
+
if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
|
73
|
+
set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
|
74
|
+
}
|
75
|
+
set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
|
76
|
+
|
77
|
+
## 添加信号到 group
|
78
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
|
79
|
+
## ============== sub_md1_default =========================
|
80
|
+
|
81
|
+
|
82
|
+
## -------------- sub_md1_inner -------------------------
|
83
|
+
set _wave_session_group_sub_md1_inner sub_md1_inner
|
84
|
+
# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
|
85
|
+
if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
|
86
|
+
set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
|
87
|
+
}
|
88
|
+
set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
|
89
|
+
|
90
|
+
## 添加信号到 group
|
91
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
|
92
|
+
## ============== sub_md1_inner =========================
|
93
|
+
|
94
|
+
|
95
|
+
## -------------- sub_md1_inner.inter_tf -------------------------
|
96
|
+
## set _wave_session_group_sub_md1_inner_inter_tf Group1
|
97
|
+
## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
|
98
|
+
|
99
|
+
set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
|
100
|
+
append _wave_session_group_sub_md1_inner_inter_tf inter_tf
|
101
|
+
set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
102
|
+
|
103
|
+
# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
|
104
|
+
|
105
|
+
## 添加信号到 group
|
106
|
+
gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
|
107
|
+
## ============== sub_md1_inner.inter_tf =========================
|
108
|
+
|
109
|
+
|
110
|
+
## -------------- exp_test_unit_default -------------------------
|
111
|
+
set _wave_session_group_exp_test_unit_default exp_test_unit_default
|
112
|
+
# set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
|
113
|
+
if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
|
114
|
+
set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
|
115
|
+
}
|
116
|
+
set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
|
117
|
+
|
118
|
+
## 添加信号到 group
|
119
|
+
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
|
120
|
+
## ============== exp_test_unit_default =========================
|
121
|
+
|
122
|
+
|
123
|
+
## -------------- exp_test_unit_default.axis_data_inf -------------------------
|
124
|
+
## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
|
125
|
+
## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
|
126
|
+
|
127
|
+
set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
|
128
|
+
append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
|
129
|
+
set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
|
130
|
+
|
131
|
+
# set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
|
132
|
+
|
133
|
+
## 添加信号到 group
|
134
|
+
gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
|
135
|
+
## ============== exp_test_unit_default.axis_data_inf =========================
|
136
|
+
|
15
137
|
|
16
138
|
## 创建波形窗口
|
17
139
|
if {![info exists useOldWindow]} {
|
@@ -40,7 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
|
|
40
162
|
## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
|
41
163
|
## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
|
42
164
|
## === [add_signal_wave] === ##
|
43
|
-
|
165
|
+
## -------------- Group2_sub_md0_logic -------------------------
|
166
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
|
167
|
+
## ============== Group2_sub_md0_logic =========================
|
168
|
+
## -------------- Group2_sub_md0_interface -------------------------
|
169
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
|
170
|
+
## ============== Group2_sub_md0_interface =========================
|
171
|
+
## -------------- Group2_sub_md0_default -------------------------
|
172
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
|
173
|
+
## ============== Group2_sub_md0_default =========================
|
174
|
+
## -------------- sub_md0_default|inter_tf -------------------------
|
175
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
|
176
|
+
## ============== sub_md0_default|inter_tf =========================
|
177
|
+
## -------------- Group2_sub_md1_default -------------------------
|
178
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
|
179
|
+
## ============== Group2_sub_md1_default =========================
|
180
|
+
## -------------- Group2_sub_md1_inner -------------------------
|
181
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
|
182
|
+
## ============== Group2_sub_md1_inner =========================
|
183
|
+
## -------------- sub_md1_inner|inter_tf -------------------------
|
184
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
|
185
|
+
## ============== sub_md1_inner|inter_tf =========================
|
186
|
+
## -------------- Group2_exp_test_unit_default -------------------------
|
187
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
|
188
|
+
## ============== Group2_exp_test_unit_default =========================
|
189
|
+
## -------------- exp_test_unit_default|axis_data_inf -------------------------
|
190
|
+
gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
|
191
|
+
## ============== exp_test_unit_default|axis_data_inf =========================
|
44
192
|
|
45
193
|
gui_seek_criteria -id ${Wave.3} {Any Edge}
|
46
194
|
|
@@ -57,7 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
|
|
57
205
|
gui_list_set_filter -id ${Wave.3} -text {*}
|
58
206
|
##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
|
59
207
|
## === [add_bar] === ##
|
60
|
-
|
208
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
|
209
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
|
210
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
|
211
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
|
212
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
|
213
|
+
gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
|
61
214
|
|
62
215
|
gui_marker_move -id ${Wave.3} {C1} 560248001
|
63
216
|
gui_view_scroll -id ${Wave.3} -vertical -set 35
|