axi_tdl 0.0.9 → 0.0.19

data/lib/tdl/tdl.rb

@@ -81,6 +81,9 @@ require_relative "./rebuild_ele/data_inf_c.rb"
 require_relative "./rebuild_ele/axi_lite.rb"
 require_relative "./rebuild_ele/cm_ram_inf_define.rb"
 
+## 添加axis 流slice功能
+require_relative "./exlib/axis_eth_ex.rb"
+
 require_relative "./bfm/axi_stream/axi_stream_bfm.rb"
 
 require_relative "./exlib/constraints"
@@ -118,6 +121,12 @@ require_relative "./sdlmodule/test_unit_module.rb"
 ## 添加 DVE TCL 支持
 require_relative "./exlib/dve_tcl.rb"
 
+## 添加 verify 
+require_relative "./exlib/axis_verify.rb"
+require_relative "./exlib/clock_reset_verify.rb"
+require_relative "./exlib/logic_verify.rb"
+
+
 ## --- INIT BLOCK Methods -----
 # AutoGenSdl.add_inf_parse TrackInf.method(:parse_ports)
 # SdlInst.add_inst_t0_method TrackInf.method(:sdlinst_t0)
@@ -127,7 +136,7 @@ require_relative "./exlib/dve_tcl.rb"
 
 ## === INIT BLOCK Methods =====
 $argvs_hash = {}
-$argvs_hash = Parser.parse($TdlARGV || ARGV) unless $_child_argv_
+$argvs_hash = Parser.parse($TdlARGV || ARGV) 
 TopModule.sim = $argvs_hash[:sim]
 
 class Tdl
@@ -175,6 +184,7 @@ class Tdl # add file paths
          else
              @@all_file_paths[a] = b
          end
+
      end
 
      def self.all_file_paths
@@ -250,12 +260,14 @@ class Tdl
         self.log_array("LOG FOR GEN SDLMOUDLE",@@build_sdlmodule_collect)
         self.log_array("LOG OF WARNING",@@warning_collect)
         # puts(page(tag: "SUMMARY" ,body: "RUN @ TIME : #{Time.now}"))
-        puts(pagination("TEST POINT"))
-        puts TdlTestPoint.echo_list
+        puts(pagination("TEST POINT")) if TopModule.current
+        # puts TdlTestPoint.echo_list
         # puts(pagination("SIM TEST"))
         # puts TdlSimTest::TdlBaseTestUnit.echo_prj_test_list
+        puts SdlModule.echo_tracked_by_dve if TopModule.current && TopModule.sim
         puts(pagination("TEST UNIT")) if TopModule.current
-        puts TopModule.current.test_unit.echo_units if TopModule.current
+        # puts TopModule.current.test_unit.echo_units if TopModule.current
+        puts TestUnitModule.echo_be_instanced_by_sim if TopModule.current
         puts(pagination("SUMMARY"))
         puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
 
@@ -266,6 +278,9 @@ class Tdl
         #     end
         # end
         ## ===========
+        # File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
+        #     f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
+        # end
     end
 
 end

metadata

@@ -1,29 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.0.9
+  version: 0.0.19
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-03-08 00:00:00.000000000 Z
+date: 2021-03-20 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: bundler
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - "~>"
-      - !ruby/object:Gem::Version
-        version: '1.16'
-  type: :development
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - "~>"
-      - !ruby/object:Gem::Version
-        version: '1.16'
 - !ruby/object:Gem::Dependency
   name: rake
   requirement: !ruby/object:Gem::Requirement
@@ -42,43 +28,46 @@ dependencies:
   name: pry
   requirement: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '0'
+        version: '0.11'
   type: :development
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '0'
+        version: '0.11'
 - !ruby/object:Gem::Dependency
   name: minitest
   requirement: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '0'
+        version: '5.10'
   type: :development
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '0'
-description: 'tdl is a hardware Construction language, it like chisel, but more intresting.
-  It is a DSL and base on ruby. Finally, it convert to systemverilog. '
+        version: '5.10'
+description: 'tdl 是一种硬件构造语言, 和chisel类似, 但是更加有趣, 他是一种基于Ruby的DSL. 最终它会编译输出systemverilog
+  。 '
 email:
 - cook_darwin@hotmail.com
 executables: []
 extensions: []
 extra_rdoc_files: []
 files:
+- ".github/workflows/gem-push.yml"
+- ".github/workflows/ruby.yml"
 - ".gitignore"
+- ".travis.yml"
 - CODE_OF_CONDUCT.md
 - Gemfile
-- Gemfile.lock
 - LICENSE
+- README.EN.md
 - README.md
 - Rakefile
 - axi_tdl.gemspec
@@ -220,7 +209,6 @@ files:
 - lib/axi/AXI_stream/axi_stream_partition_A1.sv
 - lib/axi/AXI_stream/axi_stream_planer.sv
 - lib/axi/AXI_stream/axi_stream_split_channel.rb
-- lib/axi/AXI_stream/axi_stream_split_channel.sv
 - lib/axi/AXI_stream/axi_streams_combin.sv
 - lib/axi/AXI_stream/axi_streams_combin_A1.sv
 - lib/axi/AXI_stream/axi_streams_scaler.sv
@@ -242,10 +230,8 @@ files:
 - lib/axi/AXI_stream/axis_head_cut.sv
 - lib/axi/AXI_stream/axis_head_cut_verb.sv
 - lib/axi/AXI_stream/axis_head_cut_verc.rb
-- lib/axi/AXI_stream/axis_head_cut_verc.sv
 - lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv
 - lib/axi/AXI_stream/axis_insert_copy.rb
-- lib/axi/AXI_stream/axis_insert_copy.sv
 - lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv
@@ -261,18 +247,18 @@ files:
 - lib/axi/AXI_stream/axis_mirrors.sv
 - lib/axi/AXI_stream/axis_orthogonal.sv
 - lib/axi/AXI_stream/axis_pipe_sync_seam.rb
-- lib/axi/AXI_stream/axis_pipe_sync_seam.sv
 - lib/axi/AXI_stream/axis_ram_buffer.sv
 - lib/axi/AXI_stream/axis_rom_contect.rb
 - lib/axi/AXI_stream/axis_rom_contect.sv
 - lib/axi/AXI_stream/axis_rom_contect_sim.rb
-- lib/axi/AXI_stream/axis_rom_contect_sim.sv
+- lib/axi/AXI_stream/axis_sim_master_model.rb
+- lib/axi/AXI_stream/axis_sim_slaver_model.rb
+- lib/axi/AXI_stream/axis_sim_verify_by_coe.sv
 - lib/axi/AXI_stream/axis_slaver_empty.sv
 - lib/axi/AXI_stream/axis_slaver_pipe.sv
 - lib/axi/AXI_stream/axis_slaver_pipe_A1.sv
 - lib/axi/AXI_stream/axis_slaver_vector_empty.sv
 - lib/axi/AXI_stream/axis_split_channel_verb.rb
-- lib/axi/AXI_stream/axis_split_channel_verb.sv
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.rb
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.sv
 - lib/axi/AXI_stream/axis_to_data_inf.sv
@@ -408,6 +394,8 @@ files:
 - lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv
 - lib/axi/data_interface/data_inf_c/data_c_scaler.sv
 - lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv
+- lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv
+- lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv
 - lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv
 - lib/axi/data_interface/data_inf_c/data_condition_mirror.sv
 - lib/axi/data_interface/data_inf_c/data_condition_valve.sv
@@ -426,6 +414,7 @@ files:
 - lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak
 - lib/axi/data_interface/data_inf_c/data_uncompress.sv
 - lib/axi/data_interface/data_inf_c/data_valve.sv
+- lib/axi/data_interface/data_inf_c/logic_sim_model.sv
 - lib/axi/data_interface/data_inf_c/next_prio.sv
 - lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv
 - lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv
@@ -525,6 +514,10 @@ files:
 - lib/axi/platform_ip/xilinx_fifo_verb.sv
 - lib/axi/platform_ip/xilinx_fifo_verc.sv
 - lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv
+- lib/axi/techbench/tb_axi_stream_split_channel.rb
+- lib/axi/techbench/tb_axi_stream_split_channel.sv
+- lib/axi/techbench/tb_axis_split_channel_verb.rb
+- lib/axi/techbench/tb_axis_split_channel_verb.sv
 - lib/axi/top/axi4_data_convert_2_20_tb.sv
 - lib/axi/top/axi4_data_convert_5_24_tb.sv
 - lib/axi/top/axi4_interconnnect_2_24_tb.sv
@@ -829,108 +822,6 @@ files:
 - lib/tdl/auto_script/import_sdl.rb
 - lib/tdl/auto_script/test_autogensdl.rb
 - lib/tdl/auto_script/tmp.rb
-- lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb
-- lib/tdl/auto_script/tmp/acce_iic_bus_upgrade_sdl.rb
-- lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb
-- lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb
-- lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb
-- lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb
-- lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_bind_tuser_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_latency_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb
-- lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb
-- lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb
-- lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb
-- lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb
-- lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb
-- lib/tdl/auto_script/tmp/axis_direct_sdl.rb
-- lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb
-- lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb
-- lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb
-- lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb
-- lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb
-- lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb
-- lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb
-- lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb
-- lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb
-- lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb
-- lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axis_valve_sdl.rb
-- lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb
-- lib/tdl/auto_script/tmp/axis_vector_slaver_empty_sdl.rb
-- lib/tdl/auto_script/tmp/axis_width_combin_A1_sdl.rb
-- lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb
-- lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb
-- lib/tdl/auto_script/tmp/bits_decode_nc_verb_sdl.rb
-- lib/tdl/auto_script/tmp/bits_decode_verb_sdl.rb
-- lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb
-- lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb
-- lib/tdl/auto_script/tmp/common_fifo_sdl.rb
-- lib/tdl/auto_script/tmp/data_c_cache_sdl.rb
-- lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb
-- lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb
-- lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb
-- lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb
-- lib/tdl/auto_script/tmp/data_mirrors_sdl.rb
-- lib/tdl/auto_script/tmp/data_valve_sdl.rb
-- lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb
-- lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb
-- lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb
-- lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb
-- lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb
-- lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb
-- lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb
-- lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb
-- lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb
-- lib/tdl/auto_script/tmp/hdl_test_sdl.rb
-- lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb
-- lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb
-- lib/tdl/auto_script/tmp/init_mac_sdl.rb
-- lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb
-- lib/tdl/auto_script/tmp/k7_ethernet_10g_api_mask_shift_sdl.rb
-- lib/tdl/auto_script/tmp/k7_ethernet_10g_api_sdl.rb
-- lib/tdl/auto_script/tmp/mac_to_file_64b_sdl.rb
-- lib/tdl/auto_script/tmp/mac_to_file_sdl.rb
-- lib/tdl/auto_script/tmp/mdio_model_sdl.rb
-- lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb
-- lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb
-- lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb
-- lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb
-- lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb
-- lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb
-- lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb
-- lib/tdl/auto_script/tmp/sensor_array_ddr_lvds_wrapper_sdl.rb
-- lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb
-- lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb
-- lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb
-- lib/tdl/auto_script/tmp/tcp_option_split_sdl.rb
-- lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb
-- lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb
-- lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb
-- lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb
-- lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb
-- lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb
-- lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb
-- lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb
-- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb
-- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb
-- lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb
-- lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb
-- lib/tdl/auto_script/tmp/width_convert_verb_sdl.rb
-- lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb
-- lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb
 - lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb
 - lib/tdl/axi4/axi4_direct.rb
 - lib/tdl/axi4/axi4_direct_A1_auto.rb
@@ -1323,6 +1214,9 @@ files:
 - lib/tdl/examples/9_itegration/test_tttop_constraints.xdc
 - lib/tdl/examples/9_itegration/top.rb
 - lib/tdl/examples/readme.md
+- lib/tdl/exlib/axis_eth_ex.rb
+- lib/tdl/exlib/axis_verify.rb
+- lib/tdl/exlib/clock_reset_verify.rb
 - lib/tdl/exlib/common_cfg_reg_inf.rb
 - lib/tdl/exlib/constraints.rb
 - lib/tdl/exlib/constraints_verb.rb
@@ -1337,9 +1231,11 @@ files:
 - lib/tdl/exlib/integral_test/simple_logic_itest.rb
 - lib/tdl/exlib/itegration.rb
 - lib/tdl/exlib/itegration_verb.rb
+- lib/tdl/exlib/logic_verify.rb
 - lib/tdl/exlib/parse_argv.rb
 - lib/tdl/exlib/sdlmodule_sim.bak.rb
 - lib/tdl/exlib/test_point.rb
+- lib/tdl/exlib/test_point.rb.bak
 - lib/tdl/global_scan.rb
 - lib/tdl/rebuild_ele/axi4.rb
 - lib/tdl/rebuild_ele/axi_lite.rb
@@ -1356,6 +1252,7 @@ files:
 - lib/tdl/sdlimplement/test.rb
 - lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb
 - lib/tdl/sdlmodule/generator_block_module.rb
+- lib/tdl/sdlmodule/sdlmodlule_path_db.rb
 - lib/tdl/sdlmodule/sdlmodule.rb
 - lib/tdl/sdlmodule/sdlmodule_arraychain.rb
 - lib/tdl/sdlmodule/sdlmodule_draw.rb
@@ -1366,7 +1263,9 @@ files:
 - lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb
 - lib/tdl/sdlmodule/techbench_module.rb
 - lib/tdl/sdlmodule/test_unit_module.rb
+- lib/tdl/sdlmodule/test_unit_module.rb.bak
 - lib/tdl/sdlmodule/top_module.rb
+- lib/tdl/sdlmodule/top_module.rb.bak
 - lib/tdl/tdl.rb
 - lib/tdl/tdlerror/tdlerror.rb
 - lib/tdl/testunit/test_all.rb
@@ -1391,8 +1290,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.6
+rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: Axi is a light weight axi library. Tdl is a hardware Construction language
+summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言
 test_files: []

data/Gemfile.lock

@@ -1,28 +0,0 @@
-PATH
-  remote: .
-  specs:
-    axi_tdl (0.0.9)
-
-GEM
-  remote: https://rubygems.org/
-  specs:
-    coderay (1.1.3)
-    method_source (1.0.0)
-    minitest (5.14.3)
-    pry (0.14.0)
-      coderay (~> 1.1)
-      method_source (~> 1.0)
-    rake (10.5.0)
-
-PLATFORMS
-  ruby
-
-DEPENDENCIES
-  axi_tdl!
-  bundler (~> 1.16)
-  minitest
-  pry
-  rake (~> 10.0)
-
-BUNDLED WITH
-   1.17.3

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -1,149 +0,0 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-created: xxxx.xx.xx
-madified:
-***********************************************/
-`timescale 1ns/1ps
-
-module axi_stream_split_channel (
-    input [15:0]            split_len,
-    axi_stream_inf.slaver   origin_inf,
-    axi_stream_inf.master   first_inf,
-    axi_stream_inf.master   end_inf
-);
-
-//==========================================================================
-//-------- define ----------------------------------------------------------
-logic  clock;
-logic  rst_n;
-logic addr;
-logic new_last;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
-//==========================================================================
-//-------- instance --------------------------------------------------------
-axi_stream_interconnect_S2M #(
-    .NUM   (2 )
-)axi_stream_interconnect_S2M_inst(
-/* input                 */.addr (addr                ),
-/* axi_stream_inf.slaver */.s00  (origin_inf_add_last ),
-/* axi_stream_inf.master */.m00  (sub_origin_inf      )
-);
-//==========================================================================
-//-------- expression ------------------------------------------------------
-
-axi_stream_inf #(.DSIZE(first_inf.DSIZE))  sub_first_inf[1-1:0](.aclk(first_inf.aclk),.aresetn(first_inf.aresetn),.aclken(1'b1));
-
-
-axis_direct  axis_direct_first_inf_inst0 (
-/*  axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
-/*  axi_stream_inf.master*/ .master (sub_first_inf[0])
-);
-
-
-axi_stream_inf #(.DSIZE(end_inf.DSIZE))  sub_end_inf[1-1:0](.aclk(end_inf.aclk),.aresetn(end_inf.aresetn),.aclken(1'b1));
-
-
-axis_direct  axis_direct_end_inf_inst0 (
-/*  axi_stream_inf.slaver*/ .slaver (sub_origin_inf[1]),
-/*  axi_stream_inf.master*/ .master (sub_end_inf[0])
-);
-//-------- CLOCKs Total 3 ----------------------
-//--->> CheckClock <<----------------
-logic cc_done_8,cc_same_8;
-integer cc_afreq_8,cc_bfreq_8;
-ClockSameDomain CheckPClock_inst_8(
-/*  input         */      .aclk     (origin_inf.aclk        ),
-/*  input         */      .bclk     (first_inf.aclk         ),
-/*  output logic  */      .done     (cc_done_8),
-/*  output logic  */      .same     (cc_same_8),
-/*  output integer */     .aFreqK   (cc_afreq_8),
-/*  output integer */     .bFreqK   (cc_bfreq_8)
-);
-
-initial begin
-    wait(cc_done_8);
-    assert(cc_same_8)
-    else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
-        repeat(10)begin 
-            @(posedge origin_inf.aclk);
-        end
-        $stop;
-    end
-end
-//---<< CheckClock >>----------------
-
-//--->> CheckClock <<----------------
-logic cc_done_9,cc_same_9;
-integer cc_afreq_9,cc_bfreq_9;
-ClockSameDomain CheckPClock_inst_9(
-/*  input         */      .aclk     (origin_inf.aclk        ),
-/*  input         */      .bclk     (end_inf.aclk           ),
-/*  output logic  */      .done     (cc_done_9),
-/*  output logic  */      .same     (cc_same_9),
-/*  output integer */     .aFreqK   (cc_afreq_9),
-/*  output integer */     .bFreqK   (cc_bfreq_9)
-);
-
-initial begin
-    wait(cc_done_9);
-    assert(cc_same_9)
-    else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
-        repeat(10)begin 
-            @(posedge origin_inf.aclk);
-        end
-        $stop;
-    end
-end
-//---<< CheckClock >>----------------
-
-//======== CLOCKs Total 3 ======================
-assign  clock = origin_inf.aclk;
-assign  rst_n = origin_inf.aresetn;
-
-always_ff@(posedge clock,negedge rst_n) begin 
-    if(~rst_n)begin
-         addr <= 1'b0;
-         new_last <= 1'b0;
-    end
-    else begin
-         new_last <= ( origin_inf.axis_tcnt==( split_len-2)&& origin_inf.axis_tvalid && origin_inf.axis_tready);
-        if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
-             addr <= 1'b0;
-        end
-        else if( origin_inf.axis_tcnt==( split_len-1)&& origin_inf.axis_tvalid && origin_inf.axis_tready)begin
-             addr <= 1'b1;
-        end
-        else begin
-             addr <= addr;
-        end
-    end
-end
-
-assign  origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
-assign  origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
-assign  origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
-assign  origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
-assign  origin_inf_add_last.axis_tlast = ( origin_inf.axis_tlast|new_last);
-assign  origin_inf.axis_tready = origin_inf_add_last.axis_tready;
-
-
-axis_direct  axis_direct_first_inf_instMM (
-/*  axi_stream_inf.slaver*/ .slaver (sub_first_inf[0]),
-/*  axi_stream_inf.master*/ .master (first_inf)
-);
-
-
-axis_direct  axis_direct_end_inf_instMM (
-/*  axi_stream_inf.slaver*/ .slaver (sub_end_inf[0]),
-/*  axi_stream_inf.master*/ .master (end_inf)
-);
-
-endmodule