axi_tdl 0.0.9 → 0.0.19

Sign up to get free protection for your applications and to get access to all the features.
Files changed (116) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +44 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +322 -0
  8. data/README.md +24 -20
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +5 -6
  11. data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
  17. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
  19. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
  20. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
  21. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
  22. data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
  23. data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
  24. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
  25. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
  26. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
  27. data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
  28. data/lib/axi/common/common_ram_wrapper.sv +12 -12
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
  31. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
  32. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
  35. data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
  36. data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
  37. data/lib/axi_tdl.rb +1 -0
  38. data/lib/axi_tdl/version.rb +1 -1
  39. data/lib/tdl/auto_script/autogensdl.rb +16 -5
  40. data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
  41. data/lib/tdl/basefunc.rb +1 -0
  42. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
  43. data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
  44. data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
  45. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
  46. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  47. data/lib/tdl/class_hdl/hdl_function.rb +4 -2
  48. data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
  49. data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
  50. data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
  51. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
  52. data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
  53. data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
  54. data/lib/tdl/elements/originclass.rb +6 -1
  55. data/lib/tdl/elements/parameter.rb +1 -1
  56. data/lib/tdl/examples/10_random/exp_random.sv +3 -3
  57. data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
  58. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
  59. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  60. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
  61. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
  62. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
  63. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
  64. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
  65. data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
  66. data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
  67. data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
  68. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
  69. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
  70. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
  71. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
  72. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
  73. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
  74. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
  75. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
  76. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
  77. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
  78. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
  79. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
  80. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
  81. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
  82. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  83. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
  84. data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
  85. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
  86. data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
  87. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
  88. data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
  89. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
  90. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -2
  91. data/lib/tdl/examples/9_itegration/test_tttop.sv +3 -3
  92. data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
  93. data/lib/tdl/exlib/axis_verify.rb +264 -0
  94. data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
  95. data/lib/tdl/exlib/dve_tcl.rb +30 -11
  96. data/lib/tdl/exlib/itegration.rb +15 -3
  97. data/lib/tdl/exlib/logic_verify.rb +88 -0
  98. data/lib/tdl/exlib/test_point.rb +96 -94
  99. data/lib/tdl/exlib/test_point.rb.bak +293 -0
  100. data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
  101. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
  102. data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
  103. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
  104. data/lib/tdl/sdlmodule/test_unit_module.rb +272 -33
  105. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
  106. data/lib/tdl/sdlmodule/top_module.rb +53 -48
  107. data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
  108. data/lib/tdl/tdl.rb +19 -4
  109. metadata +36 -137
  110. data/Gemfile.lock +0 -28
  111. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
  112. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
  113. data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
  114. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
  115. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
  116. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
data/lib/axi/AXI_stream/axis_split_channel_verb.sv DELETED
@@ -1,62 +0,0 @@
1
- /**********************************************
2
- _______________________________________
3
- ___________ Cook Darwin __________
4
- _______________________________________
5
- descript:
6
- author : Cook.Darwin
7
- Version: VERA.0.0
8
- created: xxxx.xx.xx
9
- madified:
10
- ***********************************************/
11
- `timescale 1ns/1ps
12
-
13
- module axis_split_channel_verb (
14
- input [15:0] split_len,
15
- axi_stream_inf.slaver origin_inf,
16
- axi_stream_inf.master first_inf,
17
- axi_stream_inf.master end_inf
18
- );
19
-
20
- //==========================================================================
21
- //-------- define ----------------------------------------------------------
22
- logic clock;
23
- logic rst_n;
24
- logic [16-1:0] insert_seed ;
25
- logic [16-1:0] next_split_len ;
26
- axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
27
- //==========================================================================
28
- //-------- instance --------------------------------------------------------
29
- axis_insert_copy axis_insert_copy_inst(
30
- /* input */.insert_seed (insert_seed ),
31
- /* input */.insert_len (8'd1 ),
32
- /* axi_stream_inf.slaver */.in_inf (origin_inf ),
33
- /* axi_stream_inf.master */.out_inf (origin_inf_insert )
34
- );
35
- common_fifo #(
36
- .DEPTH (4 ),
37
- .DSIZE (16 )
38
- )common_fifo_head_bytesx_inst(
39
- /* input */.clock (clock ),
40
- /* input */.rst_n (rst_n ),
41
- /* input */.wdata (split_len ),
42
- /* input */.wr_en ((origin_inf.axis_tcnt == '0) && origin_inf.axis_tvalid && origin_inf.axis_tready ),
43
- /* output */.rdata (next_split_len ),
44
- /* input */.rd_en (origin_inf_insert.axis_tvalid && origin_inf_insert.axis_tready && origin_inf_insert.axis_tlast ),
45
- /* output */.count (/*unused */ ),
46
- /* output */.empty (/*unused */ ),
47
- /* output */.full (/*unused */ )
48
- );
49
- axi_stream_split_channel axi_stream_split_channel_inst(
50
- /* input */.split_len (next_split_len ),
51
- /* axi_stream_inf.slaver */.origin_inf (origin_inf_insert ),
52
- /* axi_stream_inf.master */.first_inf (first_inf ),
53
- /* axi_stream_inf.master */.end_inf (end_inf )
54
- );
55
- //==========================================================================
56
- //-------- expression ------------------------------------------------------
57
- assign clock = origin_inf.aclk;
58
- assign rst_n = origin_inf.aresetn;
59
-
60
- assign insert_seed = ( split_len-1'b1);
61
-
62
- endmodule