axi_tdl 0.0.9 → 0.0.19

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Files changed (116) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +44 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +322 -0
  8. data/README.md +24 -20
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +5 -6
  11. data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +33 -33
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +20 -20
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +32 -32
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
  17. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +71 -71
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
  19. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +23 -23
  20. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
  21. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
  22. data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
  23. data/lib/axi/AXI_stream/axis_sim_master_model.rb +28 -0
  24. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
  25. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
  26. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
  27. data/lib/axi/common/common_ram_sim_wrapper.sv +9 -9
  28. data/lib/axi/common/common_ram_wrapper.sv +12 -12
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +26 -26
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +69 -0
  31. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
  32. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
  33. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
  34. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +149 -0
  35. data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
  36. data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
  37. data/lib/axi_tdl.rb +1 -0
  38. data/lib/axi_tdl/version.rb +1 -1
  39. data/lib/tdl/auto_script/autogensdl.rb +16 -5
  40. data/lib/tdl/axi4/axi4_interconnect_verb.rb +4 -2
  41. data/lib/tdl/basefunc.rb +1 -0
  42. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -3
  43. data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
  44. data/lib/tdl/class_hdl/hdl_assign.rb +5 -3
  45. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +11 -9
  46. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  47. data/lib/tdl/class_hdl/hdl_function.rb +4 -2
  48. data/lib/tdl/class_hdl/hdl_generate.rb +5 -4
  49. data/lib/tdl/class_hdl/hdl_initial.rb +11 -10
  50. data/lib/tdl/class_hdl/hdl_module_def.rb +18 -1
  51. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +35 -14
  52. data/lib/tdl/class_hdl/hdl_struct.rb +1 -1
  53. data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
  54. data/lib/tdl/elements/originclass.rb +6 -1
  55. data/lib/tdl/elements/parameter.rb +1 -1
  56. data/lib/tdl/examples/10_random/exp_random.sv +3 -3
  57. data/lib/tdl/examples/11_test_unit/dve.tcl +155 -2
  58. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
  59. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  60. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
  61. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
  62. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
  63. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
  64. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
  65. data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
  66. data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
  67. data/lib/tdl/examples/1_define_module/exmple_md.sv +12 -12
  68. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
  69. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
  70. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
  71. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
  72. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
  73. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
  74. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
  75. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
  76. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
  77. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +2 -2
  78. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
  79. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -5
  80. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
  81. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
  82. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  83. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
  84. data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
  85. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
  86. data/lib/tdl/examples/7_module_with_package/body_package.sv +3 -4
  87. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +4 -4
  88. data/lib/tdl/examples/7_module_with_package/head_package.sv +3 -4
  89. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
  90. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +2 -2
  91. data/lib/tdl/examples/9_itegration/test_tttop.sv +3 -3
  92. data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
  93. data/lib/tdl/exlib/axis_verify.rb +264 -0
  94. data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
  95. data/lib/tdl/exlib/dve_tcl.rb +30 -11
  96. data/lib/tdl/exlib/itegration.rb +15 -3
  97. data/lib/tdl/exlib/logic_verify.rb +88 -0
  98. data/lib/tdl/exlib/test_point.rb +96 -94
  99. data/lib/tdl/exlib/test_point.rb.bak +293 -0
  100. data/lib/tdl/rebuild_ele/ele_base.rb +1 -1
  101. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
  102. data/lib/tdl/sdlmodule/sdlmodule.rb +18 -14
  103. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
  104. data/lib/tdl/sdlmodule/test_unit_module.rb +272 -33
  105. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
  106. data/lib/tdl/sdlmodule/top_module.rb +53 -48
  107. data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
  108. data/lib/tdl/tdl.rb +19 -4
  109. metadata +36 -137
  110. data/Gemfile.lock +0 -28
  111. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +0 -149
  112. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +0 -242
  113. data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -66
  114. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -48
  115. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -113
  116. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +0 -62
data/Rakefile CHANGED
@@ -1,4 +1,4 @@
1
- require "bundler/gem_tasks"
1
+ # require "bundler/gem_tasks"
2
2
  require "rake/clean"
3
3
  require "rake/testtask"
4
4
  require "fileutils"
@@ -10,9 +10,5 @@ Rake::TestTask.new(:test) do |t|
10
10
  t.libs << "lib/tdl"
11
11
  t.pattern = "test/*_test.rb"
12
12
  # t.ruby_opts = ["-c"]
13
- t.verbose = true
13
+ # t.verbose = true
14
14
  end
15
-
16
- task :old do
17
- exec 'ruby -I"lib:test" -I"/home/wmy367/.rvm/gems/ruby-2.6.3/gems/rake-10.5.0/lib" "/home/wmy367/.rvm/gems/ruby-2.6.3/gems/rake-10.5.0/lib/rake/rake_test_loader.rb" "test/*_test.rb" '
18
- end
data/axi_tdl.gemspec CHANGED
@@ -1,4 +1,3 @@
1
-
2
1
  lib = File.expand_path("../lib", __FILE__)
3
2
  $LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
4
3
  require "axi_tdl/version"
@@ -9,8 +8,8 @@ Gem::Specification.new do |spec|
9
8
  spec.authors = ["Cook.Darwin"]
10
9
  spec.email = ["cook_darwin@hotmail.com"]
11
10
 
12
- spec.summary = %q{Axi is a light weight axi library. Tdl is a hardware Construction language}
13
- spec.description = %q{tdl is a hardware Construction language, it like chisel, but more intresting. It is a DSL and base on ruby. Finally, it convert to systemverilog. }
11
+ spec.summary = %q{Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言}
12
+ spec.description = %q{tdl 是一种硬件构造语言, 和chisel类似, 但是更加有趣, 他是一种基于Ruby的DSL. 最终它会编译输出systemverilog 。 }
14
13
  spec.homepage = "https://www.github.com/CookDarwin/axi_tdl"
15
14
  # spec.homepage = "https://rubygems.org/gems/axi_tdl"
16
15
  spec.license = "LGPL-2.1"
@@ -35,9 +34,9 @@ Gem::Specification.new do |spec|
35
34
  spec.executables = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
36
35
  spec.require_paths = ["lib"]
37
36
 
38
- spec.add_development_dependency "bundler", "~> 1.16"
37
+ # spec.add_development_dependency "bundler", "~> 1.16"
39
38
  spec.add_development_dependency "rake", "~> 10.0"
40
39
  # spec.add_development_dependency "rspec"
41
- spec.add_development_dependency "pry"
42
- spec.add_development_dependency "minitest"
40
+ spec.add_development_dependency "pry","~> 0.11"
41
+ spec.add_development_dependency "minitest","~> 5.10"
43
42
  end
data/lib/axi/AXI4/axi4_direct_B1.sv CHANGED
@@ -12,61 +12,61 @@ madified:
12
12
  (* axi4 = "true" *)
13
13
  module axi4_direct_B1 (
14
14
  (* up_stream = "true" *)
15
- axi_inf.slaver slaver,
15
+ axi_inf.slaver slaver_inf,
16
16
  (* down_stream = "true" *)
17
- axi_inf.master master
17
+ axi_inf.master master_inf
18
18
  );
19
19
 
20
20
 
21
21
  generate
22
- if(slaver.MODE == "ONLY_READ" && master.MODE == "ONLY_READ")
22
+ if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "ONLY_READ")
23
23
  axi4_direct_A1 #(
24
24
  .MODE ("ONLY_READ_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
25
25
  )axi4_direct_inst_ONLY_READ_to_ONLY_READ(
26
- /* axi_inf.slaver */ .slaver (slaver ),
27
- /* axi_inf.master */ .master (master )
26
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
27
+ /* axi_inf.master */ .master (master_inf )
28
28
  );
29
- else if(slaver.MODE == "ONLY_READ" && master.MODE == "BOTH")
29
+ else if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "BOTH")
30
30
  axi4_direct_A1 #(
31
31
  .MODE ("ONLY_READ_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
32
32
  )axi4_direct_inst_ONLY_READ_to_BOTH(
33
- /* axi_inf.slaver */ .slaver (slaver ),
34
- /* axi_inf.master */ .master (master )
33
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
34
+ /* axi_inf.master */ .master (master_inf )
35
35
  );
36
- else if(slaver.MODE == "ONLY_WRITE" && master.MODE == "BOTH")
36
+ else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "BOTH")
37
37
  axi4_direct_A1 #(
38
38
  .MODE ("ONLY_WRITE_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
39
39
  )axi4_direct_inst_ONLY_WRITE_to_BOTH(
40
- /* axi_inf.slaver */ .slaver (slaver ),
41
- /* axi_inf.master */ .master (master )
40
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
41
+ /* axi_inf.master */ .master (master_inf )
42
42
  );
43
- else if(slaver.MODE == "ONLY_WRITE" && master.MODE == "ONLY_WRITE")
43
+ else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "ONLY_WRITE")
44
44
  axi4_direct_A1 #(
45
45
  .MODE ("ONLY_WRITE_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
46
46
  )axi4_direct_inst_ONLY_WRITE_to_ONLY_WRITE(
47
- /* axi_inf.slaver */ .slaver (slaver ),
48
- /* axi_inf.master */ .master (master )
47
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
48
+ /* axi_inf.master */ .master (master_inf )
49
49
  );
50
- else if(slaver.MODE == "BOTH" && master.MODE == "ONLY_WRITE")
50
+ else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_WRITE")
51
51
  axi4_direct_A1 #(
52
52
  .MODE ("BOTH_to_ONLY_WRITE") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
53
53
  )axi4_direct_inst_BOTH_to_ONLY_WRITE(
54
- /* axi_inf.slaver */ .slaver (slaver ),
55
- /* axi_inf.master */ .master (master )
54
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
55
+ /* axi_inf.master */ .master (master_inf )
56
56
  );
57
- else if(slaver.MODE == "BOTH" && master.MODE == "ONLY_READ")
57
+ else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_READ")
58
58
  axi4_direct_A1 #(
59
59
  .MODE ("BOTH_to_ONLY_READ") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
60
60
  )axi4_direct_inst_BOTH_to_ONLY_READ(
61
- /* axi_inf.slaver */ .slaver (slaver ),
62
- /* axi_inf.master */ .master (master )
61
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
62
+ /* axi_inf.master */ .master (master_inf )
63
63
  );
64
- else if(slaver.MODE == "BOTH" && master.MODE == "BOTH")
64
+ else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "BOTH")
65
65
  axi4_direct_A1 #(
66
66
  .MODE ("BOTH_to_BOTH") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
67
67
  )axi4_direct_inst_BOTH_to_BOTH(
68
- /* axi_inf.slaver */ .slaver (slaver ),
69
- /* axi_inf.master */ .master (master )
68
+ /* axi_inf.slaver */ .slaver (slaver_inf ),
69
+ /* axi_inf.master */ .master (master_inf )
70
70
  );
71
71
 
72
72
  endgenerate
data/lib/axi/AXI4/axi4_dpram_cache.sv CHANGED
@@ -20,7 +20,7 @@ module axi4_dpram_cache #(
20
20
  //==========================================================================
21
21
  //-------- define ----------------------------------------------------------
22
22
 
23
- cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE( a_inf.DSIZE/8)) xram_inf();
23
+ cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(a_inf.DSIZE/8)) xram_inf();
24
24
  axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
25
25
  axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
26
26
  data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
@@ -69,44 +69,44 @@ common_ram_wrapper #(
69
69
  //==========================================================================
70
70
  //-------- expression ------------------------------------------------------
71
71
  initial begin
72
- assert( a_inf.ASIZE==b_inf.ASIZE)else begin
73
- $error("a_inf.ASIZE != b_inf.ASIZE");
74
- $stop;
72
+ assert(a_inf.ASIZE==b_inf.ASIZE)else begin
73
+ $error("a_inf.ASIZE != b_inf.ASIZE");
74
+ $stop;
75
75
  end
76
- assert( a_inf.DSIZE==b_inf.DSIZE)else begin
77
- $error("a_inf.ASIZE != b_inf.ASIZE");
78
- $stop;
76
+ assert(a_inf.DSIZE==b_inf.DSIZE)else begin
77
+ $error("a_inf.ASIZE != b_inf.ASIZE");
78
+ $stop;
79
79
  end
80
80
  end
81
81
 
82
- assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]);
83
- assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
84
- assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1];
82
+ assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]);
83
+ assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
84
+ assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1];
85
85
 
86
- assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
87
- assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[ a_inf.DSIZE-1:0];
88
- assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[ a_inf.ASIZE+a_inf.DSIZE+1-1];
89
- assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
90
- assign xram_inf.addra = a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
91
- assign xram_inf.dia = a_axis_inf.axis_tdata[ a_inf.DSIZE-1:0];
92
- assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]}};
93
- assign xram_inf.ena = 1'b1;
94
- assign xram_inf.clka = a_inf.axi_aclk;
95
- assign xram_inf.rsta = ~a_inf.axi_aresetn;
86
+ assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
87
+ assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[a_inf.DSIZE-1:0];
88
+ assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[a_inf.ASIZE+a_inf.DSIZE+1-1];
89
+ assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
90
+ assign xram_inf.addra = a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
91
+ assign xram_inf.dia = a_axis_inf.axis_tdata[a_inf.DSIZE-1:0];
92
+ assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]}};
93
+ assign xram_inf.ena = 1'b1;
94
+ assign xram_inf.clka = a_inf.axi_aclk;
95
+ assign xram_inf.rsta = ~a_inf.axi_aresetn;
96
96
 
97
- assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]);
98
- assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
99
- assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1];
97
+ assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]);
98
+ assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
99
+ assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1];
100
100
 
101
- assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
102
- assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[ b_inf.DSIZE-1:0];
103
- assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[ b_inf.ASIZE+b_inf.DSIZE+1-1];
104
- assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
105
- assign xram_inf.addrb = b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
106
- assign xram_inf.dib = b_axis_inf.axis_tdata[ b_inf.DSIZE-1:0];
107
- assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]}};
108
- assign xram_inf.enb = 1'b1;
109
- assign xram_inf.clkb = b_inf.axi_aclk;
110
- assign xram_inf.rstb = ~b_inf.axi_aresetn;
101
+ assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
102
+ assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[b_inf.DSIZE-1:0];
103
+ assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[b_inf.ASIZE+b_inf.DSIZE+1-1];
104
+ assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
105
+ assign xram_inf.addrb = b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
106
+ assign xram_inf.dib = b_axis_inf.axis_tdata[b_inf.DSIZE-1:0];
107
+ assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]}};
108
+ assign xram_inf.enb = 1'b1;
109
+ assign xram_inf.clkb = b_inf.axi_aclk;
110
+ assign xram_inf.rstb = ~b_inf.axi_aresetn;
111
111
 
112
112
  endmodule
data/lib/axi/AXI4/axis_to_axi4_wr.rb CHANGED
@@ -6,6 +6,7 @@ require_hdl 'axis_length_split_with_addr.sv'
6
6
  require_hdl 'axi_stream_long_fifo.sv'
7
7
  require_hdl 'axi4_wr_auxiliary_gen_without_resp.sv'
8
8
  require_hdl 'axis_valve_with_pipe.sv'
9
+ require_hdl 'independent_clock_fifo.sv'
9
10
 
10
11
  new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
11
12
 
data/lib/axi/AXI4/axis_to_axi4_wr.sv CHANGED
@@ -56,7 +56,7 @@ logic stream_en;
56
56
  axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
57
  axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
58
  axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
- axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1264 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
59
+ axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1977 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
60
  axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
61
61
  //==========================================================================
62
62
  //-------- instance --------------------------------------------------------
@@ -94,13 +94,13 @@ independent_clock_fifo #(
94
94
  axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
95
95
  /* output */.stream_en (stream_en ),
96
96
  /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
97
- /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1264 )
97
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1977 )
98
98
  );
99
99
  vcs_axi4_comptable #(
100
100
  .ORIGIN ("master_wr_aux_no_resp" ),
101
101
  .TO ("master_wr" )
102
- )vcs_axi4_comptable_axi_wr_aux_R858_axi_wr_inst(
103
- /* input */.origin (axi_wr_vcs_cp_R1264 ),
102
+ )vcs_axi4_comptable_axi_wr_aux_R874_axi_wr_inst(
103
+ /* input */.origin (axi_wr_vcs_cp_R1977 ),
104
104
  /* output */.to (axi_wr )
105
105
  );
106
106
  axis_valve_with_pipe #(
@@ -112,30 +112,30 @@ axis_valve_with_pipe #(
112
112
  );
113
113
  //==========================================================================
114
114
  //-------- expression ------------------------------------------------------
115
- always_ff@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
115
+ always@(posedge axis_in.aclk,negedge axis_in.aresetn) begin
116
116
  if(~axis_in.aresetn)begin
117
- id <= 0;
117
+ id <= 0;
118
118
  end
119
119
  else if(split_out.axis_tvalid && split_out.axis_tready && split_out.axis_tlast)begin
120
- id <= ( id+1);
120
+ id <= (id+1);
121
121
  end
122
122
  else begin
123
- id <= id;
123
+ id <= id;
124
124
  end
125
125
  end
126
126
 
127
- assign addr_s = addr_cur;
128
- assign len_s = split_out.axis_tcnt;
129
- assign id_add_len_in.axis_tvalid = ~fifo_empty;
130
- assign id_add_len_in.axis_tdata = fifo_rdata;
131
- assign id_add_len_in.axis_tlast = "1'b1";
132
- assign rd_en = id_add_len_in.axis_tready;
127
+ assign addr_s = addr_cur;
128
+ assign len_s = split_out.axis_tcnt;
129
+ assign id_add_len_in.axis_tvalid = ~fifo_empty;
130
+ assign id_add_len_in.axis_tdata = fifo_rdata;
131
+ assign id_add_len_in.axis_tlast = "1'b1";
132
+ assign rd_en = id_add_len_in.axis_tready;
133
133
 
134
- assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
135
- assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
136
- assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
137
- assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
138
- assign axi_wr.axi_bready = 1'b1;
139
- assign pipe_axis.axis_tready = axi_wr.axi_wready;
134
+ assign axi_wr.axi_wdata = pipe_axis.axis_tdata;
135
+ assign axi_wr.axi_wstrb = ~pipe_axis.axis_tkeep;
136
+ assign axi_wr.axi_wvalid = pipe_axis.axis_tvalid;
137
+ assign axi_wr.axi_wlast = pipe_axis.axis_tlast;
138
+ assign axi_wr.axi_bready = 1'b1;
139
+ assign pipe_axis.axis_tready = axi_wr.axi_wready;
140
140
 
141
141
  endmodule
data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv CHANGED
@@ -44,49 +44,49 @@ common_fifo #(
44
44
  .DEPTH (6 ),
45
45
  .DSIZE (1 )
46
46
  )common_fifo_inst(
47
- /* input */.clock (clock ),
48
- /* input */.rst_n (rst_n ),
49
- /* input */.wdata (partition_pulse_inf.data ),
50
- /* input */.wr_en (partition_pulse_inf.valid && partition_pulse_inf.ready ),
51
- /* output */.rdata ( ),
52
- /* input */.rd_en ( (short_inf.axi_rvalid & short_inf.axi_rready)&short_inf.axi_rlast ),
53
- /* output */.count (/*unused */ ),
54
- /* output */.empty (fifo_empty ),
55
- /* output */.full (fifo_full )
47
+ /* input */.clock (clock ),
48
+ /* input */.rst_n (rst_n ),
49
+ /* input */.wdata (partition_pulse_inf.data ),
50
+ /* input */.wr_en (partition_pulse_inf.valid && partition_pulse_inf.ready ),
51
+ /* output */.rdata ( ),
52
+ /* input */.rd_en ((short_inf.axi_rvalid & short_inf.axi_rready)&short_inf.axi_rlast ),
53
+ /* output */.count (/*unused */ ),
54
+ /* output */.empty (fifo_empty ),
55
+ /* output */.full (fifo_full )
56
56
  );
57
57
  //==========================================================================
58
58
  //-------- expression ------------------------------------------------------
59
- assign clock = long_inf.axi_aclk;
60
- assign rst_n = long_inf.axi_aresetn;
59
+ assign clock = long_inf.axi_aclk;
60
+ assign rst_n = long_inf.axi_aresetn;
61
61
 
62
- assign pre_partition_data_inf.data = {long_inf.axi_arid,long_inf.axi_araddr,long_inf.axi_arlen};
63
- assign pre_partition_data_inf.valid = long_inf.axi_arvalid;
64
- assign long_inf.axi_arready = pre_partition_data_inf.ready;
65
- assign {short_inf.axi_arid,short_inf.axi_araddr,short_inf.axi_arlen} = post_partition_data_inf.data;
66
- assign short_inf.axi_arvalid = post_partition_data_inf.valid;
67
- assign post_partition_data_inf.ready = short_inf.axi_arready;
62
+ assign pre_partition_data_inf.data = {long_inf.axi_arid,long_inf.axi_araddr,long_inf.axi_arlen};
63
+ assign pre_partition_data_inf.valid = long_inf.axi_arvalid;
64
+ assign long_inf.axi_arready = pre_partition_data_inf.ready;
65
+ assign {short_inf.axi_arid,short_inf.axi_araddr,short_inf.axi_arlen} = post_partition_data_inf.data;
66
+ assign short_inf.axi_arvalid = post_partition_data_inf.valid;
67
+ assign post_partition_data_inf.ready = short_inf.axi_arready;
68
68
 
69
- assign partition_pulse_inf.ready = ~fifo_full;
69
+ assign partition_pulse_inf.ready = ~fifo_full;
70
70
 
71
- assign short_inf.axi_arsize = long_inf.axi_arsize;
72
- assign short_inf.axi_arburst = long_inf.axi_arburst;
73
- assign short_inf.axi_arlock = long_inf.axi_arlock;
74
- assign short_inf.axi_arcache = long_inf.axi_arcache;
75
- assign short_inf.axi_arprot = long_inf.axi_arprot;
76
- assign short_inf.axi_arqos = long_inf.axi_arqos;
77
- assign long_inf.axi_rid = short_inf.axi_rid[ long_inf.IDSIZE-1:0];
78
- assign long_inf.axi_rdata = short_inf.axi_rdata;
79
- assign long_inf.axi_rresp = short_inf.axi_rresp;
80
- assign long_inf.axi_rlast = ( short_inf.axi_rlast&fifo_empty);
81
- assign long_inf.axi_rvalid = short_inf.axi_rvalid;
82
- assign short_inf.axi_rready = long_inf.axi_rready;
71
+ assign short_inf.axi_arsize = long_inf.axi_arsize;
72
+ assign short_inf.axi_arburst = long_inf.axi_arburst;
73
+ assign short_inf.axi_arlock = long_inf.axi_arlock;
74
+ assign short_inf.axi_arcache = long_inf.axi_arcache;
75
+ assign short_inf.axi_arprot = long_inf.axi_arprot;
76
+ assign short_inf.axi_arqos = long_inf.axi_arqos;
77
+ assign long_inf.axi_rid = short_inf.axi_rid[long_inf.IDSIZE-1:0];
78
+ assign long_inf.axi_rdata = short_inf.axi_rdata;
79
+ assign long_inf.axi_rresp = short_inf.axi_rresp;
80
+ assign long_inf.axi_rlast = short_inf.axi_rlast&fifo_empty;
81
+ assign long_inf.axi_rvalid = short_inf.axi_rvalid;
82
+ assign short_inf.axi_rready = long_inf.axi_rready;
83
83
 
84
84
  always_ff@(posedge clock,negedge rst_n) begin
85
85
  if(~rst_n)begin
86
- wait_last_inf.ready <= 1'b0;
86
+ wait_last_inf.ready <= 1'b0;
87
87
  end
88
88
  else begin
89
- wait_last_inf.ready <= ( ( long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
89
+ wait_last_inf.ready <= ((long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
90
90
  end
91
91
  end
92
92
 
data/lib/axi/AXI4/packet_partition/data_inf_partition.rb CHANGED
@@ -1,3 +1,5 @@
1
+ require_hdl 'common_fifo.sv'
2
+
1
3
  TdlBuild.data_inf_partition(__dir__) do
2
4
  parameter.PLEN 128
3
5
  parameter.LSIZE 8
data/lib/axi/AXI4/packet_partition/data_inf_partition.sv CHANGED
@@ -29,9 +29,9 @@ logic rst_n;
29
29
  logic tail_len;
30
30
  logic one_long_stream;
31
31
  logic fifo_wr;
32
- logic [ IDSIZE+4-1:0] curr_id ;
32
+ logic [IDSIZE+4-1:0] curr_id ;
33
33
  logic [LSIZE-1:0] curr_length ;
34
- logic [ ( data_in.DSIZE-IDSIZE)-LSIZE-1:0] curr_addr ;
34
+ logic [(data_in.DSIZE-IDSIZE)-LSIZE-1:0] curr_addr ;
35
35
  logic [LSIZE-1:0] wr_length ;
36
36
  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
37
37
  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
@@ -68,21 +68,21 @@ typedef enum {
68
68
  } SE_STATE_ps;
69
69
  SE_STATE_ps CSTATE_ps,NSTATE_ps;
70
70
  initial begin
71
- assert( ( data_in.DSIZE+4)==data_out.DSIZE)else begin
72
- $error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
73
- $stop;
71
+ assert((data_in.DSIZE+4)==data_out.DSIZE)else begin
72
+ $error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
73
+ $stop;
74
74
  end
75
75
  end
76
76
 
77
- assign clock = data_in.clock;
78
- assign rst_n = data_in.rst_n;
77
+ assign clock = data_in.clock;
78
+ assign rst_n = data_in.rst_n;
79
79
 
80
80
  always_ff@(posedge clock,negedge rst_n) begin
81
81
  if(~rst_n)begin
82
- CSTATE_ps <= IDLE;
82
+ CSTATE_ps <= IDLE;
83
83
  end
84
84
  else begin
85
- CSTATE_ps <= NSTATE_ps;
85
+ CSTATE_ps <= NSTATE_ps;
86
86
  end
87
87
  end
88
88
 
@@ -90,85 +90,85 @@ always_comb begin
90
90
  case(CSTATE_ps)
91
91
  IDLE:begin
92
92
  if(data_in.valid && data_in.ready)begin
93
- NSTATE_ps = LOCK;
93
+ NSTATE_ps = LOCK;
94
94
  end
95
95
  else begin
96
- NSTATE_ps = IDLE;
96
+ NSTATE_ps = IDLE;
97
97
  end
98
98
  end
99
99
  LOCK:begin
100
100
  if(one_long_stream)begin
101
- NSTATE_ps = Pl;
101
+ NSTATE_ps = Pl;
102
102
  end
103
103
  else begin
104
- NSTATE_ps = WAT_PP;
104
+ NSTATE_ps = WAT_PP;
105
105
  end
106
106
  end
107
107
  WAT_PP:begin
108
108
  if(partition_pulse_inf.valid && partition_pulse_inf.ready)begin
109
- NSTATE_ps = Px;
109
+ NSTATE_ps = Px;
110
110
  end
111
111
  else begin
112
- NSTATE_ps = WAT_PP;
112
+ NSTATE_ps = WAT_PP;
113
113
  end
114
114
  end
115
115
  Px:begin
116
116
  if(~fifo_full)begin
117
- NSTATE_ps = HOLD;
117
+ NSTATE_ps = HOLD;
118
118
  end
119
119
  else begin
120
- NSTATE_ps = Px;
120
+ NSTATE_ps = Px;
121
121
  end
122
122
  end
123
123
  HOLD:begin
124
124
  if(tail_len)begin
125
- NSTATE_ps = Pl;
125
+ NSTATE_ps = Pl;
126
126
  end
127
127
  else begin
128
- NSTATE_ps = WAT_PP;
128
+ NSTATE_ps = WAT_PP;
129
129
  end
130
130
  end
131
131
  Pl:begin
132
132
  if(~fifo_full)begin
133
- NSTATE_ps = DONE;
133
+ NSTATE_ps = DONE;
134
134
  end
135
135
  else begin
136
- NSTATE_ps = Pl;
136
+ NSTATE_ps = Pl;
137
137
  end
138
138
  end
139
139
  DONE:begin
140
140
  if(fifo_empty)begin
141
- NSTATE_ps = WAIT;
141
+ NSTATE_ps = WAIT;
142
142
  end
143
143
  else begin
144
- NSTATE_ps = DONE;
144
+ NSTATE_ps = DONE;
145
145
  end
146
146
  end
147
147
  WAIT:begin
148
148
  if(wait_last_inf.valid && wait_last_inf.ready)begin
149
- NSTATE_ps = IDLE;
149
+ NSTATE_ps = IDLE;
150
150
  end
151
151
  else begin
152
- NSTATE_ps = WAIT;
152
+ NSTATE_ps = WAIT;
153
153
  end
154
154
  end
155
155
  default:begin
156
- NSTATE_ps = IDLE;
156
+ NSTATE_ps = IDLE;
157
157
  end
158
158
  endcase
159
159
  end
160
160
 
161
161
  always_ff@(posedge clock,negedge rst_n) begin
162
162
  if(~rst_n)begin
163
- data_in.ready <= 1'b0;
163
+ data_in.ready <= 1'b0;
164
164
  end
165
165
  else begin
166
166
  case(NSTATE_ps)
167
167
  IDLE:begin
168
- data_in.ready <= 1'b1;
168
+ data_in.ready <= 1'b1;
169
169
  end
170
170
  default:begin
171
- data_in.ready <= 1'b0;
171
+ data_in.ready <= 1'b0;
172
172
  end
173
173
  endcase
174
174
  end
@@ -176,23 +176,23 @@ end
176
176
 
177
177
  always_ff@(posedge clock,negedge rst_n) begin
178
178
  if(~rst_n)begin
179
- curr_addr <= '0;
180
- curr_length <= '0;
179
+ curr_addr <= '0;
180
+ curr_length <= '0;
181
181
  end
182
182
  else begin
183
183
  case(NSTATE_ps)
184
184
  LOCK:begin
185
- one_long_stream <= data_in.data[ LSIZE-1:0]< PLEN;
186
- curr_id[ IDSIZE+4-1:IDSIZE] <= 2'b00;
187
- {curr_id[ IDSIZE-1:0],curr_addr,curr_length} <= data_in.data;
185
+ one_long_stream <= data_in.data[LSIZE-1:0]<PLEN;
186
+ curr_id[IDSIZE+4-1:IDSIZE] <= 2'b00;
187
+ {curr_id[IDSIZE-1:0],curr_addr,curr_length} <= data_in.data;
188
188
  end
189
189
  HOLD:begin
190
- curr_length <= ( curr_length-PLEN);
191
- curr_addr <= ( curr_addr+( ADDR_STEP*PLEN/1024));
192
- curr_id[ IDSIZE+4-1:IDSIZE] <= ( curr_id[ IDSIZE+2-1:IDSIZE]+1'b1);
190
+ curr_length <= (curr_length-PLEN);
191
+ curr_addr <= (curr_addr+(ADDR_STEP*PLEN/1024));
192
+ curr_id[IDSIZE+4-1:IDSIZE] <= (curr_id[IDSIZE+2-1:IDSIZE]+1'b1);
193
193
  end
194
194
  IDLE,DONE:begin
195
- one_long_stream <= 1'b0;
195
+ one_long_stream <= 1'b0;
196
196
  end
197
197
  endcase
198
198
  end
@@ -200,19 +200,19 @@ end
200
200
 
201
201
  always_ff@(posedge clock,negedge rst_n) begin
202
202
  if(~rst_n)begin
203
- tail_len <= 1'b0;
203
+ tail_len <= 1'b0;
204
204
  end
205
205
  else begin
206
206
  case(NSTATE_ps)
207
207
  LOCK:begin
208
- tail_len <= ( data_in.data[ LSIZE-1:0]<PLEN);
208
+ tail_len <= (data_in.data[LSIZE-1:0]<PLEN);
209
209
  end
210
210
  HOLD:begin
211
- if( curr_length<( PLEN*2-0))begin
212
- tail_len <= 1'b1;
211
+ if(curr_length<(PLEN*2-0))begin
212
+ tail_len <= 1'b1;
213
213
  end
214
214
  else begin
215
- tail_len <= 1'b0;
215
+ tail_len <= 1'b0;
216
216
  end
217
217
  end
218
218
  endcase
@@ -221,21 +221,21 @@ end
221
221
 
222
222
  always_ff@(posedge clock,negedge rst_n) begin
223
223
  if(~rst_n)begin
224
- wr_length <= '0;
225
- fifo_wr <= 1'b0;
224
+ wr_length <= '0;
225
+ fifo_wr <= 1'b0;
226
226
  end
227
227
  else begin
228
228
  case(NSTATE_ps)
229
229
  Px:begin
230
- wr_length <= ( PLEN-1'b1);
231
- fifo_wr <= 1'b1;
230
+ wr_length <= (PLEN-1'b1);
231
+ fifo_wr <= 1'b1;
232
232
  end
233
233
  Pl:begin
234
- wr_length <= curr_length;
235
- fifo_wr <= 1'b1;
234
+ wr_length <= curr_length;
235
+ fifo_wr <= 1'b1;
236
236
  end
237
237
  default:begin
238
- fifo_wr <= 1'b0;
238
+ fifo_wr <= 1'b0;
239
239
  end
240
240
  endcase
241
241
  end
@@ -243,39 +243,39 @@ end
243
243
 
244
244
  always_ff@(posedge clock,negedge rst_n) begin
245
245
  if(~rst_n)begin
246
- partition_pulse_inf.valid <= 1'b0;
247
- partition_pulse_inf.data <= '0;
246
+ partition_pulse_inf.valid <= 1'b0;
247
+ partition_pulse_inf.data <= '0;
248
248
  end
249
249
  else begin
250
250
  case(NSTATE_ps)
251
251
  WAT_PP:begin
252
- partition_pulse_inf.valid <= 1'b1;
253
- partition_pulse_inf.data <= '0;
252
+ partition_pulse_inf.valid <= 1'b1;
253
+ partition_pulse_inf.data <= '0;
254
254
  end
255
255
  default:begin
256
- partition_pulse_inf.valid <= 1'b0;
257
- partition_pulse_inf.data <= '0;
256
+ partition_pulse_inf.valid <= 1'b0;
257
+ partition_pulse_inf.data <= '0;
258
258
  end
259
259
  endcase
260
260
  end
261
261
  end
262
262
 
263
- assign data_out.valid = ~fifo_empty;
263
+ assign data_out.valid = ~fifo_empty;
264
264
 
265
265
  always_ff@(posedge clock,negedge rst_n) begin
266
266
  if(~rst_n)begin
267
- wait_last_inf.data <= '0;
268
- wait_last_inf.valid <= '0;
267
+ wait_last_inf.data <= '0;
268
+ wait_last_inf.valid <= '0;
269
269
  end
270
270
  else begin
271
271
  case(NSTATE_ps)
272
272
  WAIT:begin
273
- wait_last_inf.data <= '0;
274
- wait_last_inf.valid <= 1'b1;
273
+ wait_last_inf.data <= '0;
274
+ wait_last_inf.valid <= 1'b1;
275
275
  end
276
276
  default:begin
277
- wait_last_inf.data <= '0;
278
- wait_last_inf.valid <= 1'b0;
277
+ wait_last_inf.data <= '0;
278
+ wait_last_inf.valid <= 1'b0;
279
279
  end
280
280
  endcase
281
281
  end
@@ -283,22 +283,22 @@ end
283
283
 
284
284
  always_ff@(posedge clock,negedge rst_n) begin
285
285
  if(~rst_n)begin
286
- st5_cnt <= '0;
287
- track_st5 <= 1'b0;
286
+ st5_cnt <= '0;
287
+ track_st5 <= 1'b0;
288
288
  end
289
289
  else begin
290
290
  case(NSTATE_ps)
291
291
  WAT_PP:begin
292
- st5_cnt <= ( st5_cnt+1'b1);
293
- track_st5 <= st5_cnt> 10'd200;
292
+ st5_cnt <= (st5_cnt+1'b1);
293
+ track_st5 <= st5_cnt>10'd200;
294
294
  end
295
295
  WAIT:begin
296
- st5_cnt <= ( st5_cnt+1'b1);
297
- track_st5 <= st5_cnt> 10'd1000;
296
+ st5_cnt <= (st5_cnt+1'b1);
297
+ track_st5 <= st5_cnt>10'd1000;
298
298
  end
299
299
  default:begin
300
- st5_cnt <= '0;
301
- track_st5 <= 1'b0;
300
+ st5_cnt <= '0;
301
+ track_st5 <= 1'b0;
302
302
  end
303
303
  endcase
304
304
  end