axi_tdl 0.0.9 → 0.0.19

data/lib/axi/techbench/tb_axis_split_channel_verb.sv

@@ -0,0 +1,125 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module tb_axis_split_channel_verb ();
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock;
+logic  rst_n;
+logic [16-1:0]  split_len ;
+logic [32-1:0]  first_inf_rdy_percetage_index ;
+logic [32-1:0]  first_inf_rdy_percetage[2-1:0] ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) origin_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) first_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+axi_stream_inf #(.DSIZE(8),.USIZE(1)) end_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_split_channel_verb axis_split_channel_verb_inst(
+/* input                 */.split_len  (split_len  ),
+/* axi_stream_inf.slaver */.origin_inf (origin_inf ),
+/* axi_stream_inf.master */.first_inf  (first_inf  ),
+/* axi_stream_inf.master */.end_inf    (end_inf    )
+);
+logic_sim_model #(
+    .LOOP      ("TRUE" ),
+    .DSIZE     (16     ),
+    .RAM_DEPTH (4      )
+)split_len_sim_model_inst(
+/* input  */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast            ),
+/* input  */.next_at_posedge_of (1'b0                                                                                 ),
+/* input  */.load_trigger       (1'b0                                                                                 ),
+/* input  */.total_length       (4                                                                                    ),
+/* input  */.mem_file           ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/split_len_R372.coe" ),
+/* output */.data               (split_len                                                                            )
+);
+axis_sim_master_model #(
+    .LOOP      ("TRUE" ),
+    .RAM_DEPTH (246    )
+)sim_model_inst_origin_inf(
+/* input                 */.load_trigger (1'b0                                                                                  ),
+/* input                 */.total_length (246                                                                                   ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/origin_inf_R994.coe" ),
+/* axi_stream_inf.master */.out_inf      (origin_inf                                                                            )
+);
+axis_sim_verify_by_coe #(
+    .RAM_DEPTH   (21    ),
+    .VERIFY_KEEP ("OFF" ),
+    .VERIFY_USER ("OFF" )
+)axis_sim_verify_by_coe_inst_first_inf(
+/* input                 */.load_trigger (1'b0                                                                                 ),
+/* input                 */.total_length (21                                                                                   ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/first_inf_R285.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (first_inf                                                                            )
+);
+axis_sim_verify_by_coe #(
+    .RAM_DEPTH   (118   ),
+    .VERIFY_KEEP ("OFF" ),
+    .VERIFY_USER ("OFF" )
+)axis_sim_verify_by_coe_inst_end_inf(
+/* input                 */.load_trigger (1'b0                                                                                ),
+/* input                 */.total_length (118                                                                                 ),
+/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/end_inf_R1971.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (end_inf                                                                             )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+initial begin
+     clock = 1'b0;
+     #(100ns);
+     forever begin #(5.0ns);clock = ~clock;end;
+end
+
+initial begin
+     rst_n = 1'b0;
+     #(200ns);
+     rst_n = ~rst_n;
+end
+
+initial begin
+     first_inf_rdy_percetage_index = 0;
+     first_inf_rdy_percetage[0] = 100;
+     first_inf_rdy_percetage[1] = 50;
+end
+
+always@(posedge clock) begin 
+    if(first_inf.axis_tvalid && first_inf.axis_tready && first_inf.axis_tlast)begin
+        if( first_inf_rdy_percetage_index>=( 2-1))begin
+             first_inf_rdy_percetage_index <= 0;
+        end
+        else begin
+             first_inf_rdy_percetage_index <= ( first_inf_rdy_percetage_index+1'b1);
+        end
+    end
+    else begin
+         first_inf_rdy_percetage_index <= first_inf_rdy_percetage_index;
+    end
+end
+
+always@(posedge clock) begin 
+    if(~rst_n)begin
+         first_inf.axis_tready <= 1'b0;
+    end
+    else begin
+         first_inf.axis_tready <= ($urandom_range(0,99) <= first_inf_rdy_percetage[first_inf_rdy_percetage_index]);
+    end
+end
+
+always@(posedge clock) begin 
+    if(~rst_n)begin
+         end_inf.axis_tready <= 1'b0;
+    end
+    else begin
+         end_inf.axis_tready <= ($urandom_range(0,99) <= 50);
+    end
+end
+
+endmodule

data/lib/axi_tdl.rb

@@ -20,6 +20,7 @@ add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common_fifo"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common"))
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface")) 
 add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/techbench"))
 
 ## base require 
 require_hdl 'axis_master_empty.sv'

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.0.9"
+  VERSION = "0.0.19"
 end

data/lib/tdl/auto_script/autogensdl.rb

@@ -232,10 +232,21 @@ class AutoGenSdl
     end
 
     def gen_file
-        @autof = File.open(@autof_name,"w") do |f|
-            f.puts gen_head
-            f.puts gen_content
-            # f.puts "sm.origin_sv = true"
+        unless File.exist?(@autof_name) 
+            @autof = File.open(@autof_name,"w") do |f|
+                f.print gen_head
+                f.print gen_content
+                # f.puts "sm.origin_sv = true"
+            end
+        else 
+            _old_str  = File.open(@autof_name).read
+            _new_str = gen_head+gen_content
+            if _old_str != _new_str
+                @autof = File.open(@autof_name,"w") do |f|
+                    f.print _new_str
+                    # f.puts "sm.origin_sv = true"
+                end
+            end
         end
     end
 
@@ -255,7 +266,7 @@ self.path = File.expand_path(__FILE__)
     end
 
     def gen_content
-        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end"]).join("\n")
+        (@param_port_inst+@signals_ports_inst+@inf_ports_inst + ["end\n\n"]).join("\n")
     end
 
 

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -218,16 +218,18 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
+                require_hdl 'axi4_direct_B1.sv'
                 # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
                 belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
                     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                    h.slaver        lo
-                    h.master        "#{sub_name}[#{index}]".to_nq
+                    h.slaver_inf        lo
+                    h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
             else
                 los = short_only.pop
                 @_long_slim_to_wide.delete los
+                require_hdl 'axi4_combin_wr_rd_batch.sv'
                 if wr_lg
                     # Axi4.axi4_combin_wr_rd_batch(wr_slaver:lo,rd_slaver:los,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
                     belong_to_module.Instance(:axi4_combin_wr_rd_batch,"axi4_combin_wr_rd_batch_inst_#{sub_name}") do |h|

data/lib/tdl/basefunc.rb

@@ -264,6 +264,7 @@ class Integer
     def clog2
         b = Math.log2(self)
         c = b.ceil
+        return c
     end
 
 end

data/lib/tdl/class_hdl/hdl_always_comb.rb

@@ -3,9 +3,10 @@ module ClassHDL
 
     class HDLAlwaysCombBlock 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance
@@ -28,7 +29,7 @@ module ClassHDL
     end
 
     def self.AlwaysComb(sdl_m,&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysCombBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysCombBlock.new(sdl_m)) do |ab|
             AssignDefOpertor.with_rollback_opertors(:new,&block)
             # return ClassHDL::AssignDefOpertor.curr_assign_block
             AssignDefOpertor.with_rollback_opertors(:old) do

data/lib/tdl/class_hdl/hdl_always_ff.rb

@@ -30,14 +30,14 @@ module ClassHDL
     class ClassNegedge < ClassEdge
     end
 
-
-    class HDLAlwaysFFBlock 
+    class HDLAlwaysBlock 
         attr_accessor :opertor_chains,:posedges,:negedges
-
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
             @posedges = []
             @negedges = []
+            @belong_to_module = belong_to_module
         end
 
         def edge_instance(flag='posedge',edges=[])
@@ -50,6 +50,32 @@ module ClassHDL
             return es.map{|e| "#{flag} #{e.to_s}"}
         end
 
+        def instance
+            str = []
+
+            pose_str = edge_instance('posedge',@posedges)
+            nege_str = edge_instance('negedge',@negedges)
+            pose_str.concat nege_str
+
+            str.push "always@(#{pose_str.join(",")}) begin "
+            opertor_chains.each do |op|
+                unless op.is_a? OpertorChain
+                    str.push op.instance(:always_ff).gsub(/^./){ |m| "    #{m}"}
+                else 
+                    unless op.slaver
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
+                        str.push "    #{rel_str};"
+                    end
+                end
+                
+            end
+            str.push "end\n"
+            str.join("\n")
+        end
+    end
+
+    class HDLAlwaysFFBlock < HDLAlwaysBlock
+
         def instance
             str = []
 
@@ -74,8 +100,21 @@ module ClassHDL
         end
     end
 
+    def self.Always(sdl_m: nil,posedge: [],negedge: [],&block)
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysBlock.new(sdl_m)) do |ab|
+            ab.posedges = posedge
+            ab.negedges = negedge
+
+            AssignDefOpertor.with_rollback_opertors(:new,&block)
+            # return ClassHDL::AssignDefOpertor.curr_assign_block
+            AssignDefOpertor.with_rollback_opertors(:old) do
+                sdl_m.Logic_draw.push ab.instance
+            end
+        end
+    end
+
     def self.AlwaysFF(sdl_m: nil,posedge: [],negedge: [],&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysFFBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysFFBlock.new(sdl_m)) do |ab|
             ab.posedges = posedge
             ab.negedges = negedge
 
@@ -116,7 +155,7 @@ module ClassHDL
     end
 
     def self.AlwaysSIM(sdl_m: nil,posedge: [],negedge: [],&block)
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysSIMBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAlwaysSIMBlock.new(sdl_m)) do |ab|
             ab.posedges = posedge
             ab.negedges = negedge
 
@@ -144,16 +183,18 @@ class SdlModule
     end
 
     def Always(posedge: nil,negedge: nil,&block)
-        ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
+        ClassHDL::Always(sdl_m: self,posedge: posedge,negedge: negedge,&block)
     end
 
+    alias_method :always, :Always
+
     def Always_ff(posedge: nil,negedge: nil,&block)
         ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block)
     end
 
     def always_ff(*args,&block)
         if args[0].is_a? Hash 
-            return Always(args[0],&block)
+            return Always(**args[0],&block)
         end 
         posedge_list = []
         negedge_list = [] 

data/lib/tdl/class_hdl/hdl_assign.rb

@@ -3,9 +3,11 @@ module ClassHDL
 
     class HDLAssignBlock 
         attr_accessor :opertor_chains
-
-        def initialize
+        attr_reader :belong_to_module
+        
+        def initialize(belong_to_module)
             @opertor_chains = []
+            @belong_to_module = belong_to_module
         end
 
         def instance
@@ -29,7 +31,7 @@ module ClassHDL
 
     def self.Assign(sdl_m,&block)
         # ClassHDL::AssignDefOpertor.curr_assign_block = ClassHDL::HDLAssignBlock.new
-        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignBlock.new) do |ab|
+        ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignBlock.new(sdl_m)) do |ab|
             AssignDefOpertor.with_rollback_opertors(:new,&block)
             # return ClassHDL::AssignDefOpertor.curr_assign_block
             AssignDefOpertor.with_rollback_opertors(:old) do 

data/lib/tdl/class_hdl/hdl_block_ifelse.rb

@@ -2,9 +2,11 @@ module ClassHDL
 
     class BlockIF
         attr_accessor :cond,:opertor_chains,:slaver
-        def initialize
+        attr_reader :belong_to_module
+        def initialize(belong_to_module)
             @opertor_chains = []
             @cond = nil
+            @belong_to_module = belong_to_module
         end
 
         def instance(as_type= :cond)
@@ -180,7 +182,7 @@ module ClassHDL
 end
 
 module ClassHDL
-    class EnumStruct
+    class EnumStruct < AxiTdl::SdlModuleActiveBaseElm
         # attr_accessor :sdl_m
         attr_accessor :belong_to_module
         def initialize(sdl_m,*args)
@@ -238,7 +240,7 @@ end
 class SdlModule
 
     def IF(cond,&block)
-        new_op = ClassHDL::BlockIF.new
+        new_op = ClassHDL::BlockIF.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -255,7 +257,7 @@ class SdlModule
     end
 
     def ELSIF(cond,&block)
-        new_op = ClassHDL::BlockELSIF.new
+        new_op = ClassHDL::BlockELSIF.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -272,7 +274,7 @@ class SdlModule
     end
 
     def ELSE(&block)
-        new_op = ClassHDL::BlockELSE.new
+        new_op = ClassHDL::BlockELSE.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -284,7 +286,7 @@ class SdlModule
     end
 
     def CASE(cond,&block)
-        new_op = ClassHDL::BlockCASE.new
+        new_op = ClassHDL::BlockCASE.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -301,7 +303,7 @@ class SdlModule
     end
 
     def CASEX(cond,&block)
-        new_op = ClassHDL::BlockCASEX.new
+        new_op = ClassHDL::BlockCASEX.new(self)
         # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
         #     new_op.slaver = true
         # end
@@ -318,7 +320,7 @@ class SdlModule
     end
 
     def WHEN(*cond,&block)
-        new_op = ClassHDL::BlockCASEWHEN.new
+        new_op = ClassHDL::BlockCASEWHEN.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
             if cond.is_a? ClassHDL::OpertorChain
@@ -333,7 +335,7 @@ class SdlModule
     end
 
     def DEFAULT(&block)
-        new_op = ClassHDL::BlockCASEDEFAULT.new
+        new_op = ClassHDL::BlockCASEDEFAULT.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
             block.call

data/lib/tdl/class_hdl/hdl_foreach.rb

@@ -55,7 +55,7 @@ class SdlModule
         ClassHDL::AssignDefOpertor.with_normal_opertor do 
             @@__foreach_index_cnt__ += 1
         end
-        new_op = ClassHDL::BlockFOREACH.new
+        new_op = ClassHDL::BlockFOREACH.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_opertor do 
             ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
@@ -81,7 +81,7 @@ class SdlModule
         ClassHDL::AssignDefOpertor.with_normal_opertor do 
             @@__for_index_cnt__ += 1
         end
-        new_op = ClassHDL::BlockFOR.new
+        new_op = ClassHDL::BlockFOR.new(self)
 
         ClassHDL::AssignDefOpertor.with_new_opertor do 
             ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|